CMOS Active Inductor Using G_m-Boosting Technique with Resistive Feedback and Its Broadband RF Application

Abstract

This paper presents a novel low-power, high-quality factor, and wide-tunable CMOS active inductor based on the gyrator-C configuration. The G_m-boosting technique is employed to reduce power consumption and noise while enhancing the transconductance. The inclusion of a feedback resistor further improves the quality factor. The designed active inductor operates up to 4.1 GHz, offers a wide inductance tuning range from 4.5 nH to 215 nH, consumes only 1.82 mW at 1.8 V supply, and occupies a compact area of 0.0006 mm². The input-referred current noise is as low as $27\mathrm{p}\mathrm{A}\sqrt{\mathrm{H}\mathrm{z}}$. This study aims to provide an effective solution to the large area requirements of traditional passive inductors, while simultaneously improving key performance parameters with minimal compromise by introducing a novel active inductor design. The proposed design also exhibits superior performance in key specifications compared with existing active inductor implementations. For demonstration purposes, the active inductor is incorporated into a broadband RF amplifier, achieving near-ideal behavior across the 0.8–2.1 GHz. Corner and Monte Carlo analyses, along with temperature sweep and stability analyses, were carried out to validate the reliability and robustness of the proposed design. Results confirm the effectiveness of the G_m-boosted active inductor for high-performance RF applications, making it a promising candidate for 5G and beyond future wireless communication systems.

1. Introduction

The growing demand for wireless communication technologies has accelerated research into RFIC design, particularly in CMOS technology, due to its cost efficiency and shrinking sizes. Numerous analog, RF, and mixed-signal circuits rely on intrinsically passive components such as inductors, capacitors, and resistors, which are essential in RF designs and are commonly used in matching networks, filters, phase shifters, voltage-controlled oscillators, biasing networks, etc. [1,2]. Among these components, inductors implemented in silicon CMOS processes present significant challenges [3,4,5,6]. Conventional on-chip passive inductors are typically realized as spiral structures and suffer from several inherent drawbacks, including low self-resonant frequency (SRF), limited inductance value, and large silicon area requirements [7]. Their quality factor tends to degrade significantly at lower frequencies due to increased substrate losses and parasitics, which arise from the larger component sizes. Additionally, their values can be imprecise, even in well-characterized processes, making them less desirable for high-performance RF applications. To overcome these limitations, active inductors (AIs) offer a more compact alternative to traditional passive spirals. CMOS AIs have gained considerable attention in the recent literature due to their smaller chip area, higher achievable inductance and SRF, continuous tunability, and improved quality factor [8,9,10,11,12,13]. These designs typically replicate inductive behavior using gyrator-based circuits, which consist of various configurations of NMOS and PMOS transistors and, in some cases, additional capacitors and resistors. However, AIs are subject to inherent noise and power dissipation from active devices, as well as performance degradation arising from process and supply variations.

Table 1. A comparison of passive inductors and active inductors.

Parameter	Active Inductors	Passive Inductors
Main difference	Realized using active elements like transistors and capacitors	Uses metal traces (spirals) or off-chip coils on silicon substrate
Size and integration	Area is small, suitable for high-density ICs, and decreases when transistor gate width decreases	Occupied area is large and increases when inductance increases
Linearity	Signal distortion when operating in large-signal regime	Superior linearity
Quality factor	High quality factor	Low quality factor
Tunability	Adjustable via transistor biasing	Fixed and non-tunable inductance value
Noise	Noise contribution is high and increases with decrease in device size	Low noise (due to no active elements)
Frequency range	High self-resonant frequency but requires careful stability management	Low self-resonant frequency due to parasitic capacitances and resistive losses
Cost	Higher due to complexity, but integration cost has its advantages	Lower fabrication cost but increases the overall IC cost due to its larger size
Power consumption	Consumption of overhead power	Does not need dc bias to work

provides a detailed comparison between passive and active CMOS inductors in terms of chip area, ease of integration, quality factor, tuning capability, etc.

In this study, the G_m-boosting technique is utilized to improve the performance of AIs, providing several advantages, such as an enhanced quality factor, lower power dissipation, and reduced noise [14,15]. The proposed active inductor (AI) is based on a gyrator-C configuration using the G_m-boosting technique in CMOS technology. A detailed small-signal analysis is provided, and simulation results are presented to verify the expected G_m-boosting effects. Furthermore, the proposed AI is demonstrated by using a broadband RF amplifier design for 5G and beyond applications, achieving near-ideal gain, input and output reflections, and noise figures across 0.8–2.1 GHz, illustrating its practical effectiveness.

The remainder of the paper is organized as follows: Section 2 presents the basic principles of CMOS active inductor design, the G_m-boosting mechanism, and the circuit analysis of the proposed active inductor. Design equations and small-signal analysis of the proposed active inductor are also discussed in this section, accompanied by a summary of the simulation results and comparisons with prior studies. Section 3 presents an example of the proposed active inductor used in a broadband RF amplifier, along with simulation results and comparisons to the ideal inductor case. Finally, Section 4 concludes the paper by reviewing the design challenges, trade-offs, and overall findings.

2. Proposed Active Inductor: Concept and Design

2.1. Basic Principles of Active Inductors

A gyrator, implemented using MOS transistors and capacitors, serves as the main building block of CMOS AIs, commonly referred to as a “gyrator-C” network [16,17,18]. The block diagram of a lossy single-ended gyrator-C network is shown in Figure 1a. As illustrated, the gyrator-C-based AI comprises two transconductances (one negative and one positive) connected in a loop, with a capacitor placed at the output port (node-A). In practice, both transconductances exhibit finite input and output impedances.

In Figure 1a, G_o1 and G_o2 represent the output and input conductances, while C₁ and C₂ denote the parasitic output and input capacitances, respectively. By applying Kirchhoff’s Current Law (KCL) to nodes A and B, the input admittance measured from node B can be expressed as follows:

$${\mathrm{Y}}_{\mathrm{i}\mathrm{n}}={\displaystyle \frac{{\mathrm{I}}_{\mathrm{i}\mathrm{n}}}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}}=\mathrm{s}{\mathrm{C}}_2+{\mathrm{G}}_{\mathrm{o}2}+{\displaystyle \frac{1}{\mathrm{s}\left(\frac{{\mathrm{C}}_1}{{\mathrm{G}}_{\mathrm{m}1}{\mathrm{G}}_{\mathrm{m}2}}\right)+\frac{{\mathrm{G}}_{\mathrm{o}1}}{{\mathrm{G}}_{\mathrm{m}1}{\mathrm{G}}_{\mathrm{m}2}}}}$$

(1)

Referring to (1), when the output conductance (G_o1) is sufficiently small and the parasitic input capacitance (C₂) and input conductance (G_o2) are negligible, the input impedance becomes purely inductive. However, in practical cases, the equivalent inductance introduces losses, which can be modeled as an RLC network, as illustrated in Figure 1b. Based on (1), the values of each component in the equivalent RLC circuit are determined as follows:

$${\mathrm{G}}_p={\mathrm{G}}_{\mathrm{o}2},{\mathrm{C}}_{\mathrm{p}}={\mathrm{C}}_2$$

(2)

$${\mathrm{R}}_{\mathrm{s}}={\displaystyle \frac{{\mathrm{G}}_{\mathrm{o}1}}{{\mathrm{G}}_{\mathrm{m}1}{\mathrm{G}}_{\mathrm{m}2}}},{\mathrm{L}}_{\mathrm{e}\mathrm{q}}={\displaystyle \frac{{\mathrm{C}}_1}{{\mathrm{G}}_{\mathrm{m}1}{\mathrm{G}}_{\mathrm{m}2}}}$$

(3)

An important parameter that determines the maximum operating frequency of an AI is its SRF, which is denoted by ω₀ and expressed as

$${\mathsf{\omega }}_0={\displaystyle \frac{1}{\sqrt{{\mathrm{L}}_{\mathrm{e}\mathrm{q}}{\mathrm{C}}_{\mathrm{p}}}}}=\sqrt{{\displaystyle \frac{{\mathrm{G}}_{\mathrm{m}1}}{{\mathrm{C}}_1}}{\displaystyle \frac{{\mathrm{G}}_{\mathrm{m}2}}{{\mathrm{C}}_2}}}=\sqrt{{\mathsf{\omega }}_{\mathrm{t}1}{\mathsf{\omega }}_{\mathrm{t}2}}$$

(4)

where ω_t1 and ω_t2 are the cut-off frequencies of the transconductance G_m1 and G_m2, respectively, and defined by (5):

$${\mathsf{\omega }}_{\mathrm{t}\mathrm{1,2}}={\displaystyle \frac{{\mathrm{G}}_{\mathrm{m}\mathrm{1,2}}}{{\mathrm{C}}_{\mathrm{1,2}}}}$$

(5)

Clearly, the effectiveness of an AI design depends on identifying and minimizing parasitics. Referring to Figure 1b, the key factors mainly affecting the behavior of AI include series resistance (R_s), parallel conductance (G_p), and parallel capacitance (C_p). Furthermore, L_eq and R_s can be controlled through C₁ and G_o1. The equations indicate that inductive bandwidth is primarily determined by the transistor’s transconductance, the parasitic capacitance C_p, and the output conductance (G_o1 or g_ds).

2.2. Concept of G_m-Boosting

G_m-boosting is a widely adopted technique for enhancing the gain of operational amplifiers [19]. Since this technique is also utilized in the design of the proposed AI, this subsection is devoted to explaining the concept of G_m-boosting briefly, before giving the detailed analysis of the proposed AI.

In a conventional MOS transistor, the transconductance is expressed as ${\mathrm{g}}_{\mathrm{m}}=\sqrt{2\mathrm{\mu }{\mathrm{C}}_{\mathrm{o}\mathrm{x}}\left({\displaystyle \frac{\mathrm{W}}{\mathrm{L}}}\right){\mathrm{I}}_{\mathrm{D}}}$, where $\mathsf{\mu }$ is the carrier mobility (with ${\mathsf{\mu }}_n$ for NMOS and ${\mathsf{\mu }}_p$ for PMOS); C_ox is the gate capacitance per unit area; W/L is the transistor’s aspect ratio, and I_D is the bias current. Achieving a higher transconductance (g_m) level typically requires a larger device size with a higher bias current, which increases power consumption and limits performance. To mitigate these drawbacks, the G_m-boosting technique has been introduced [14,15]. Figure 2 illustrates the basic principle of the G_m-boosting technique. As depicted in Figure 2b, a G_m-boosted transistor employs a feedback loop with a negative gain ($-\left|A\right|$). Therefore, this method enhances the transconductance by a factor, as given in (6):

$$\begin{gathered} {\mathrm{i}}_{\mathrm{o}}=-{\mathrm{g}}_{\mathrm{m}}{\mathrm{V}}_{\mathrm{g}\mathrm{s}}=-{\mathrm{g}}_{\mathrm{m}}\left({\mathrm{V}}_{\mathrm{g}}-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\right) \\ =-{\mathrm{g}}_{\mathrm{m}}\left(-{\mathrm{A}\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\right)={\mathrm{g}}_{\mathrm{m}}\left(1+\mathrm{A}\right){\mathrm{V}}_{\mathrm{i}\mathrm{n}} \\ \Rightarrow {\mathrm{G}}_{\mathrm{m}}={\mathrm{i}}_{\mathrm{o}}/{\mathrm{V}}_{\mathrm{i}\mathrm{n}}={\mathrm{g}}_{\mathrm{m}}\left(1+\mathrm{A}\right) \end{gathered}$$

(6)

Here, g_m is the intrinsic transconductance of the MOS transistor, and A is the gain of the feedback amplifier. By incorporating a simple common-gate (CG) amplifier with a negative gain, the overall transconductance G_m is significantly increased. Regarding (6) and Figure 2, the input signal, amplified by a factor of ($-\left|A\right|$) through the inverting gain block, is then applied to the gate of the transistor M₁. As a result, the overall transconductance of the CG amplifier increases by a factor of (1 + A). It is noted that, compared with conventional designs, the feedback amplifier operates with low bias currents to achieve similar transconductance levels, ensuring minimal additional power dissipation.

This technique not only boosts the performance of the circuit by enhancing the transconductance but also reduces power consumption. As a result, these advantages make the G_m-boosting technique highly suitable for applications demanding low-power and high-performance inductive components, in RF applications, including filters, matching networks, phase shifters, and more.

2.3. Proposed Active Inductor and Its Small-Signal Characteristics

The proposed active inductor is based on a CMOS implemented gyrator-C structure, and a G_m-boosting stage connected over a feedback resistor. The schematic of the proposed AI is shown in Figure 3. The core of the gyrator-C network relies on distinct positive and negative transconductors. Specifically, transistor M_3N acts as the positive transconductor (G_m1), and the regulated cascode input transistors M_2N, M_4N, and M_5N adjust the gyrator’s negative transconductance (G_m2) block that controls the effective inductance and input parasitic capacitance independently. The control is primarily achieved through the G_m-Boosting Block (transistors M_2P and M_5N). In this loop, M_2P and M_5N function as a feedback path that drives the gate voltage of M_4N. Current sources I₁ and I₂ are realized by M_P1 and M_P2, respectively. By properly varying V_CTRL1 and V_CTRL2, the currents through M_4N and M_5N are adjusted, and thus the inductance value of the AI can be tuned. Moreover, the negative resistance of the cross-coupled structure M_1N, M_2N helps to cancel the parasitic series resistance of the inductor, which in turn enhances the quality factor. Leveraging the G_m-boosting technique through node-4 enhances the effective transconductance of M_4N, thereby improving the overall noise performance of the active inductor. Introducing the feedback resistor R_f, between core-AI and G_m-boosting stages, helps to reduce G_p and improves the quality factor. However, due to the use of the cross-coupled negative-resistance compensation and the G_m-boosting feedback loop, the circuit stability requires careful attention, especially under large tuning ranges of voltage and process and temperature variations.

In the proposed design, the bias currents I₁ and I₂ shown in dashed form in Figure 3 represent controllable current sources that set the operating points and tuning characteristics of the active inductor. In this implementation, these currents are generated by PMOS transistors M_1P and M_2P, whose values are adjusted through the gate-bias voltages V_CTRL1 and V_CTRL2. While simple gate-controlled current sources are used here to maintain a compact and fully integrated structure, they may be replaced by tunable current mirrors or externally controlled bias circuits. The small-signal equivalent circuit of the proposed AI is presented in Figure 4. Referring to this small-signal schematic, the input admittance of the system is calculated and given in Appendix A.

After algebraic decomposition and simplifications, it can be modeled as an equivalent RLC circuit with the component values given in (7):

$$\left\{\begin{array}{c}{\mathrm{L}}_{\mathrm{e}\mathrm{q}}\cong {\displaystyle \frac{{\mathrm{C}}_{\mathrm{g}\mathrm{s}5}{\mathrm{R}}_{\mathrm{f}}{\mathrm{g}}_{\mathrm{o}4}+{2\mathrm{C}}_{\mathrm{g}\mathrm{s}3}}{{\mathrm{g}}_{\mathrm{m}2}{\mathrm{g}}_{\mathrm{m}3}}}\\ {\mathrm{R}}_{\mathrm{s}}\cong {\displaystyle \frac{{\mathrm{g}}_{\mathrm{o}4}}{{\mathrm{g}}_{\mathrm{m}3}{\mathrm{g}}_{\mathrm{m}2}}}\\ {\mathrm{G}}_{\mathrm{p}}\cong {\displaystyle \frac{{{\mathrm{g}}_{\mathrm{m}3}\mathrm{g}}_{\mathrm{m}2}}{{\mathrm{g}}_{\mathrm{o}4}}}+{\displaystyle \frac{{\mathrm{C}}_{\mathrm{g}\mathrm{s}4}{\mathrm{g}}_{\mathrm{m}3}{\mathrm{g}}_{\mathrm{m}2}}{2{\mathrm{C}}_{\mathrm{g}\mathrm{s}3}{\mathrm{g}}_{\mathrm{m}4}{\mathrm{g}}_{\mathrm{m}5}+{\mathrm{C}}_{\mathrm{g}\mathrm{s}5}{\mathrm{g}}_{\mathrm{o}4}{\mathrm{R}}_{\mathrm{f}}{\mathrm{g}}_{\mathrm{m}4}{\mathrm{g}}_{\mathrm{m}5}}}\\ {{\mathrm{C}}_{\mathrm{p}}=\mathrm{C}}_{\mathrm{g}\mathrm{s}2}-{\displaystyle \frac{{\mathrm{C}}_{\mathrm{g}\mathrm{s}4}{\mathrm{g}}_{\mathrm{m}1}{\mathrm{g}}_{\mathrm{m}2}}{{\mathrm{g}}_{\mathrm{m}4}{\mathrm{g}}_{\mathrm{m}5}}}\end{array}\right.$$

(7)

It is important to note that L_eq in (7) is proportional to R_f, meaning that choosing a higher R_f leads to a higher extracted inductance. As seen from (7), the series resistance (R_s) remains unaffected by changes in R_f. The maximum frequency at which the circuit exhibits inductive behavior is referred to as the self-resonant frequency (SRF) of the active inductor and is defined as ${\mathsf{\omega }}_0={\displaystyle \frac{1}{\sqrt{{\mathrm{L}}_{\mathrm{e}\mathrm{q}}{\mathrm{C}}_{\mathrm{p}}}}}$. Using the extracted expressions of L_eq and C_p from (7), the SRF and quality factor of the proposed AI are obtained as in (8) and (9):

$${\mathsf{\omega }}_0\cong \sqrt{{\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}2}{\mathrm{g}}_{\mathrm{m}3}{\mathrm{g}}_{\mathrm{m}4}{\mathrm{g}}_{\mathrm{m}5}}{\left({{\mathrm{C}}_{\mathrm{g}\mathrm{s}5}\mathrm{R}}_{\mathrm{f}}{\mathrm{g}}_{\mathrm{o}4}+{2\mathrm{C}}_{\mathrm{g}\mathrm{s}3}\right)\left({\mathrm{C}}_{\mathrm{g}\mathrm{s}2}{\mathrm{g}}_{\mathrm{m}4}{\mathrm{g}}_{\mathrm{m}5}-{\mathrm{C}}_{\mathrm{g}\mathrm{s}4}{\mathrm{g}}_{\mathrm{m}1}{\mathrm{g}}_{\mathrm{m}2}\right)}}}$$

(8)

$$\mathrm{Q}={\displaystyle \frac{{\mathsf{\omega }}_0{\mathrm{L}}_{\mathrm{e}\mathrm{q}}}{{\mathrm{R}}_{\mathrm{s}}}}\cong \sqrt{{\displaystyle \frac{\left({\mathrm{C}}_{\mathrm{g}\mathrm{s}5}{\mathrm{R}}_{\mathrm{f}}{\mathrm{g}}_{\mathrm{o}4}+{2\mathrm{C}}_{\mathrm{g}\mathrm{s}3}\right){\mathrm{g}}_{\mathrm{m}2}{\mathrm{g}}_{\mathrm{m}3}{\mathrm{g}}_{\mathrm{m}4}{\mathrm{g}}_{\mathrm{m}5}}{\left({\mathrm{C}}_{\mathrm{g}\mathrm{s}2}{\mathrm{g}}_{\mathrm{m}4}{\mathrm{g}}_{\mathrm{m}5}-{\mathrm{C}}_{\mathrm{g}\mathrm{s}4}{\mathrm{g}}_{\mathrm{m}1}{\mathrm{g}}_{\mathrm{m}2}\right){{\mathrm{g}}_{\mathrm{o}4}}^2}}}$$

(9)

According to (8) and (9), a higher value of R_f results in an increased quality factor. This effect will also be examined through simulations in the next subsection.

2.4. Results of Proposed Active Inductor

The proposed design in Figure 3 is implemented using a 180 nm RFCMOS process with a supply voltage of 1.8 V. For reference design, circuit parameters and element values are rigorously calculated and tuned as provided in

Table 2. Circuit parameter values.

Parameter	Value	Parameter	Value
M1P(W/L)	9.7 μm/0.18 μm	M2P(W/L)	27 μm/0.18 μm
M1N(W/L)	3.2 μm/0.18 μm	M2N(W/L)	13 μm/0.18 μm
M3N(W/L)	13 μm/0.18 μm	M4N(W/L)	3.7 μm/0.18 μm
M4N(W/L)	3.7 μm/0.18 μm	M5N(W/L)	5.8 μm/0.18 μm
VCTRL1	0.63 V	VCTRL2	0.87 V

. These parameters correspond to a range of control voltages V_CTRL1 and V_CTRL2 varying from 600 mV to 1.2 V. V_CTRL1 primarily controls the frequency band, whereas V_CTRL2 has effects on the inductance values. A higher V_CTRL1 results in a lower resonant frequency and vice versa. Similarly, the inductance value is proportional to V_CTRL2. Variations in control voltages also affect the bias currents I₁ and I₂ and, consequently, the total power consumption. Since M_1P and M_2P are PMOS current sources, higher control voltages reduce their overdrive voltages, leading to lower power consumption.

The layout of the AI is given in Figure 5a; it occupies an area of 0.0006 mm² (23.56 μm × 25.8 μm). As shown in Figure 5b, the inductance value varies from 4.5 nH to 215 nH by sweeping control voltages from 600 mV to 1.2 V.

By running the simulations, the resulting performance characteristics of the AI are shown in Figure 6. The magnitude and phase of the input impedance (Z_in) are depicted in Figure 6a. Examination of Figure 6a reveals that the design exhibits an inductive behavior up to 4.1 GHz. The impedance phase approaching 90° is promising for achieving a pure and high-quality inductor. As seen in Figure 6b, beyond 4.1 GHz, the imaginary part of Z_in becomes negative, indicating a transition to capacitive behavior. In addition, the equivalent RLC model of the proposed AI is derived based on Figure 1b, and the approximated parameters are given as L_eq = 11.78 nH, R_s = 8.21 Ω, C_p = 0.126 pF, and R_P ≈ 50 kΩ. The simulated response of the RLC model is also plotted in Figure 6. A detailed comparison shows a close match between the RLC model and the designed active inductor, validating the accuracy of the equivalent representation.

In the proposed active inductor, a feedback resistor R_f is intentionally inserted between the core gyrator-C structure and the G_m-boosting stage to regulate the boosting loop and enhance the overall performance. The resistor R_f provides a controlled feedback path that limits the loop gain, stabilizes the boosted transconductance, and reduces the equivalent parallel loss G_p. As demonstrated by the analytical expressions in (7), the extracted inductance L_eq increases proportionally with R_f. Moreover, substituting L_eq and C_p into (8) and (9) shows that a larger R_f directly leads to a higher quality factor. As predicted by (7)–(9), an increase in the value of R_f yields an improved quality factor. This relationship is illustrated in Figure 7a,b, which shows the quality factor for various values of R_f. As shown in the figure, the quality factor reaches values around 1000 and can rise as high as 5000. The high quality factor observed in Figure 7 arises from the combined effect of the negative-resistance compensation provided by the cross-coupled pair (M_1N, M_2N) and the substantial enhancement of the effective transconductance generated by the G_m-boosting loop around M_4N. In the proposed gyrator-C active inductor, the equivalent series resistance R_s becomes very small when the negative conductance introduced by the cross-coupled devices nearly cancels the parasitic channel and bias-dependent resistances of the core transconductance stage. At the same time, the feedback-assisted G_m-boosting path (M_2P, M_5N), together with the feedback resistor R_f, increases the effective g_m4 while reducing the parallel conductance G_p, thereby raising the equivalent parallel resistance (R_p ≈ 1/G_p). Nonetheless, we acknowledge that parasitic effects, device mismatch, and practical implementation constraints tend to reduce the achievable Q. To observe the noise performance of the circuit, the simulated input-referred current noise is presented in Figure 7c. The input-referred noise at maximum quality factor (i.e., at 2.7 GHz) is $27\mathrm{p}\mathrm{A}\sqrt{\mathrm{H}\mathrm{z}}$ as depicted in the figure.

To evaluate the stability of the proposed active inductor, two separate loop-gain analyses were performed. The first loop is formed by the feedback resistor R_f, and its loop gain was obtained by breaking the path across R_f and measuring the corresponding response. The second loop corresponds to the G_m-boosting path, for which the loop gain was similarly extracted by breaking the internal boosting loop. Loop-gain curves were generated for various control-voltage settings for both loops. For lower control voltage values, all the loop gains remain below unity, indicating a stable operating region. For the cases in which the loop gain exceeds unity, the corresponding magnitude and phase responses are plotted in Figure 8 and Figure 9, for the R_f path and the G_m-boosting path, respectively. An examination of Figure 8b and Figure 9b shows that the phase margins remain well above commonly accepted stability limits, all exceeding 45°. Based on the simulations, it can be observed that the proposed active inductor remains stabilized for V_CTRL values below 1.2 V, while instability may begin to appear above this level due to excessive boosting. This analysis indicates that the proposed active inductor exhibits stable behavior across typical operating conditions for the component values used.

In order to assess the robustness of the proposed active inductor under practical operating conditions, corner, temperature, and Monte Carlo analyses were performed. These analyses collectively assess the sensitivity of the design to process variations, thermal changes, and device mismatch. In MOSFETs, process parameters such as oxide thickness, doping concentration, and threshold voltage fluctuate, causing deviations from nominal values. As a result, the current can vary, being higher at the Fast Corner or lower at the Slow Corner, depending on the fluctuations in each parameter. When designing a circuit, the designer must ensure that the circuit is compatible with these process variations. In this study, three corner models from the RFCMOS 0.18 μm model library were utilized: TT (Typical–Typical), FF (Fast–Fast), and SS (Slow–Slow), representing the typical, fast, and slow process variations, respectively. Corner analyses, as depicted in Figure 10a,b, show a slight variation in the obtained value for the concerned corner. As expected, different corner sections result in noticeable variations in performance, without altering the overall behavior of the circuit. An analog circuit can be subjected to temperature variations, so temperature sweep analyses were performed for the imaginary part of the input impedance and the equivalent inductance, as depicted in Figure 11a,b.

The Monte Carlo analysis can be used to examine process variation and device mismatch of a circuit and study its impact on the design. Therefore, it allows us to examine and predict circuit performance variations, which may affect yield. Monte Carlo analysis with a sample size of 1000 was performed by applying Gaussian distribution with three sigma variations. Figure 12a,b show the statistical distribution of simulated parameters with respect to histograms. It can be illustrated from the figures that the simulated parameters have low standard deviations from their mean values.

Finally, the overall performance of the proposed AI is summarized in

Table 3. Performance comparison table.

Parameter	[15]	[20]	[21]	[22]	[23]	This Work
Technology (nm)	180	130	65	180	130	180
Inductance (nH)	4.35–15.2	6.7–84.4	2.2–3.2	500–3500	27.49–73.8	4.5–215
Power (mW)	0.65	2	9.6	0.31	0.137	1.82
SRF (GHz)	7.2	3.96	3.8	0.3–1.9	0.271–3.7	4.1
Supply voltage (V)	1.8	1	1.2	±0.8	1.5	1.8
Area (mm2)	0.0003	0.0003	0.013	0.0002	0.0001	0.0006
$\mathrm{Current}\mathrm{noise}\left(\mathrm{p}\mathrm{A}\sqrt{\mathrm{H}\mathrm{z}}\right)$	22	-	-	-	-	27
Quality factor	90	1586	1.83	577	437	5500

with comparisons to other existing similar studies, highlighting its superior performance.

3. Application of the Proposed AI in a Broadband RF Amplifier Design

In this section, we present a demonstration of the proposed AI structure in a microwave amplifier system. Specifically, we aim to design a broadband small-signal RF amplifier using CMOS technology operating within the 0.8–2.1 GHz frequency band, intended for sub-6 GHz 5G and beyond wireless communication systems. To achieve this, we used a common-source transistor with the following parameters: width W = 400 μm and length L = 180 nm, biased with V_DC = 1.8 V drain voltage and V_GG = 0.65 V gate voltage applied over RF chokes. Additionally, a feedback resistor R_FB was inserted between the drain and gate terminals of the transistor to improve stability, accompanied by a feedback capacitor C_FB to block DC leakage within the feedback path. To further improve the stability, a small-valued series R_O in resistance is also included at the drain end of the transistor.

Under these fixed conditions, we measured the S-parameters of the biased and stabilized transistor. These measured S-parameters were then used to design the appropriate matching networks for 50 Ω source and load terminations, which is a standard for microwave applications. In the design process, the transducer power gain (TPG) of the system was optimized using the Simplified Real Frequency Technique (SRFT). It is noted that SRFT is a robust numerical method for designing broadband microwave amplifiers, as it directly utilizes the transistor’s S-parameters rather than requiring impedance or admittance representations [24,25,26,27]. For the selected target minimum gain level T₀ = 14 dB, both the input matching network (IMN) and the output matching network (OMN) were synthesized with ideal circuit components. The final schematic of the designed amplifier is shown in Figure 13. Evaluation of Figure 13 indicates that the inductor L_o2, with a value of 9 nH in the OMN, is well suited for integration with our proposed AI circuit, as it is connected in shunt with the signal path. To validate the AI design, we replaced L_o2 with the proposed AI, carefully tuning its parameters to closely approximate the target inductance value. Additionally, an equivalent RLC model of the designed AI was extracted with the element values of L_eq = 9.5 nH, R_s = 0.5 Ω, C_p = 0.25 pF, and R_P ≈ 1 kΩ. The corresponding simulation results are presented in Figure 14 and Figure 15.

Figure 14a,b show the input and output reflectance results of the amplifier, respectively. In both cases (ideal inductor and AI), |S₁₁| and |S₂₂| remain below −10 dB over the frequency band of operation. Analysis of the figures reveals that input and output reflection performances are close to each other along the band of operation. In Figure 15a, the TPG of the amplifier for both the ideal inductor and AI cases are presented. As shown from the figure, the performance with the AI is nearly identical to the ideal case, with a gain ranging from 13.43 dB to 13.88 dB, exhibiting only a minimal and negligible decrease compared with the ideal case. The |S₁₂| performance results given in Figure 15b show that the active inductor and the ideal model are in good agreement, with S₁₂ reaching approximately −20 dB, indicating a fine isolation performance within the frequency band of interest. Figure 16a presents the noise figure (NF) performances of the amplifier for both AI and ideal inductor cases. From the figure, it is observed that, while there is an increase of about 1.48 dB at the lower cut-off frequency (reaching 5.48 dB level at 0.8 GHz), the noise figure for the AI case approaches the ideal inductor performance as frequency increases, becoming 3.43 dB at 2.1 GHz. This demonstrates that the proposed AI exhibits low noise figure performance, comparable to the ideal case. In this design, the active inductor L_o2 creates a transmission zero at DC and maintains the lower cut-off slope. At low frequencies, L_o2 acts as a short circuit, while at higher RF frequencies (up to 2.1 GHz), its impedance increases toward an open circuit, shunting the noise current away from the signal path. Consequently, the active inductor’s noise contribution becomes negligible at the operating frequency, explaining the noise figure behavior observed in Figure 16. The stability analysis of the amplifier incorporating the active inductor L_o2 was performed together with a Monte Carlo analysis that includes statistical, mismatch, and process variations. The resulting plotted Rollett stability factor (K), μ-factor (load), and μ-factor (source) are presented in Figure 16b and Figure 17a,b, respectively, along with their nominal values (red curves) and Monte Carlo variations (gray curves). As seen from the figures, the K-factor and μ-factors remain above unity with sufficient margins, indicating stable operation over the entire frequency band. Through this example, it is shown that the proposed AI can be effectively used in RFIC systems, specifically in matching networks, to replace passive inductors, making it a promising and efficient technology for 5G and future communication systems.

4. Conclusions

A novel low-power, high-quality factor, wide-tunable, and broadband CMOS active inductor based on a gyrator-C configuration is presented. Through the application of the G_m-boosting technique, the AI achieves significant improvements in both performance and power efficiency, while a feedback resistor further boosts the quality factor. The inductance can be tuned ranging from 4.5 nH to 215 nH, across a wide frequency range up to 4.1 GHz, with a power consumption of only 1.82 mW at a 1.8 V supply, and the AI exhibits a low input-referred current noise as $27\mathrm{p}\mathrm{A}\sqrt{\mathrm{H}\mathrm{z}}$, making it ideal for low-noise applications. The compactness of the design, with a chip area of 0.0006 mm², makes it a strong candidate for integration in RF systems.

The versatility of the proposed AI was demonstrated by incorporating it into a broadband RF amplifier design for RFIC applications, which operates within a 0.8–2.1 GHz bandwidth and provides near-ideal performance. The results validate the potential of the proposed AI for meeting the stringent demands of modern wireless GSM and 5G and beyond communication systems. The robustness and reliability of the proposed design are validated by performing temperature, stability, corner, and Monte Carlo analyses. In conclusion, the proposed AI offers an advantageous solution for future wireless communication systems, providing a compact and efficient inductive component that can be integrated into complex RF circuits.