CMOS LIF Spiking Neuron Designed with a Memristor Emulator Based on Optimized Operational Transconductance Amplifiers

Abstract

The proposed work introduces a sizing algorithm to achieve a desired linear transconductance in the optimization of operational transconductance amplifiers (OTAs) by applying the $g_m/I_D$ method to find the initial width (W) and length (L) sizes of the transistors. These size values are used to run the non-dominated sorting genetic algorithm (NSGA-II) to perform a multi-objective optimization of three OTA topologies. The $g_m/I_D$ method begins with transistor characterization using MATLAB R2024a generated look-up tables (LUTs), which map normalized transconductance of the transistor channel dimensions, and key performance metrics of a complementary metal–oxide–semiconductor (CMOS) technology. The LUTs guide the initial population generation within NSGA-II during the optimization of OTAs to achieve not only a desired transconductance but also accuracy alongside linearity, high DC gain, low power consumption, and stability. The feasible W/L size solutions provided by NSGA-II are used to enhance the CMOS design of a memristor emulator, where the OTA with the desired transconductance is adapted to tune the behavior of the memristor, demonstrating improved pinched hysteresis loop characteristics. In addition, process, voltage and temperature (PVT) variations are performed by using TSMC 180 nm CMOS technology. The memristor-based on optimized OTAs is used to design a Leaky Integrate-and-Fire (LIF) neuron, which produces identical spike counts (seven spikes) under the same input conditions, though the time period varied with a CMOS inverter scaling. It is shown that increasing transistor widths by 100 in the inverter stage, the spike quantity is altered while changing the spiking period. This highlights the role of device sizing in modulating LIF neuron dynamics, and in addition, these findings provide valuable insights for energy-efficient neuromorphic hardware design.

1. Introduction

Nowadays, Spiking Neural Networks (SNNs) represent a paradigm in neuromorphic computing, establishing themselves as the third generation of artificial neural networks [1]. Unlike conventional second-generation neuron models, which rely on continuous activation functions, SNNs more faithfully replicate biological nervous systems’ information processing through temporal pulses (spikes) [2]. This approach is grounded in key neurophysiological principles: temporal information coding, dynamic activation thresholds, and spike-timing-dependent plasticity (STDP) [3].

SNNs operate on a strictly event-driven paradigm, where each artificial neuron maintains a membrane potential modulated by synaptic inputs. A spike (analogous to biological action potentials) is generated only when this potential crosses a critical threshold. This event-driven architecture provides exceptional energy efficiency, as power consumption occurs exclusively during spike generation, unlike traditional neural networks that require continuous processing [4]. This efficiency makes SNNs particularly promising for low-power neuromorphic hardware implementations [5].

From a computational perspective, spiking neuron models capture the essential dynamics of biological membrane potentials through mathematical formulations of varying complexity. Among these, the Leaky Integrate-and-Fire (LIF) model stands out for its optimal balance between simplicity and biological plausibility, making it widely adopted in both computational neuroscience and neuromorphic engineering applications [2].

Concurrently, memristors have emerged as crucial components for advancing SNNs, owing to their non-volatile memory properties and ability to emulate biological synaptic behavior [6]. These two-terminal devices combine low power consumption with nonlinear dynamics, enabling efficient implementation of synaptic plasticity mechanisms like STDP. The synergy between memristors and SNNs opens new possibilities for developing more efficient and biologically plausible artificial intelligence systems [7]. The sizing approach described herein not only enhances memristor emulator performance but also establishes a systematic methodology for co-designing analog components and neuromorphic systems using 180 nm TSMC complementary metal–oxide–semiconductor (CMOS) technology. The obtained results provide valuable insights for developing scalable and energy-efficient neuromorphic hardware.

The proposed work integrates theoretical modeling, CMOS analog design, and evolutionary algorithms for the optimization of operational transconductance amplifiers (OTAs), resulting in a hybrid methodology that enhances the neuromorphic behavior of the proposed system. Section 2 details the implementation of CMOS memristor emulators in LIF neurons, describing their dynamics and topology consisting of four blocks. Section 3 introduces a memristor emulator based on a CMOS OTA, presenting its governing equations and dynamic characteristics. Section 4 analyzes three OTA topologies, where transistor channel widths are encoded as integer multiples of the technology parameter LAMBDA, and are optimized by applying the non-dominated sorting genetic algorithm (NSGA-II) to simultaneously achieve three objectives: linear transconductance response, high differential gain, and minimize power consumption. Section 5 presents optimization results including electrical characteristics of all OTA topologies, memristor emulation performance, and a complete characterization of the CMOS memristor emulator-based LIF neuron dynamics across all OTA designs. Finally, the conclusions are summarized in Section 6.

2. CMOS Memristor Emulator in LIF Neurons

Computational models of spiking neurons simulate two fundamental processes: synaptic current integration and action potential (spike) generation [5]. The LIF model extends the basic mechanism by incorporating a passive leakage component that mimics the membrane’s natural tendency to return to its resting potential. The main advantage of LIF models lies in their computational and circuit simplicity, making them particularly suitable for embedded systems and neuromorphic devices. An important thing is that memristors have emerged as promising components for emulating both leakage resistance and synaptic plasticity, enabling the development of more compact and energy-efficient designs [8].

2.1. LIF Neuron Dynamics

The LIF model maintains computational efficiency while being easily implementable in both analog and digital circuits, making it ideal for SNN systems without the complexity of more detailed models [9]. Its behavior can be modeled using a simple electrical circuit comprising a membrane capacitor ($C_m$) in parallel with a leakage resistor ($R_{leak}$), whose dynamics are described by Equation (1),

$${\tau }_m{\displaystyle \frac{d{V}_m\left(t\right)}{dt}}=-(V_m\left(t\right)-u_{rest})+R_{leak}{I}_m\left(t\right),$$

(1)

where ${\tau }_m=R_{leak}{C}_m$ represents the system’s characteristic time constant. The capacitor accumulates charge in response to an input current ($I_m\left(t\right)$), while the resistor models the membrane’s passive conductance responsible for ion leakage at rest. When synaptic currents excite the neuron, the membrane potential $V_m\left(t\right)$ gradually increases. Upon reaching a predetermined threshold $V_{th}$, the neuron generates a spike and immediately resets to the resting potential $u_{rest}$, replicating biological post-spike behavior [10]. The firing mechanism activates when $V_m\left(t\right)$ reaches or exceeds $V_{th}$, triggering a spike followed by a reset. In the circuit implementation shown in Figure 1, the reset is achieved through a voltage-controlled switch that rapidly discharges the capacitor. This mechanism reproduces two key biological neuron features: action potential generation and the refractory period (a brief post-spike interval during which the neuron cannot fire again).

The LIF neuron’s firing rate depends directly on the $I_m\left(t\right)$ magnitude, as illustrated in Figure 2. Weak input currents allow leakage to dominate, preventing threshold attainment and spike generation. Conversely, stronger currents accelerate capacitor charging, causing an increase in firing frequency. The input current-to-spike rate relationship enables SNNs to encode information in temporal activity patterns—a fundamental property for artificial intelligence and neuromorphic processing applications.

2.2. Memristor-Based Volatile LIF Neuron

The dynamic behavior of the LIF neuron circuit shown in Figure 1 can be electronically implemented using comparators and reset circuits, though these additional components significantly increase system complexity [10].

An innovative solution proposed in [8] replaces both the leakage resistor $R_{leak}$ and the reset switch with a volatile memristor. This device exhibits variable memconductance (dependent on charge or flux accumulation), enabling abrupt internal resistance switching with state “forgetting”. The system operates through the following three characteristic phases:

• Resting state: The memristor maintains high resistance, simulating the membrane’s elevated basal resistance.
• Integration phase: Input current $I_{in}\left(t\right)\approx {\displaystyle \frac{V_{in}\left(t\right)}{R_s}}$ progressively charges $C_m$, causing exponential $V_m\left(t\right)$ growth.
• Firing and reset: When $V_m\left(t\right)$ exceeds $V_{th}$, the memristor abruptly switches to low resistance, rapidly discharging $C_m$ (generating a spike) before spontaneously returning to high resistance—eliminating external reset circuitry requirements.

This approach significantly simplifies the architecture of the LIF neuron by eliminating additional active components while achieving more biologically plausible behavior through natural emulation of depolarization/repolarization processes. The design also improves energy efficiency by capitalizing on the volatile memristor’s intrinsic properties. As schematically shown in Figure 3, the implementation consists of a voltage-to-current conversion network (where $V_{in}\left(t\right)$ is transformed to $I_{in}\left(t\right)$ through $R_s$), a membrane integration capacitor $C_m$, and a parallel-connected memristor that dynamically regulates charge leakage [11]. The modified membrane potential dynamics are described by Equation (2),

$$C_m{\displaystyle \frac{d{V}_m\left(t\right)}{dt}}=I_{memristor}+{\displaystyle \frac{V_{in}\left(t\right)}{R_s}},$$

(2)

where the memristive current is

$$I_{memristor}=-W\left(\varphi \left(t\right)\right)(V_m\left(t\right)-u_{rest}).$$

(3)

Figure 4 illustrates the temporal evolution of this system, revealing important nonlinear relationships between input excitation and spiking response. The plot clearly demonstrates how changes in volatile memconductance during current pulses directly influence spike generation frequency. The memristor’s state-dependent resistance creates an adaptive leakage pathway that naturally maintains high resistance during subthreshold integration while providing rapid discharge during spiking events, all without requiring external control circuitry for reset operations.

2.3. CMOS Design of a Memristor Emulator-Based LIF Neuron

A more sophisticated circuit implementation of the neuronal model, based on the analog spiking neuron proposed by [12], and modified by [13] to incorporate a memristor emulator, is shown in Figure 5  [13]. It employs a modular architecture comprising four interconnected functional blocks. The use of devices with stable states enhances circuit performance by allowing the resistance states $R_{on}$ and $R_{off}$ to be reliably programmed with voltage or current pulses. These stable resistance states can be directly associated with binary information, making the design particularly suitable for memory-oriented applications such as synaptic-weight storage.

The blocks embedded in Figure 5 have the following characteristics:

• Current Mirror: This stage replicates and isolates the input current while providing a stable signal to the integrator. Its symmetric design ensures precise current injection regardless of power supply variations, maintaining consistent operation across different input conditions.
• Integration: The integration stage incorporates a capacitor $C_{int}$ that accumulates the injected current. In this implementation, a transistor is connected in parallel to the capacitor, which can be modeled as an equivalent conductance $g_{m3}$. This modifies the integration equation to account for the leakage current through the transistor
  $$V_m\left(t\right)={\displaystyle \frac{1}{C_{int}}}\int \left[I_{in}\left(\tau \right)-g_{m3}{V}_m\left(\tau \right)\right]d\tau ,$$

  (4)

  where $V_m\left(t\right)$ represents the membrane potential. The presence of the conductance $g_{m3}$ causes $V_m\left(t\right)$ to exhibit a leaky integration behavior, gradually approaching a steady state if $I_{in}$ is constant, until reaching the firing threshold.
• Memristive Reset Module (MRM): The MRM replaces conventional reset circuits by leveraging the memristor’s intrinsic properties. During spike generation, the memristor (MR) automatically transitions to a conductive state, followed by a passive self-reset to high resistivity, as further explained in Section 3.
• Schmitt Trigger: A comparator with hysteresis provides enhanced noise immunity through its symmetric thresholds. This circuit generates well-defined digital spikes when $V_m\left(t\right)$ exceeds $V_{th}$ while preventing unwanted oscillations during the reset phase. The hysteresis window ensures robust spike generation even in the presence of signal fluctuations.

The CMOS topology shown in Figure 5 offers advantages like improved firing accuracy through the Schmitt trigger implementation, enhanced dynamic control for tuning integration ($C_{int}$) and reset ($C_m$) time constants, and adaptive spiking behavior enabled by the nonlinear dynamics of the memristor emulator. The system demonstrates progressive frequency reduction in response to repeated stimuli and natural adaptation to input patterns, closely mimicking biological neuronal properties.

3. CMOS OTA-Based Memristor Emulator

Operational transconductance amplifiers (OTAs) are essential components in analog circuit design, used in applications such as precision filters [14], sample and hold circuits [15], rectifiers [16], analog-to-digital [17] and digital-to-analog [18] data converters.

The memristor (MR) emulator design embedded in Figure 5 is designed according to Figure 6 [13]. It consists of an OTA as its fundamental building block, which operates as a voltage-controlled current source, so that the output current ($I_G$) is determined by the transconductance gain ($G_m$) and the differential input voltage, i.e., $I_G=G_m(V^{+}-V^{-})$. In such a topology, $G_m$ is dynamically adjusted through a bias voltage $V_B$, thus having dependence on biasing conditions, as described in Equation (5).

$$G_m={\displaystyle \frac{k}{\sqrt{2}}}(V_B-V_S-2V_{th}),$$

(5)

where $V_S$ represents the source voltage of the biasing transistor, $V_{th}$ denotes the MOSFET threshold voltage, and $k={\mu }_{n,p}{C}_{ox}\left({\displaystyle \frac{W}{L}}\right)$ constitutes the technology-specific parameter encompassing mobility (${\mu }_{n,p}$), oxide capacitance ($C_{ox}$), and transistor sizing values.

The memristor emulation circuit shown in Figure 6, integrates three key components: a CMOS inverter, a storage capacitor (C), and the OTA. The dynamic behavior emerges from the interaction between the OTA’s transconductance and the integrating action of the CMOS inverter-capacitor pair. The integration is mathematically expressed as

$$V_B\left(t\right)={\displaystyle \frac{1}{C}}\int I_{out}\left(\tau \right)d\tau \to V_B\left(t\right)={\displaystyle \frac{g_m}{C}}\int V_{in}\left(\tau \right)d\tau ,$$

(6)

where $g_m$ represents the effective transconductance of the CMOS inverter. Substituting Equation (6) into Equation (5), one receives the description of the OTA’s effective transconductance, given by Equation (7).

$$G_m={\displaystyle \frac{k}{\sqrt{2}}}\left({\displaystyle \frac{g_m}{C}}\int V_{in}\left(\tau \right)d\tau -V_S-2V_{th}\right).$$

(7)

To ensure linear transconductance operation within the input voltage range of [−0.5 V … 0.5 V], the transistors in the CMOS inverter are sized with $L=1\mathrm{\mu }$m, $W_N=2\mathrm{\mu }$m, and $W_P=11\mathrm{\mu }$m. These sizes maintain $V_B$ = 0.55 V in large-signal operation while preserving the virtual ground condition at $V_S$.

When driven by a sinusoidal input $V_{in}\left(t\right)=A_{m}sin\left(\omega t\right)$ with $V_S$ maintained at virtual ground, the system exhibits memristive characteristics described by the memductance equation

$$W\left({\phi }_{IN}\left(t\right)\right)={\displaystyle \frac{k}{\sqrt{2}}}\left({\displaystyle \frac{A_m{g}_{m}cos(\omega t-\pi )}{\omega C}}-2V_{th}\right).$$

(8)

As the linearity and stability of $G_m$ across the operating range are difficult to accomplish, this work proposes an optimization framework for sizing OTAs by combining the $g_m/I_D$ methodology with the NSGA-II evolutionary algorithm, which allows Pareto-optimal topology exploration. This hybrid sizing approach enables simultaneous optimization of power consumption, linearity, and silicon area, while maintaining the desired memristive emulation characteristics.

4. Sizing CMOS OTA Topologies

This section describes the optimization of the three OTA topologies shown in Figure 7 [19], Figure 8 [20], and Figure 9 [21]. Each OTA topology adopts the following bias voltages: $V_B=$ 0.55 V, $V_{BN}$ = 0.3 V, $V_{B2}$ = −0.1 V and $V_{B1}$ = $V_{B3}$ = $V_{BP}$ = −0.3 V.

As outlined in Section 1 and Section 3, a hybrid methodology integrating the $g_m/I_D$ approach with the NSGA-II evolutionary algorithm can be applied to transistor sizing in CMOS analog design, ensuring compliance with target OTA specifications, as the ones considered in this work and given in

Table 1. Target specifications for the sizing of the CMOS OTAs shown in Figure 7, Figure 8 and Figure 9.

Parameter	Value
TSMC CMOS Technology	180 nm
Voltage Supply (V)	±0.9
Load Capacitance (pF)	1
DC Gain (dB)	≥40
Bandwidth (MHz)	≥1
Transconductance gain	≈3.5 mS

, which were obtained from [13].

In this work, the initial sizes of the MOS transistors for the three OTAs are encoded in

Table 2. Transistor encoding design variables for the current mirror OTA shown in Figure 7.

Transistor	$\mathit{W}/\mathit{L}$ ($\mathbf{\mu }$m)
$M_{N1}$	$16.6/1$
$M_{N2}$, $M_{N3}$	$W_1/1$
$M_{N4}$, $M_{N5}$	$W_2/1$
$M_{N6}$, $M_{N7}$	$W_3/1$
$M_{P2}$, $M_{P3}$	$W_4/1$
$M_{P1}$, $M_{P4}$	$W_5/1$

,

Table 3. Transistor encoding design variables for the folded cascode OTA shown in Figure 8.

Transistor	$\mathit{W}/\mathit{L}$ ($\mathbf{\mu }$m)
$M_{N1}$	$16.6/1$
$M_{N2}$, $M_{N3}$, $M_{N4}$	$W_1/1$
$M_{N5}$, $M_{N6}$	$W_2/1$
$M_{N7}$, $M_{N8}$, $M_{N9}$, $M_{N10}$	$W_3/1$
$M_{P1}$, $M_{P2}$	$W_4/1$
$M_{P3}$, $M_{P4}$	$W_5/1$
$M_{P5}$, $M_{P6}$	$W_6/1$
$M_{P7}$, $M_{P8}$	$W_7/1$

and

Table 4. Transistor encoding design variables for the low-voltage current mirror OTA shown in Figure 9.

Transistor	$\mathit{W}/\mathit{L}$ ($\mathbf{\mu }$m)
$M_{N1}$	$16.6/1$
$M_{N2}$, $M_{N3}$	$W_1/1$
$M_{N4}$, $M_{N5}$	$W_2/1$
$M_{N6}$, $M_{N7}$	$W_3/1$
$M_{N8}$, $M_{N9}$	$W_4/1$
$M_{P2}$, $M_{P3}$	$W_5/1$
$M_{P1}$, $M_{P4}$	$W_3/1$
$M_{P6}$, $M_{P7}$	$W_4/1$
$M_{P5}$, $M_{P8}$	$W_5/1$

. It can be seen that the channel length (L) is established by a multiple of the technology, while the widths (W) are the design variables for different sets of transistors and for each OTA topology. Specifically, the channel length is a multiple of LAMBDA when working with 180 nm CMOS technology, being $L=12\lambda =1.08\mathrm{\mu }$m $\approx 1\mathrm{\mu }$m. The sizing methodology for the OTA topologies is described as follows.

4.1. $g_m/I_D$ Sizing Methodology

Advancements in semiconductor fabrication technology have made non-ideal effects increasingly prominent, rendering traditional design methodologies (such as the square-law model) inaccurate and leading to significant discrepancies between theoretical predictions and SPICE simulation results. To address this issue, the $g_m/I_D$ methodology has been adopted from one decade ago [22]. This sizing technique employs lookup tables (LUTs), generated through DC analysis using BSIM models, to establish relationships among key parameters such as transition frequency ($f_T$), intrinsic gain ($g_m{r}_o$), current density ($I_D/W$), and transconductance efficiency ($g_m/I_D$). The LUTs are generated once, and are computationally efficient, and reusable across the design process [23].

During the CMOS design of the OTAs, one must select target values for $g_m/I_D$, drain current ($I_D$), and channel length (L). Afterwards, each transistor width ($W_X$) in each OTA design is calculated through the following equation:

$$W_X={\displaystyle \frac{I_D}{f_{LUT}\left(g_m/I_D,L\right)}},$$

(9)

where $f_{LUT}(·)$ retrieves the current density ($I_D/W$) associated with a given $g_m/I_D$ and L. This process achieves a desired circuit performance that aligns closely with SPICE simulations, enabling precise and predictable control over transistor electrical parameters [24].

The MATLAB R2024a code proposed in [25] automates the generation of LUTs and extracts W values for the selected L and biasing conditions of each MOS transistor, based on a predefined SPICE netlist. One issue is how to ensure that $W/L$ relationships are multiples of $\lambda$. This was solved by performing an integer encoding process along with the generation of the SPICE netlists [26]. Basically, this requires defining a global parameter $\lambda$ (LAMBDA) in the SPICE netlist, so that Ws are expressed as multiples of $\lambda$, as shown in Listing 1. Thus, each transistor’s width ($W_X$) is calculated as $W_X=Va{r}_X\ast \lambda$, where $Va{r}_X$ is a dimensionless integer and X denotes each design variable in the OTA topologies.

Listing 1. Example of using λ as parameter scaling in a SPICE netlist.

.PARAM LAMBDA = 0.09u

M_P D G S B PMOS L=1u W={Var1∗LAMBDA}

M_P D G S B NMOS L=1u W={Var2∗LAMBDA}

The sizing values for the MOS transistors that are obtained via the $g_m/I_D$ method are summarized in

Table 5. First iteration with $g_m/I_D$ method for sizing OTAs.

Topology	${\mathit{W}}_1$ ($\mathbf{\mu }$m)	${\mathit{W}}_2$ ($\mathbf{\mu }$m)	${\mathit{W}}_3$ ($\mathbf{\mu }$m)	${\mathit{W}}_4$ ($\mathbf{\mu }$m)	${\mathit{W}}_5$ ($\mathbf{\mu }$m)	${\mathit{W}}_6$ ($\mathbf{\mu }$m)	${\mathit{W}}_7$ ($\mathbf{\mu }$m)	${\mathit{W}}_8$ ($\mathbf{\mu }$m)
Figure 7	$125.64$	$55.35$	$58.41$	$326.97$	$531.99$	-	-	-
Figure 8	$125.64$	$55.35$	$76.68$	$326.97$	$312.48$	$531.99$	$545.76$	-
Figure 9	$125.64$	$55.35$	$78.12$	$76.68$	$531.99$	$531.99$	$545.76$	$545.76$

, for each OTA topology, and include the transistor widths ($W_X$) from Table 2, Table 3 and Table 4. Some electrical characteristics are also summarized in

Table 6. OTA parameters obtained from the first iteration with $g_m/I_D$.

Topology	Av (dB)	BW (MHz)	Gm (mS)	Margin Phase (Deg)	Voltage Offset (mV)
Figure 7	$41.84$	$1.933$	$2.18$	$18.94$	$-314.9$
Figure 8	$47.35$	$0.440$	$2.077$	$53.22$	$344$
Figure 9	$48.66$	$0.445$	$1.312$	$-5.1697$	$-379.7$

, such as open-loop gain ($A_v$), bandwidth ($BW$), transconductance, margin phase, and voltage offset.

4.2. NSGA-II Algorithm

The sizing results given in Table 5 are useful if the design does not require a linear transconductance gain of the OTA. In fact, in the majority of cases, the automated $g_m/I_D$ characterization does not ensure constant transconductance across a linear region, as the one shown in Figure 10. To address this limitation, the proposed work shows the optimization of OTAs to achieve a linear transconductance by combining the $g_m/I_D$ method and NSGA-II algorithm. This sizing approach handles discrete integer variables ($Var1,Var2,\dots$) during design-space exploration and optimizes multiple objectives simultaneously under defined constraints [27]. The sizing process also involves generating SPICE netlists that manipulate integer values that multiply LAMBDA, to produce individuals mapped to the OTA’s physical sizing parameters.

NSGA-II has proven its usefulness for solving complex multi-objective optimization problems in analog integrated circuit design [28]. This evolutionary algorithm excels at balancing the trade-offs between conflicting performance parameters during CMOS OTA transistor sizing.

The proposed automated sizing methodology encodes the OTA circuits in a SPICE-compatible netlist. A DC analysis evaluates the transconductance gain by sweeping the input voltage (from −0.2 V to 0.2 V) and measuring the corresponding output current, plotted on the I–V plane. Figure 10 contrasts the ideal I–V curve with that of a physical CMOS OTA, revealing deviations induced by nonlinearities.

$$RMSE=\sqrt{{\displaystyle \frac{1}{n}}\sum _{i=1}^n{\left(I_{ideal}-I_{real}\right)}^2}$$

(10)

The goal is to maximize transconductance linearity within the [−0.2 V … 0.2 V] range, quantified via the root-mean-squared error (RMSE) that is evaluated by Equation (10). This metric computes the RMS deviation among n sampled points from the ideal and actual current curves, ensuring predictable performance for critical applications such as memristor emulator design.

In the proposed work, NSGA-II is executed by generating an initial population of 20 individuals. These individuals are seeded with baseline values obtained through the $g_m/I_D$ methodology, as given in Table 5 to provide reasonable starting points and constrain the search space. Each individual represents a complete set of transistor dimensions for a specific OTA topology, encoded as integer variables $Va{r}_X$ in the range [40 … 8000]. These integers correspond to multiples of the technology parameter $\lambda$, directly determining the physical $W/L$ ratios of the transistors. Therefore, the objective function is devoted to maximizing a linear transconductance, its associated DC gain, and the inverse value of the power consumed, as given in Equation (11), which includes some constraints.

$$\begin{array}{cc}\hfill \mathbf{maximize}& f_x(\mathrm{Linear}\mathrm{Transconductance},\mathrm{DC}\mathrm{Gain},-\mathrm{Power}\mathrm{consumption})\hfill \\ \hfill \mathbf{subject}\mathbf{to}:& \mathrm{DC}\mathrm{Gain}\ge 40\mathrm{dB},\mathrm{BW}\ge 1M\mathrm{Hz},\mathrm{RMSE}\le {10}^{-9},\mathrm{Phase}\mathrm{Margin}\ge {55}^{°}\hfill \end{array}$$

(11)

The algorithm is executed over 50 generations, with each iteration following the standard NSGA-II workflow (Algorithm 1) to optimize the three objectives defined in Equation (11). The evaluation phase performs SPICE simulations to accurately assess each candidate OTA’s performance metrics, including open-loop voltage gain ($A_v$), bandwidth ($BW$), low power and a special focus on transconductance linearity. This simulation-based approach provides significantly more accurate performance evaluation compared to initial analytical approximations, enabling reliable optimization of the OTA topologies.

Algorithm 1 NSGA-II algorithm

1: Define: Number of generations $G_{max}$, Population size $P_N$, Size of bits for the individuals, Search spaces of the MOSFET parameters (channel W and L)   2: Create a SPICE netlist of the OTA being optimized   3: Initialize the population P based on the first iteration of the design variables $W_X$ using $g_m/I_D$ method   4: Update the design variables values in the SPICE netlist *.lib   5: Assign rank (level) based on Pareto dominance - sort   6: Generate child population   7: Binary tournament selection   8: Recombination and mutation   9: for $G=1$ to $G_{max}$ do 10:    for each Parent and Child in Population do 11:        Assign Rank (level) based on Pareto - sort 12:        Generate sets of non-dominated vectors along PF 13:        Loop (inside) by adding solutions to the next generation starting from the first front until N individuals found determine crowding distance between points on each front 14:    end for 15:    Select points (elitist) on the lower front (with lower rank) and outside a crowding distance 16:    Create next generation0 17:    Binary tournament selection 18:    Recombination and mutation 19: end for 20: $$ 21: return Population from last generation = 0

The optimization process employs simulated binary crossover (SBX), a recombination operator designed for real-valued representations that emulates the behavior of single-point crossover in binary-coded genetic algorithms [29]. In SBX, two parent solutions are combined to produce two offspring whose genes are distributed around the parents’ values according to a probability density function controlled by the distribution index $\eta$. A higher $\eta$ value results in offspring closer to their parents (exploitation), whereas a lower $\eta$ promotes greater diversity (exploration). In this study, the crossover probability $p_c=0.9$ indicates that recombination occurs in 90% of mating events, and the chosen $\eta =15$ provides a balance between exploring new regions of the design space and preserving promising traits from the parents.

Complementing this, polynomial mutation introduces small stochastic perturbations in the offspring’s design variables, ensuring sufficient diversity within the population [29]. This operator modifies each variable with a mutation probability of $p_m=0.5$, according to a polynomial probability distribution governed by the distribution index $\eta =20$. Higher $\eta$ values produce smaller, fine-grained mutations (favoring local search), while lower values allow larger variations (favoring global exploration). By applying controlled perturbations, polynomial mutation helps prevent premature convergence and enhances the algorithm’s ability to escape local optima, thereby improving the robustness of the optimization process.

A critical implementation aspect involves handling design constraints, particularly DC offset, phase margin, transistor saturation conditions, and minimum gain/bandwidth requirements to ensure compliance with target specifications from Table 1. These constraints are incorporated through a penalty mechanism that progressively guides the population toward feasible solutions while maintaining diversity.

The algorithm converges to a Pareto front (PF) of non-dominated solutions representing optimal trade-offs between competing objectives. For the CMOS OTA design, this translates to a configuration set ranging from high-gain/low-speed versions to moderate-gain/wide-bandwidth designs, including intermediate options that balance both parameters while maintaining linear transconductance response. Figure 11 outlines the proposed systematic methodology integrating these computational techniques.

Final sizing results for the optimization of the three OTA topologies provide the transconductance shown in Figure 12, Figure 13 and Figure 14, displaying all 20 candidate solutions for each OTA topology.

Table 7. Last generation with NSGA-II for sizing of OTAs.

Topology	${\mathit{W}}_1$ ($\mathbf{\mu }$m)	${\mathit{W}}_2$ ($\mathbf{\mu }$m)	${\mathit{W}}_3$ ($\mathbf{\mu }$m)	${\mathit{W}}_4$ ($\mathbf{\mu }$m)	${\mathit{W}}_5$ ($\mathbf{\mu }$m)	${\mathit{W}}_6$ ($\mathbf{\mu }$m)	${\mathit{W}}_7$ ($\mathbf{\mu }$m)	${\mathit{W}}_8$ ($\mathbf{\mu }$m)
Figure 7	$75.51$	$39.69$	$10.89$	$176.67$	$531.54$	-	-	-
Figure 8	$341.1$	$50.31$	$493.2$	$390.78$	$473.04$	$248.67$	$626.31$	-
Figure 9	$156.33$	$49.77$	$11.52$	$45.72$	$268.29$	$655.65$	$544.23$	$547.11$

summarizes the optimal configurations, with the best linearity performance (indicated by thick lines in the figures) selected from the Pareto-optimal set.

Table 8. OTA parameters obtained from the last generation with NSGA-II vs. Original OTA from [13].

Topology	Av (dB)	BW (MHz)	Gm (mS)	Margin Phase (Deg)	Voltage Offset (mV)
Original OTA	$45.78$	$2.994$	$2.886$	$9.25$	$-339.2$
Figure 7	$43.51$	$2.069$	$3.224$	$14.47$	$20.76$
Figure 8	$42.62$	$1.992$	$2.947$	$40.2$	$-189.1$
Figure 9	$69.23$	$0.139$	$3.337$	$-26.27$	$31.43$

summarizes the parameters extracted for the OTAs and compares them with those reported for the topology in [13], under equivalent operating conditions. These values were obtained from Figure 15 and Figure 16, which correspond to the DC and AC analyses, respectively.

5. Results for the Emulation of the LIF Neuron Based on the Memristor That Is Designed with Each OTA Topology

To verify the optimal sizing results given in Table 7, and shown in Figure 12, Figure 13 and Figure 14, it is necessary to obtain hysteresis curves of the memristor emulator shown in Figure 6. The characteristic curves shown in Figure 17 demonstrate the optimized OTAs’ performance in memristive emulation applications, where the pinched hysteresis loops reveal critical insights about the nonlinear memristive emulation response and its dependence on transconductance properties.

The LIF neuron shown in Figure 5 is now simulated by using the sizes given in

Table 9. Transistor dimensions for the spiking neuron shown in Figure 5.

Transistor	$\mathit{W}/\mathit{L}$ ($\mathbf{\mu }$m)
$T_{N1}$, $T_{N5}$	$0.24/0.18$
$T_{N2}$, $T_{N3}$, $T_{N6}$, $T_{P3}$, $T_{P4}$	$0.4/0.4$
$T_{N4}$	$0.3/0.3$
$T_{P1}$, $T_{P2}$	$0.5/0.4$

, and also by using the memristor emulators implemented with the three different OTA topologies. The input signal amplitudes must be at least equal to the threshold voltage $V_{th}$ of transistor TN1 to ensure proper activation. Therefore, an amplitude of 0.5 V is selected, consistent with the choice reported in [13]. To select an appropriate signal period, it is necessary to consider the time constant associated with the $R_{TN2\left|\right|TN3}{C}_{int}$ relationship. Using these values, the frequency is calculated as $f_1\approx {\displaystyle \frac{1}{2\pi \left(25\mathrm{k}\right)\left(25\mathrm{pF}\right)}}=254.64$ kHz which corresponds to a period of 3.92 $\mathrm{\mu }$s. This interval is the minimum time for observing the integration process in the neuron. However, for visualization and practical purposes, a frequency of 100 kHz is selected, equivalent to a period of 10 $\mathrm{\mu }$s with a duty cycle of 40% to meet the time condition.

Similarly, the time constant associated with $R_m{C}_m$ is analyzed, yielding $f_2={\displaystyle \frac{1}{2\pi \left(10\mathrm{k}\right)\left(40\mathrm{nF}\right)}}=397.88$ Hz which corresponds to a period of $2.51$ ms, necessary to observe the complete firing cycle of the neuron. Nevertheless, to clearly visualize the contribution of the memristor emulator and the resulting change in the burst firing frequency due to the memristive reset module, the period is set to 5 ms with a duty cycle of 30%.

The initial results are shown in Figure 18 and Figure 19, which use the sizes of the CMOS inverter given in Section 3 (with $C_{int}=25$ pF and $C_m=40$ nF). In the figures it can be appreciated that during the period T = 10 $\mathrm{\mu }$s the three OTA topologies generate different numbers of spikes under identical simulation conditions. This indicates that the transconductance behavior directly affects the memristor emulation stable states and can slow down or speed up the signal.

To assess frequency modulation induced by the memristor emulator, now the CMOS inverter embedded in Figure 6, is resized by considering 100 times the initial W values: $L=1\mathrm{\mu }$m, $W_{MN}=200\mathrm{\mu }$m, and $W_{MP}=1100\mathrm{\mu }$m. The simulation results are presented in Figure 20 and Figure 21, where the differences between the topologies can be observed. However, to enable a more quantitative comparison, the energy consumption per spike was computed using Equation (12),

$$E_{spike}={\displaystyle \frac{{\int }_0^{T}VDD·i\left(\tau \right)d\tau }{N}},$$

(12)

where N denotes the number of spikes occurring within the evaluation interval T.

Table 10. Energy consumed by the spiking neuron shown in Figure 5, using the topologies of the Original OTA taken from [13], and the three optimized ones shown in Figure 7, Figure 8, and Figure 9.

Topology	Inverter Dimension	${\mathit{E}}_{\mathit{spike}}$ ($\mathit{T}=5$ ms)	Total Area
Original OTA	Initial W Values	$211.12$ pJ/spike	$650.7764{\mathrm{\mu }\mathrm{m}}^2$
	100 Times Initial W Values	$2.021$ nJ/spike	$1937.7764{\mathrm{\mu }\mathrm{m}}^2$
Figure 7	Initial W Values	$1.71$ nJ/spike	$1699.3764{\mathrm{\mu }\mathrm{m}}^2$
	100 Times Initial W Values	$20.47$ nJ/spike	$2986.3764{\mathrm{\mu }\mathrm{m}}^2$
Figure 8	Initial W Values	$3.659$ nJ/spike	$6605.0964{\mathrm{\mu }\mathrm{m}}^2$
	100 Times Initial W Values	$46.76$ nJ/spike	$7892.0964{\mathrm{\mu }\mathrm{m}}^2$
Figure 9	Initial W Values	$1.757$ nJ/spike	$4588.0164{\mathrm{\mu }\mathrm{m}}^2$
	100 Times Initial W Values	$21.12$ nJ/spike	$5875.0164{\mathrm{\mu }\mathrm{m}}^2$

summarizes the energy consumption values over the period $T=5$ ms for the neurons implemented with the CMOS inverter of the memristor emulator, using both the initial W values and the scaled values (100 × the initial W). According to Equation (12), the energy consumption is obtained by integrating the current over the pulse duration, multiplying the result by $VDD$, and dividing by the number of generated spikes; this yields the energy consumed per spike.

Although the optimized OTAs do not match the energy consumption reported in the original work [13], the results show that adjusting the transconductance enables control over the firing frequency of the LIF neuron. The table also reports the area occupied by each neuron without capacitor dimensions, which is generally larger than that of the original design in [13], consequently affecting overall energy consumption. It is important to note that the transconductance linearity optimization performed in this work required oversizing certain transistors, making direct power- and area-related comparisons with [13] less favorable. Nevertheless, when comparing the symmetry of transconductance, this work demonstrates a clear improvement over [13].

6. Conclusions

This study demonstrated that the linearity of the transconductance can be effectively optimized while maintaining acceptable performance parameters such as gain and bandwidth, as well as improving offset response and phase margin. However, achieving this level of linearity requires biasing the transistors in strong inversion, which has a direct impact on energy consumption.

Modifying the transconductance of an OTA influences both the symmetry of the CMOS-based memristor emulator and the dynamic evolution of the LIF neuron. As illustrated in Figure 21, the width of each spike is affected by the high-time duration of the signal, indicating that the firing frequency is directly determined by the transconductance value. This implies that different $G_m$ configurations can be used to obtain characteristic bursting frequencies.

Furthermore, the OTA topologies explored in this work were successfully optimized using the hybrid $g_m/I_D$ method in combination with the NSGA-II algorithm with Python 3.11.9 and open-source tools (PDKs).

By combining automated OTA optimization with strategic transistor scaling, this work establishes a co-design framework for tuning neuromorphic dynamics. The findings enable energy-efficient spiking neuron implementations where firing rates can be adjusted for specific applications. Future research should explore large-scale neuronal arrays and advanced-node implementations to further validate scalability.