Search Results (17)

Metal oxides are the most widely used material for the resistive switching layer of memristors. Nevertheless, the majority of oxide-based memristors exhibit binary switching, restricting the emulation of neuronal synaptic behaviors. In this paper, the shift from digital-to-analog switching behavior is achieved by inserting an Al₂O₃ layer atop Zr-doped HfO₂. The TiN/Al₂O₃/HZO/W/Si device exhibits long resistance state retention time and consistency. In addition, by applying a varying voltage, the device exhibits up to 20 continuous resistance states, which is highly significant for high-density storage. Upon the application of a programmable pulse signal, the device’s conductance undergoes continual alteration, reflecting long-term potentiation (LTP) and long-term depression (LTD) synaptic characteristics. The conduction mechanism of the device is studied through physical model fitting and schematic diagrams. Full article

Biological systems learn from past experiences by establishing relationships between two simultaneously occurring events, a phenomenon known as associative learning. This concept has promising applications in modern AI (Artificial Intelligence) and ML (Machine Learning). To leverage it effectively, a precise electrical model that can simulate associative learning observed in biological systems is essential. The paper focuses on modeling Pavlov’s famous experiment related to the drooling of dogs at the sound of bell after associating the food with the bell during training. The study addresses limitations in existing circuit designs that fail to accurately replicate associative learning in dogs, particularly when the sequence of food and bell signals deviates from a specific pattern. We propose a novel design using a few CMOS (Complementary Metal Oxide Semiconductor) transistors and memristor models that produces an output corresponding to the dogs drooling only when food and bell signals are associated, mirroring real-life training conditions. The results section first discusses simulations using the standard TiO₂ (Titanium Oxide) memristor model, followed by experimental results obtained from a classical memristor emulator. Both simulation and experimental findings confirm the effectiveness of the circuit designs. Full article

We explore security aspects of a new computing paradigm that combines novel memristors and traditional Complimentary Metal Oxide Semiconductor (CMOS) to construct a highly efficient analog and/or digital fabric that is especially well-suited to Machine Learning (ML) inference processors for Radio Frequency (RF) signals. Analog and/or hybrid hardware designed for such application areas follows different constraints from that of traditional CMOS. This paradigm shift allows for enhanced capabilities but also introduces novel attack surfaces. Memristors have different properties than traditional CMOS which can potentially be exploited by attackers. In addition, the mixed signal approximate computing model has different vulnerabilities than traditional digital implementations. However both the memristor and the ML computation can be leveraged to create security mechanisms and countermeasures ranging from lightweight cryptography, identifiers (e.g., Physically Unclonable Functions (PUFs), fingerprints, and watermarks), entropy sources, hardware obfuscation and leakage/attack detection methods. Three different threat models are proposed: (1) Supply Chain, (2) Physical Attacks, and (3) Remote Attacks. For each threat model, potential vulnerabilities and defenses are identified. This survey reviews a variety of recent work from the hardware and ML security literature and proposes open problems for both attack and defense. The survey emphasizes the growing area of RF signal analysis and identification in terms of commercial space, as well as military applications and threat models. We differ from other recent surveys that target ML, in general, neglecting RF applications. Full article

Memristors are state-of-the-art, nano-sized, two-terminal, passive electronic elements with very good switching and memory characteristics. Owing to their very low power usage and a good compatibility to the existing CMOS ultra-high-density integrated circuits and chips, they are potentially applicable in artificial and spiking neural networks, memory arrays, and many other devices and circuits for artificial intelligence. In this paper, a complete electronic realization of an analog circuit model of the modified neural net with memristor-based synapses and transfer function with memristors and MOS transistors in LTSPICE is offered. Each synaptic weight is realized by only one memristor, providing enormously reduced circuit complexity. The summing and scaling implementation is founded on op-amps and memristors. The logarithmic-sigmoidal activation function is based on a simple scheme with MOS transistors and memristors. The functioning of the suggested memristor-based neural network for pulse input signals is evaluated both analytically in MATLAB-SIMULINK and in the LTSPICE environment. The obtained results are compared one to another and are successfully verified. The realized memristor-based neural network is an important step towards the forthcoming design of complex memristor-based neural networks for artificial intelligence, for implementation in very high-density integrated circuits and chips. Full article

Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the $X$ variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips. Full article

The design of memristor-based electronic circuits and devices gives researchers opportunities for the engineering of CMOS-memristor-based electronic integrated chips with ultra-high density and various applications. Metal-oxide memristors have good compatibility with the present CMOS integrated circuits technologies. The analysis of new electronic circuits requires suitable software and fast-functioning models. The main purpose of this paper is to propose the application of several modified, simplified, and improved metal-oxide memristor models in electronic devices and provide a comparison of their behavior, basic characteristics, and properties. According to this, LTSPICE is utilized in this paper because it is a free software product with good convergence. Several memristor-based electronic circuits, such as non-volatile passive and hybrid memory crossbars, a neural network, and different reconfigurable devices–filters, an amplifier, and a generator are analyzed in the LTSPICE environment, applying several standards and modified metal-oxide memristor models. After a comparison of the operation of the considered schemes, the main advantages of the modified metal-oxide memristor models, according to their standard analogs, are expressed, including fast operation, good accuracy, respectable convergence, switching properties, and successful applicability in complex electronic circuits. Full article

Memristors, as new electronic elements, have been under rigorous study in recent years, owing to their good memory and switching properties, low power consumption, nano-dimensions and a good compatibility to present integrated circuits, related to their promising applications in electronic circuits and chips. The main purpose of this paper is the application and analysis of the operations of metal–oxide memristors in logic gates and complex schemes, using several standard and modified memristor models and a comparison between their behavior in LTSPICE at a hard-switching, paying attention to their fast operation and switching properties. Several basic logic gates—OR, AND, NOR, NAND, XOR, based on memristors and CMOS transistors are considered. The logic schemes based on memristors are applicable in electronic circuits with artificial intelligence. They are analyzed in LTSPICE for pulse signals and a hard-switching functioning of the memristors. The analyses confirm the proper, fast operation and good switching properties of the considered modified memristor models in logical circuits, compared to several standard models. The modified models are compared to several classical models, according to some significant criteria such as operating frequency, simulation time, accuracy, complexity and switching properties. Based on the basic memristor logic gates, a more complex logic scheme is analyzed. Full article

When deep neural network (DNN) is extensively utilized for edge AI (Artificial Intelligence), for example, the Internet of things (IoT) and autonomous vehicles, it makes CMOS (Complementary Metal Oxide Semiconductor)-based conventional computers suffer from overly large computing loads. Memristor-based devices are emerging as an option to conduct computing in memory for DNNs to make them faster, much more energy efficient, and accurate. Despite having excellent properties, the memristor-based DNNs are yet to be commercially available because of Stuck-At-Fault (SAF) defects. A Mapping Transformation (MT) method is proposed in this paper to mitigate Stuck-at-Fault (SAF) defects from memristor-based DNNs. First, the weight distribution for the VGG8 model with the CIFAR10 dataset is presented and analyzed. Then, the MT method is used for recovering inference accuracies at 0.1% to 50% SAFs with two typical cases, SA1 (Stuck-At-One): SA0 (Stuck-At-Zero) = 5:1 and 1:5, respectively. The experiment results show that the MT method can recover DNNs to their original inference accuracies (90%) when the ratio of SAFs is smaller than 2.5%. Moreover, even when the SAF is in the extreme condition of 50%, it is still highly efficient to recover the inference accuracy to 80% and 21%. What is more, the MT method acts as a regulator to avoid energy and latency overhead generated by SAFs. Finally, the immunity of the MT Method against non-linearity is investigated, and we conclude that the MT method can benefit accuracy, energy, and latency even with high non-linearity LTP = 4 and LTD = −4. Full article

The article presents the results of the development and study of a combined circuitry (compact) model of thin metal oxide films based memristive elements, which makes it possible to simulate both bipolar switching processes and multilevel tuning of the memristor conductivity taking into account the statistical variability of parameters for both device-to-device and cycle-to-cycle switching. The equivalent circuit of the memristive element and the equation system of the proposed model are considered. The software implementation of the model in the MATLAB has been made. The results of modeling static current-voltage characteristics and transient processes during bipolar switching and multilevel turning of the conductivity of memristive elements are obtained. A good agreement between the simulation results and the measured current-voltage characteristics of memristors based on TiO_x films (30 nm) and bilayer TiO₂/Al₂O₃ structures (60 nm/5 nm) is demonstrated. Full article

In this paper, a unified and open linear technology simulation program with integrated circuit emphasis (LTSPICE) memristor library is proposed. It is suitable for the analysis, design, and comparison of the basic memristors and memristor-based circuits. The library could be freely used and expanded with new LTSPICE memristor models. The main existing standard memristor models and several enhanced and modified models based on transition metal oxides such as titanium dioxide, hafnium dioxide, and tantalum oxide are included in the library. LTSPICE is one of the best software for analysis and design of electronic schemes. It is an easy to use, widespread, and free product with very good convergence. Memristors have been under intensive analysis in recent years due to their nano-dimensions, low power consumption, high switching speed, and good compatibility with traditional complementary metal oxide semiconductor (CMOS) technology. In this work, their behavior and potential applications in artificial neural networks, reconfigurable schemes, and memory crossbars are investigated using the considered memristor models in the proposed LTSPICE library. Furthermore, a detailed comparison of the presented LTSPICE memristor model library is conducted and related to specific criteria, such as switching speed, operating frequencies, nonlinear ionic drift representation, boundary effects, switching modes, and others. Full article

Memristor crossbar arrays without selector devices, such as complementary-metal oxide semiconductor (CMOS) devices, are a potential for realizing neuromorphic computing systems. However, wire resistance of metal wires is one of the factors that degrade the performance of memristor crossbar circuits. In this work, we propose a wire resistance modeling method and a parasitic resistance-adapted programming scheme to reduce the impact of wire resistance in a memristor crossbar-based neuromorphic computing system. The equivalent wire resistances for the cells are estimated by analyzing the crossbar circuit using the superposition theorem. For the conventional programming scheme, the connection matrix composed of the target memristance values is used for crossbar array programming. In the proposed parasitic resistance-adapted programming scheme, the connection matrix is updated before it is used for crossbar array programming to compensate the equivalent wire resistance. The updated connection matrix is obtained by subtracting the equivalent connection matrix from the original connection matrix. The circuit simulations are performed to test the proposed wire resistance modeling method and the parasitic resistance-adapted programming scheme. The simulation results showed that the discrepancy of the output voltages of the crossbar between the conventional wire resistance modeling method and the proposed wire resistance modeling method is as low as 2.9% when wire resistance varied from 0.5 to 3.0 Ω. The recognition rate of the memristor crossbar with the conventional programming scheme is 99%, 95%, 81%, and 65% when wire resistance is set to be 1.5, 2.0, 2.5, and 3.0 Ω, respectively. By contrast, the memristor crossbar with the proposed parasitic resistance-adapted programming scheme can maintain the recognition as high as 100% when wire resistance is as high as 3.0 Ω. Full article

The transport and synaptic characteristics of the two-terminal Au/Ti/ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO)/thin SiO₂/p⁺-Si memristors based on the modulation of the Schottky barrier (SB) between the resistive switching (RS) oxide layer and the metal electrodes are investigated by modulating the oxygen content in the a-IGZO film with the emphasis on the mechanism that determines the boundary of the abrupt/gradual RS. It is found that a bimodal distribution of the effective SB height (Φ_B) results from further reducing the top electrode voltage (V_TE)-dependent Fermi-level (E_F) followed by the generation of ionized oxygen vacancies (V_O²⁺s). Based on the proposed model, the influences of the readout voltage, the oxygen content, the number of consecutive V_TE sweeps on Φ_B, and the memristor current are explained. In particular, the process of V_O²⁺ generation followed by the Φ_B lowering is gradual because increasing the V_TE-dependent E_F lowering followed by the V_O²⁺ generation is self-limited by increasing the electron concentration-dependent E_F heightening. Furthermore, we propose three operation regimes: the readout, the potentiation in gradual RS, and the abrupt RS. Our results prove that the Au/Ti/a-IGZO/SiO₂/p⁺-Si memristors are promising for the monolithic integration of neuromorphic computing systems because the boundary between the gradual and abrupt RS can be controlled by modulating the SiO₂ thickness and IGZO work function. Full article

Hierarchical Temporal Memory (HTM) has been known as a software framework to model the brain’s neocortical operation. However, mimicking the brain’s neocortical operation by not software but hardware is more desirable, because the hardware can not only describe the neocortical operation, but can also employ the brain’s architectural advantages. To develop a hybrid circuit of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) for realizing HTM’s spatial pooler (SP) by hardware, memristor defects such as stuck-at-faults and variations should be considered. For solving the defect problem, we first show that the boost-factor adjustment can make HTM’s SP defect-tolerant, because the false activation of defective columns are suppressed. Second, we propose a memristor-CMOS hybrid circuit with the boost-factor adjustment to realize this defect-tolerant SP by hardware. The proposed circuit does not rely on the conventional defect-aware mapping scheme, which cannot avoid the false activation of defective columns. For the Modified subset of National Institute of Standards and Technology (MNIST) vectors, the boost-factor adjusted crossbar with defects = 10% shows a rate loss of only ~0.6%, compared to the ideal crossbar with defects = 0%. On the contrary, the defect-aware mapping without the boost-factor adjustment demonstrates a significant rate loss of ~21.0%. The energy overhead of the boost-factor adjustment is only ~0.05% of the programming energy of memristor synapse crossbar. Full article

Silicon oxide-based memristors have been extensively studied due to their compatibility with the dominant silicon complementary metal–oxide–semiconductor (CMOS) fabrication technology. However, the variability of resistance switching (RS) parameters is one of the major challenges for commercialization applications. Owing to the filamentary nature of most RS devices, the variability of RS parameters can be reduced by doping in the RS region, where conductive filaments (CFs) can grow along the locations of impurities. In this work, we have successfully obtained RS characteristics in Pt dispersed silicon oxide-based memristors. The RS variabilities and mechanisms have been analyzed by screening the statistical data into different resistance ranges, and the distributions are shown to be compatible with a Weibull distribution. Additionally, a quantum points contact (QPC) model has been validated to account for the conductive mechanism and further sheds light on the evolution of the CFs during RS processes. Full article

The investigation of new memory circuits is very important for the development of future generations’ non-volatile and Random Access Memories (RAM) memories and modern schemes for in-memory calculations. The purpose of the present research is to propose a detailed analysis of passive and hybrid memristor-based memory crossbars with separating metal oxide semiconductor (MOS) transistors. The considered memristors are based on HfO₂. The transistors are applied to eliminate the parasitic paths in the schemes. For simulations, a previously proposed strongly nonlinear modified window function by the author together with a physical nonlinear memristor model is used. The considered model is adjusted according to the experimental i–v relationship of HfO₂ memristors. The i–v relationship obtained by the simulation is successfully fitted to the respective relationship derived by physical measurements. A good coincidence between these characteristics is established. Several basic window functions are also applied for comparison to the corresponding results. The proposed model is analyzed in Personal Simulation Program with Integrated Circuit Emphasis (PSpice) and it is also used for simulation of a 5 × 5 fragment of a memristor memory crossbar with isolating transistors and for the analysis of a 6 × 6 passive memory matrix. The investigated matrices are simulated for writing, reading, and erasing information. It is established that the model proposed could be used for simulations of complex memristor circuits. Full article