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Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems
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Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Artificial Intelligence".

Deadline for manuscript submissions: closed (21 December 2019) | Viewed by 30165

Printed Edition Available!
A printed edition of this Special Issue is available here.

Special Issue Editor

Prof. Dr. Seongjae Cho

E-Mail Website
Guest Editor
Department of Electronics Engineering, Gachon University, Seongnam-si 13120, Gyeonggi-do, Korea
Interests: advanced CMOS devices; emerging volatile/nonvolatile memory devices; synaptic devices and neuromorphic system; photonic devices and integrated circuits

Special Issue Information

Dear Colleagues,

This Special Issue aims to convey the most recent progresses in hardware-driven neuromorphic systems. The machine learning system and various types of artificial neural networks to realize the learning process have been mainly focused on software technologies. Tremendous advances have been made particularly in the area of recognition, in which humans have great superiority compared to computers. For higher resemblance with the biological nervous system, the upcoming progresses are ought to take power consumption into account and foster revolutions in the electron devices and integrated circuits that make up the neuromorphic system.

For this Special Issue, we cordially invite contributions related to state-of-the-art technologies for neuromorphic systems more intimately oriented to hardware developments. Topics of interest include but are not limited to: mathematical and physical theories and modeling with practical implications in hardware representation, synaptic components including novel solid-state logic and memory devices, neuron circuits with power-efficient transistors, metallic and optical interconnects, novel software algorithms optimally prepared for specific types of synaptic devices, floor plans for synapse and neuron circuits in either two- or three-dimensional architectures, emulation of neural chips compatible with conventional computers, measurement techniques, and time- and cost-effective process integration for realizing these systems.

Prof. Dr. Seongjae Cho
Guest Editor

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Keywords

  • Hardware-driven neuromorphic system
  • Machine learning
  • Artificial neural network
  • Mathematical and physical theories, modeling, and algorithms
  • Synaptic electron devices
  • Solid-state logic and memory devices
  • Neuron circuits
  • Neural chip emulation
  • Process integration

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Published Papers (7 papers)

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10 pages, 4005 KiB  
Article
3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application
by Hyun-Seok Choi, Yu Jeong Park, Jong-Ho Lee and Yoon Kim
Electronics 2020, 9(1), 57; https://doi.org/10.3390/electronics9010057 - 30 Dec 2019
Cited by 23 | Viewed by 6577
Abstract
In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. [...] Read more.
In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. In our previous work, we proposed the 3-D synapse array architecture based on a charge-trap flash (CTF) memory. It has the advantages of high-density integration of 3-D stacking technology and excellent reliability characteristics of mature CTF device technology. This paper examines some issues of the 3-D synapse array architecture. Also, we propose an improved structure and programming method compared to the previous work. The synaptic characteristics of the proposed method are closely examined and validated through a technology computer-aided design (TCAD) device simulation and a system-level simulation for the pattern recognition task. The proposed technology will be the promising solution for high-performance and high-reliability of neuromorphic hardware systems. Full article
(This article belongs to the Special Issue Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems)
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8 pages, 2077 KiB  
Article
Solving Overlapping Pattern Issues in On-Chip Learning of Bio-Inspired Neuromorphic System with Synaptic Transistors
by Hyungjin Kim and Byung-Gook Park
Electronics 2020, 9(1), 13; https://doi.org/10.3390/electronics9010013 - 21 Dec 2019
Cited by 2 | Viewed by 3416
Abstract
Recently, bio-inspired neuromorphic systems have been attracting widespread interest thanks to their energy-efficiency compared to conventional von Neumann architecture computing systems. Previously, we reported a silicon synaptic transistor with an asymmetric dual-gate structure for the direct connection between synaptic devices and neuron circuits. [...] Read more.
Recently, bio-inspired neuromorphic systems have been attracting widespread interest thanks to their energy-efficiency compared to conventional von Neumann architecture computing systems. Previously, we reported a silicon synaptic transistor with an asymmetric dual-gate structure for the direct connection between synaptic devices and neuron circuits. In this study, we study a hardware-based spiking neural network for pattern recognition using a binary modified National Institute of Standards and Technology (MNIST) dataset with a device model. A total of three systems were compared with regard to learning methods, and it was confirmed that the feature extraction of each pattern is the most crucial factor to avoiding overlapping pattern issues and obtaining a high pattern classification ability. Full article
(This article belongs to the Special Issue Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems)
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6 pages, 1328 KiB  
Article
Analysis of the Voltage-Dependent Plasticity in Organic Neuromorphic Devices
by Seunghyuk Lee and Chang-Hyun Kim
Electronics 2020, 9(1), 4; https://doi.org/10.3390/electronics9010004 - 18 Dec 2019
Cited by 5 | Viewed by 3606
Abstract
The bias-dependent signal transmission of flexible synaptic transistors is investigated. The novel neuromorphic devices are fabricated on a thin and transparent plastic sheet, incorporating a high-performance organic semiconductor, dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene, into the active channel. Upon spike emulation at different synaptic voltages, the short-term plasticity [...] Read more.
The bias-dependent signal transmission of flexible synaptic transistors is investigated. The novel neuromorphic devices are fabricated on a thin and transparent plastic sheet, incorporating a high-performance organic semiconductor, dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene, into the active channel. Upon spike emulation at different synaptic voltages, the short-term plasticity feature of the devices is substantially modulated. By adopting an iterative model for the synaptic output currents, key physical parameters associated with the charge carrier dynamics are estimated. The correlative extraction approach is found to yield the close fits to the experimental results, and the systematic evolution of the timing constants is rationalized. Full article
(This article belongs to the Special Issue Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems)
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15 pages, 1292 KiB  
Article
Benchmarking a Many-Core Neuromorphic Platform With an MPI-Based DNA Sequence Matching Algorithm
by Gianvito Urgese, Francesco Barchi, Emanuele Parisi, Evelina Forno, Andrea Acquaviva and Enrico Macii
Electronics 2019, 8(11), 1342; https://doi.org/10.3390/electronics8111342 - 14 Nov 2019
Cited by 4 | Viewed by 2615
Abstract
SpiNNaker is a neuromorphic globally asynchronous locally synchronous (GALS) multi-core architecture designed for simulating a spiking neural network (SNN) in real-time. Several studies have shown that neuromorphic platforms allow flexible and efficient simulations of SNN by exploiting the efficient communication infrastructure optimised for [...] Read more.
SpiNNaker is a neuromorphic globally asynchronous locally synchronous (GALS) multi-core architecture designed for simulating a spiking neural network (SNN) in real-time. Several studies have shown that neuromorphic platforms allow flexible and efficient simulations of SNN by exploiting the efficient communication infrastructure optimised for transmitting small packets across the many cores of the platform. However, the effectiveness of neuromorphic platforms in executing massively parallel general-purpose algorithms, while promising, is still to be explored. In this paper, we present an implementation of a parallel DNA sequence matching algorithm implemented by using the MPI programming paradigm ported to the SpiNNaker platform. In our implementation, all cores available in the board are configured for executing in parallel an optimised version of the Boyer-Moore (BM) algorithm. Exploiting this application, we benchmarked the SpiNNaker platform in terms of scalability and synchronisation latency. Experimental results indicate that the SpiNNaker parallel architecture allows a linear performance increase with the number of used cores and shows better scalability compared to a general-purpose multi-core computing platform. Full article
(This article belongs to the Special Issue Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems)
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12 pages, 4499 KiB  
Article
A Silicon-Compatible Synaptic Transistor Capable of Multiple Synaptic Weights toward Energy-Efficient Neuromorphic Systems
by Eunseon Yu, Seongjae Cho and Byung-Gook Park
Electronics 2019, 8(10), 1102; https://doi.org/10.3390/electronics8101102 - 30 Sep 2019
Cited by 10 | Viewed by 3333
Abstract
In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and [...] Read more.
In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and Si processing compatibility. In this work, we design a synaptic transistor with short-term and long-term plasticity, high density, high reliability and energy efficiency, and Si processing compatibility. The synaptic characteristics of the device are closely examined and validated through technology computer-aided design (TCAD) device simulation. Consequently, full synaptic functions with high energy efficiency have been realized. Full article
(This article belongs to the Special Issue Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems)
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11 pages, 2356 KiB  
Article
Control of the Boundary between the Gradual and Abrupt Modulation of Resistance in the Schottky Barrier Tunneling-Modulated Amorphous Indium-Gallium-Zinc-Oxide Memristors for Neuromorphic Computing
by Jun Tae Jang, Geumho Ahn, Sung-Jin Choi, Dong Myong Kim and Dae Hwan Kim
Electronics 2019, 8(10), 1087; https://doi.org/10.3390/electronics8101087 - 25 Sep 2019
Cited by 18 | Viewed by 4410
Abstract
The transport and synaptic characteristics of the two-terminal Au/Ti/ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO)/thin SiO2/p+-Si memristors based on the modulation of the Schottky barrier (SB) between the resistive switching (RS) oxide layer and the metal electrodes are investigated by modulating the [...] Read more.
The transport and synaptic characteristics of the two-terminal Au/Ti/ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO)/thin SiO2/p+-Si memristors based on the modulation of the Schottky barrier (SB) between the resistive switching (RS) oxide layer and the metal electrodes are investigated by modulating the oxygen content in the a-IGZO film with the emphasis on the mechanism that determines the boundary of the abrupt/gradual RS. It is found that a bimodal distribution of the effective SB height (ΦB) results from further reducing the top electrode voltage (VTE)-dependent Fermi-level (EF) followed by the generation of ionized oxygen vacancies (VO2+s). Based on the proposed model, the influences of the readout voltage, the oxygen content, the number of consecutive VTE sweeps on ΦB, and the memristor current are explained. In particular, the process of VO2+ generation followed by the ΦB lowering is gradual because increasing the VTE-dependent EF lowering followed by the VO2+ generation is self-limited by increasing the electron concentration-dependent EF heightening. Furthermore, we propose three operation regimes: the readout, the potentiation in gradual RS, and the abrupt RS. Our results prove that the Au/Ti/a-IGZO/SiO2/p+-Si memristors are promising for the monolithic integration of neuromorphic computing systems because the boundary between the gradual and abrupt RS can be controlled by modulating the SiO2 thickness and IGZO work function. Full article
(This article belongs to the Special Issue Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems)
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19 pages, 2691 KiB  
Article
A Spiking Neural Network Based on the Model of VO2–Neuron
by Maksim Belyaev and Andrei Velichko
Electronics 2019, 8(10), 1065; https://doi.org/10.3390/electronics8101065 - 20 Sep 2019
Cited by 15 | Viewed by 5604
Abstract
In this paper, we present an electrical circuit of a leaky integrate-and-fire neuron with one VO2 switch, which models the properties of biological neurons. Based on VO2 neurons, a two-layer spiking neural network consisting of nine input and three output neurons [...] Read more.
In this paper, we present an electrical circuit of a leaky integrate-and-fire neuron with one VO2 switch, which models the properties of biological neurons. Based on VO2 neurons, a two-layer spiking neural network consisting of nine input and three output neurons is modeled in the SPICE simulator. The network contains excitatory and inhibitory couplings, and implements the winner-takes-all principle in pattern recognition. Using a supervised Spike-Timing-Dependent Plasticity training method and a timing method of information coding, the network was trained to recognize three patterns with dimensions of 3 × 3 pixels. The neural network is able to recognize up to 105 images per second, and has the potential to increase the recognition speed further. Full article
(This article belongs to the Special Issue Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems)
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