Special Issue "Hardware-Driven Neuromorphic System: Theories, Components, and Integrated Circuits"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Artificial Intelligence".

Deadline for manuscript submissions: 30 November 2019.

Special Issue Editor

Prof. Dr. Seongjae Cho
E-Mail Website
Guest Editor
Department of Electronics Engineering, Gachon University, Gyeonggi-do 13120, Korea
Interests: Advanced CMOS devices, emerging volatile/nonvolatile memory devices, synaptic devices and neuromorphic system, photonic devices and integrated circuits

Special Issue Information

Dear Colleagues,

This Special Issue aims to convey the most recent progresses in hardware-driven neuromorphic systems. The machine learning system and various types of artificial neural networks to realize the learning process have been mainly focused on software technologies. Tremendous advances have been made particularly in the area of recognition, in which humans have great superiority compared to computers. For higher resemblance with the biological nervous system, the upcoming progresses are ought to take power consumption into account and foster revolutions in the electron devices and integrated circuits that make up the neuromorphic system.

For this Special Issue, we cordially invite contributions related to state-of-the-art technologies for neuromorphic systems more intimately oriented to hardware developments. Topics of interest include but are not limited to: mathematical and physical theories and modeling with practical implications in hardware representation, synaptic components including novel solid-state logic and memory devices, neuron circuits with power-efficient transistors, metallic and optical interconnects, novel software algorithms optimally prepared for specific types of synaptic devices, floor plans for synapse and neuron circuits in either two- or three-dimensional architectures, emulation of neural chips compatible with conventional computers, measurement techniques, and time- and cost-effective process integration for realizing these systems.

Prof. Dr. Seongjae Cho
Guest Editor

Manuscript Submission Information

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Keywords

  • Hardware-driven neuromorphic system
  • Machine learning
  • Artificial neural network
  • Mathematical and physical theories, modeling, and algorithms
  • Synaptic electron devices
  • Solid-state logic and memory devices
  • Neuron circuits
  • Neural chip emulation
  • Process integration

Published Papers (4 papers)

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Research

Open AccessFeature PaperArticle
Benchmarking a Many-Core Neuromorphic Platform With an MPI-Based DNA Sequence Matching Algorithm
Electronics 2019, 8(11), 1342; https://doi.org/10.3390/electronics8111342 - 14 Nov 2019
Abstract
SpiNNaker is a neuromorphic globally asynchronous locally synchronous (GALS) multi-core architecture designed for simulating a spiking neural network (SNN) in real-time. Several studies have shown that neuromorphic platforms allow flexible and efficient simulations of SNN by exploiting the efficient communication infrastructure optimised for [...] Read more.
SpiNNaker is a neuromorphic globally asynchronous locally synchronous (GALS) multi-core architecture designed for simulating a spiking neural network (SNN) in real-time. Several studies have shown that neuromorphic platforms allow flexible and efficient simulations of SNN by exploiting the efficient communication infrastructure optimised for transmitting small packets across the many cores of the platform. However, the effectiveness of neuromorphic platforms in executing massively parallel general-purpose algorithms, while promising, is still to be explored. In this paper, we present an implementation of a parallel DNA sequence matching algorithm implemented by using the MPI programming paradigm ported to the SpiNNaker platform. In our implementation, all cores available in the board are configured for executing in parallel an optimised version of the Boyer-Moore (BM) algorithm. Exploiting this application, we benchmarked the SpiNNaker platform in terms of scalability and synchronisation latency. Experimental results indicate that the SpiNNaker parallel architecture allows a linear performance increase with the number of used cores and shows better scalability compared to a general-purpose multi-core computing platform. Full article
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Open AccessFeature PaperArticle
A Silicon-Compatible Synaptic Transistor Capable of Multiple Synaptic Weights toward Energy-Efficient Neuromorphic Systems
Electronics 2019, 8(10), 1102; https://doi.org/10.3390/electronics8101102 - 30 Sep 2019
Abstract
In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and [...] Read more.
In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and Si processing compatibility. In this work, we design a synaptic transistor with short-term and long-term plasticity, high density, high reliability and energy efficiency, and Si processing compatibility. The synaptic characteristics of the device are closely examined and validated through technology computer-aided design (TCAD) device simulation. Consequently, full synaptic functions with high energy efficiency have been realized. Full article
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Open AccessFeature PaperArticle
Control of the Boundary between the Gradual and Abrupt Modulation of Resistance in the Schottky Barrier Tunneling-Modulated Amorphous Indium-Gallium-Zinc-Oxide Memristors for Neuromorphic Computing
Electronics 2019, 8(10), 1087; https://doi.org/10.3390/electronics8101087 - 25 Sep 2019
Abstract
The transport and synaptic characteristics of the two-terminal Au/Ti/ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO)/thin SiO2/p+-Si memristors based on the modulation of the Schottky barrier (SB) between the resistive switching (RS) oxide layer and the metal electrodes are investigated by modulating the [...] Read more.
The transport and synaptic characteristics of the two-terminal Au/Ti/ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO)/thin SiO2/p+-Si memristors based on the modulation of the Schottky barrier (SB) between the resistive switching (RS) oxide layer and the metal electrodes are investigated by modulating the oxygen content in the a-IGZO film with the emphasis on the mechanism that determines the boundary of the abrupt/gradual RS. It is found that a bimodal distribution of the effective SB height (ΦB) results from further reducing the top electrode voltage (VTE)-dependent Fermi-level (EF) followed by the generation of ionized oxygen vacancies (VO2+s). Based on the proposed model, the influences of the readout voltage, the oxygen content, the number of consecutive VTE sweeps on ΦB, and the memristor current are explained. In particular, the process of VO2+ generation followed by the ΦB lowering is gradual because increasing the VTE-dependent EF lowering followed by the VO2+ generation is self-limited by increasing the electron concentration-dependent EF heightening. Furthermore, we propose three operation regimes: the readout, the potentiation in gradual RS, and the abrupt RS. Our results prove that the Au/Ti/a-IGZO/SiO2/p+-Si memristors are promising for the monolithic integration of neuromorphic computing systems because the boundary between the gradual and abrupt RS can be controlled by modulating the SiO2 thickness and IGZO work function. Full article
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Open AccessArticle
A Spiking Neural Network Based on the Model of VO2–Neuron
Electronics 2019, 8(10), 1065; https://doi.org/10.3390/electronics8101065 - 20 Sep 2019
Abstract
In this paper, we present an electrical circuit of a leaky integrate-and-fire neuron with one VO2 switch, which models the properties of biological neurons. Based on VO2 neurons, a two-layer spiking neural network consisting of nine input and three output neurons [...] Read more.
In this paper, we present an electrical circuit of a leaky integrate-and-fire neuron with one VO2 switch, which models the properties of biological neurons. Based on VO2 neurons, a two-layer spiking neural network consisting of nine input and three output neurons is modeled in the SPICE simulator. The network contains excitatory and inhibitory couplings, and implements the winner-takes-all principle in pattern recognition. Using a supervised Spike-Timing-Dependent Plasticity training method and a timing method of information coding, the network was trained to recognize three patterns with dimensions of 3 × 3 pixels. The neural network is able to recognize up to 105 images per second, and has the potential to increase the recognition speed further. Full article
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