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Special Issue "Memristors for Neuromorphic Circuits and Artificial Intelligence Applications"

A special issue of Materials (ISSN 1996-1944).

Deadline for manuscript submissions: 31 October 2019.

Special Issue Editor

Guest Editor
Prof. Dr. Jordi Suñé

Universitat Autònoma de Barcelona, Departament d‘Enginyeria Electrònica, Barcelona, Spain
Website | E-Mail
Phone: +34 935 813 527
Fax: +34 935 812 600
Interests: memristors; neuromorphic circuits; deep learning applications; deep-learning in hardware; artificial intelligence

Special Issue Information

Dear Colleagues,

Machine learning is impacting our society in every corner. This is the artificial intelligence (AI) revolution. From medical to automotive application, from preventive maintenance to global climate forecasting and prevention, from the management of emergencies to the prevention of terrorist attacks, deep-learning-based AI is continuously penetrating our daily lives. AI is a pervasive technology that, presently is mainly implemented in software. However, the solid-state nanoelectronic implementation of the memristor (for the first time in 2008 by the HP group), predicted by Prof. Leon Chua in 1971 using symmetry arguments, opens up a new frontier for AI applications: Deep learning ICs. Less-known by the general public, these hardware-based neuromeorphic systems will allow distributed energy-efficient deployment of AI in many areas requiring real-time response, intelligent decision and fast action. In this Special Issue we will try to give a general overview of this new technology. We will review the concepts of machine learning and deep learning, with a focus on their applications. We will cover the state-of-the-art technological implementation of memristor electron devices with particular emphasis on resistive devices (both ReRAM and PCM). We will also present the actual state-of-the-art of memristor-based deep learning prototypes for different applications. Finally, we will dedicate a few papers to ethical issues related to AI (and also to neurosciences). These two technologies have many potential applications that will aid to face global societal challenges (AI for the Good). However, there are also many serious ethical challenges to be faced because the coupling of these technologies have also many negative applications (AI for the Devil) that might even put the future of humanity at serious risk.

Prof. Dr. Jordi Suñé
Guest Editor

Manuscript Submission Information

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Keywords

  • memristors
  • artificial intelligence
  • hardware-based deep learning ICs

Published Papers (4 papers)

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Research

Open AccessArticle
On the Application of a Diffusive Memristor Compact Model to Neuromorphic Circuits
Materials 2019, 12(14), 2260; https://doi.org/10.3390/ma12142260
Received: 30 May 2019 / Revised: 1 July 2019 / Accepted: 8 July 2019 / Published: 13 July 2019
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Abstract
Memristive devices have found application in both random access memory and neuromorphic circuits. In particular, it is known that their behavior resembles that of neuronal synapses. However, it is not simple to come by samples of memristors and adjusting their parameters to change [...] Read more.
Memristive devices have found application in both random access memory and neuromorphic circuits. In particular, it is known that their behavior resembles that of neuronal synapses. However, it is not simple to come by samples of memristors and adjusting their parameters to change their response requires a laborious fabrication process. Moreover, sample to sample variability makes experimentation with memristor-based synapses even harder. The usual alternatives are to either simulate or emulate the memristive systems under study. Both methodologies require the use of accurate modeling equations. In this paper, we present a diffusive compact model of memristive behavior that has already been experimentally validated. Furthermore, we implement an emulation architecture that enables us to freely explore the synapse-like characteristics of memristors. The main advantage of emulation over simulation is that the former allows us to work with real-world circuits. Our results can give some insight into the desirable characteristics of the memristors for neuromorphic applications. Full article
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Graphical abstract

Open AccessArticle
Hybrid Circuit of Memristor and Complementary Metal-Oxide-Semiconductor for Defect-Tolerant Spatial Pooling with Boost-Factor Adjustment
Materials 2019, 12(13), 2122; https://doi.org/10.3390/ma12132122
Received: 17 June 2019 / Revised: 27 June 2019 / Accepted: 29 June 2019 / Published: 1 July 2019
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Abstract
Hierarchical Temporal Memory (HTM) has been known as a software framework to model the brain’s neocortical operation. However, mimicking the brain’s neocortical operation by not software but hardware is more desirable, because the hardware can not only describe the neocortical operation, but can [...] Read more.
Hierarchical Temporal Memory (HTM) has been known as a software framework to model the brain’s neocortical operation. However, mimicking the brain’s neocortical operation by not software but hardware is more desirable, because the hardware can not only describe the neocortical operation, but can also employ the brain’s architectural advantages. To develop a hybrid circuit of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) for realizing HTM’s spatial pooler (SP) by hardware, memristor defects such as stuck-at-faults and variations should be considered. For solving the defect problem, we first show that the boost-factor adjustment can make HTM’s SP defect-tolerant, because the false activation of defective columns are suppressed. Second, we propose a memristor-CMOS hybrid circuit with the boost-factor adjustment to realize this defect-tolerant SP by hardware. The proposed circuit does not rely on the conventional defect-aware mapping scheme, which cannot avoid the false activation of defective columns. For the Modified subset of National Institute of Standards and Technology (MNIST) vectors, the boost-factor adjusted crossbar with defects = 10% shows a rate loss of only ~0.6%, compared to the ideal crossbar with defects = 0%. On the contrary, the defect-aware mapping without the boost-factor adjustment demonstrates a significant rate loss of ~21.0%. The energy overhead of the boost-factor adjustment is only ~0.05% of the programming energy of memristor synapse crossbar. Full article
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Figure 1

Open AccessArticle
Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons
Materials 2019, 12(6), 875; https://doi.org/10.3390/ma12060875
Received: 24 February 2019 / Revised: 9 March 2019 / Accepted: 13 March 2019 / Published: 15 March 2019
Cited by 1 | PDF Full-text (2442 KB) | HTML Full-text | XML Full-text
Abstract
As a software framework, Hierarchical Temporal Memory (HTM) has been developed to perform the brain’s neocortical functions, such as spatial and temporal pooling. However, it should be realized with hardware not software not only to mimic the neocortical function but also to exploit [...] Read more.
As a software framework, Hierarchical Temporal Memory (HTM) has been developed to perform the brain’s neocortical functions, such as spatial and temporal pooling. However, it should be realized with hardware not software not only to mimic the neocortical function but also to exploit its architectural benefit. To do so, we propose a new memristor-CMOS (Complementary Metal-Oxide-Semiconductor) hybrid circuit of temporal-pooling here, which is composed of the input-layer and output-layer neurons mimicking the neocortex. In the hybrid circuit, the input-layer neurons have the proximal and basal/distal dendrites to combine sensory information with the temporal/location information from the brain’s hippocampus. Using the same crossbar architecture, the output-layer neurons can perform a prediction by integrating the temporal information on the basal/distal dendrites. For training the proposed circuit, we used only simple Hebbian learning, not the complicated backpropagation algorithm. Due to the simple hardware of Hebbian learning, the proposed hybrid circuit can be very suitable to online learning. The proposed memristor-CMOS hybrid circuit has been verified by the circuit simulation using the real memristor model. The proposed circuit has been verified to predict both the ordinal and out-of-order sequences. In addition, the proposed circuit has been tested with the external noise and memristance variation. Full article
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Open AccessArticle
Bipolar Analog Memristors as Artificial Synapses for Neuromorphic Computing
Materials 2018, 11(11), 2102; https://doi.org/10.3390/ma11112102
Received: 10 September 2018 / Revised: 18 October 2018 / Accepted: 23 October 2018 / Published: 26 October 2018
Cited by 3 | PDF Full-text (4088 KB) | HTML Full-text | XML Full-text
Abstract
Synaptic devices with bipolar analog resistive switching behavior are the building blocks for memristor-based neuromorphic computing. In this work, a fully complementary metal-oxide semiconductor (CMOS)-compatible, forming-free, and non-filamentary memristive device (Pd/Al2O3/TaOx/Ta) with bipolar analog switching behavior is [...] Read more.
Synaptic devices with bipolar analog resistive switching behavior are the building blocks for memristor-based neuromorphic computing. In this work, a fully complementary metal-oxide semiconductor (CMOS)-compatible, forming-free, and non-filamentary memristive device (Pd/Al2O3/TaOx/Ta) with bipolar analog switching behavior is reported as an artificial synapse for neuromorphic computing. Synaptic functions, including long-term potentiation/depression, paired-pulse facilitation (PPF), and spike-timing-dependent plasticity (STDP), are implemented based on this device; the switching energy is around 50 pJ per spike. Furthermore, for applications in artificial neural networks (ANN), determined target conductance states with little deviation (<1%) can be obtained with random initial states. However, the device shows non-linear conductance change characteristics, and a nearly linear conductance change behavior is obtained by optimizing the training scheme. Based on these results, the device is a promising emulator for biology synapses, which could be of great benefit to memristor-based neuromorphic computing. Full article
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Figure 1

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