Search Results (16)

Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device characteristics, and, to study this effect, this work investigates the impact of RITs on the DC/AC/RF characteristic fluctuations of FinFETs. Under high gate bias, the device screening effect suppresses large fluctuations induced by RITs. In relation to different densities of interface traps (D_it), fluctuations of short-channel effects, including potential barriers and current densities, are analyzed. Bulk FinFETs exhibit entirely different variability, despite having the same number of RITs. Potential barriers are significantly altered when devices with RITs are located near the source end. An analysis and a discussion of RIT-fluctuated gate capacitances, transconductances, cut-off, and 3-dB frequencies are provided. Under high D_it conditions, we observe ~146% variation in off-state current, ~26% in threshold voltage, and large fluctuations of ~107% and ~131% in gain and cut-off frequency, respectively. The effects of the random position of RITs on both AC and RF characteristic fluctuations are also discussed and designed in three different scenarios. Across all densities of interface traps, the device with RITs near the drain end exhibits relatively minimal fluctuations in gate capacitance, voltage gain, cut-off, and 3-dB frequencies. Full article

Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸$Ni$ and ²⁸$Si$, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs. Full article

The HCI effect has been the focus of research as a common reliability consideration under advanced nodes in semiconductors. In this paper, a new compact model that takes into account the self-heating effect, width dependence, and substrate voltage dependence is proposed in the framework of a self-saturated power–law model containing oxide defects. The compact model employs different parameters in different carrier energy regions to improve the accuracy of the model. The predictions of the model fit well with experimental data extracted from the literature and the TCAD data, proving the validity of the model. Meanwhile, the model is used in this paper to predict and analyze the HCI’s degradation as well as lifetime under different conditions. Full article

The surge in demand for 3D MOSFETs, such as FinFETs, driven by recent technological advances, is explored in this review. FinFETs, positioned as promising alternatives to bulk CMOS, exhibit favorable electrostatic characteristics and offer power/performance benefits, scalability, and control over short-channel effects. Simulations provide insights into functionality and leakage, addressing off-current issues common in narrow band-gap materials within a CMOS-compatible process. Multiple structures have been introduced for FinFETs. Moreover, some studies on the fabrication of FinFETs using different materials have been discussed. Despite their potential, challenges like corner effects, quantum effects, width quantization, layout dependencies, and parasitics have been acknowledged. In the post-planar CMOS landscape, FinFETs show potential for scalability in nanoscale CMOS, which leads to novel structures for them. Finally, recent developments in FinFET-based sensors are discussed. In a general view, this comprehensive review delves into the intricacies of FinFET fabrication, exploring historical development, classifications, and cutting-edge ideas for the used materials and FinFET application, i.e., sensing. Full article

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS₂ layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS₂, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT’s advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. Full article

The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO₂) with a stacked gate oxide of 0.5 nm of SiO₂ with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si₃N₄, Al₂O₃, ZrO_2, and HfO₂. It was found that the use of strained silicon and replacing only the SiO₂ device with the stacked SiO₂ and HfO₂ device was more beneficial to obtain an optimized device with the least leakage and improved drive currents. Full article

A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of 1.77 V. Compared with conventional SCR and diode string, the proposed SCR-D has an additional conduction path constituting by two additional inherent diodes, which results in a 1.8-to-2.2-times current surge capability as compared with the simple diode string and conventional SCR with the same size. The results show that the proposed device meets the 7 nm FinFET process ESD design window and has already been applied in actual circuits. Full article

Insulated-gate GaN-based transistors can fulfill the emerging demands for the future generation of highly efficient electronics for high-frequency, high-power and high-temperature applications. However, in contrast to Si-based devices, the introduction of an insulator on (Al)GaN is complicated by the absence of a high-quality native oxide for GaN. Trap states located at the insulator/(Al)GaN interface and within the dielectric can strongly affect the device performance. In particular, although AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) provide superior properties in terms of gate leakage currents compared to Schottky-gate HEMTs, the presence of an additional dielectric can induce threshold voltage instabilities. Similarly, the presence of trap states can be detrimental for the operational stability and reliability of other architectures of GaN devices employing a dielectric layer, such as hybrid MIS-FETs, trench MIS-FETs and vertical FinFETs. In this regard, the minimization of trap states is of critical importance to the advent of different insulated-gate GaN-based devices. Among the various dielectrics, aluminum oxide (Al₂O₃) is very attractive as a gate dielectric due to its large bandgap and band offsets to (Al)GaN, relatively high dielectric constant, high breakdown electric field as well as thermal and chemical stability against (Al)GaN. Additionally, although significant amounts of trap states are still present in the bulk Al₂O₃ and at the Al₂O₃/(Al)GaN interface, the current technological progress in the atomic layer deposition (ALD) process has already enabled the deposition of promising high-quality, uniform and conformal Al₂O₃ films to gate structures in GaN transistors. In this context, this paper first reviews the current status of gate dielectric technology using Al₂O₃ for GaN-based devices, focusing on the recent progress in engineering high-quality ALD-Al₂O₃/(Al)GaN interfaces and on the performance of Al₂O₃-gated GaN-based MIS-HEMTs for power switching applications. Afterwards, novel emerging concepts using the Al₂O₃-based gate dielectric technology are introduced. Finally, the recent status of nitride-based materials emerging as other gate dielectrics is briefly reviewed. Full article

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (I_off). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La₂O₃ as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (V_th) of −0.289 V ± 12.7% and I_off of less than 10⁻⁷ A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO₂ formation at the Si interface and rapid annealing processing are required to achieve La₂O₃ thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on V_th, I_on and I_off were investigated. The improved voltage scaling resulting from the lower V_th value is associated with the increased I_off due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process. Full article

IR-drop is a fundamental constraint by almost all integrated circuits (ICs) physical designs, and many iterations of timing engineer change order (ECO), IR-drop ECO, or other ECO are needed before design signoff. However, IR-drop analysis usually takes a long time and wastes so many resources. In this work, we develop a fast dynamic IR-drop predictor based on a machine learning technique, XGBoost, and the prediction method can be applied to vector-based and vectorless IR-drop analysis simultaneously. Correlation coefficient is often used to characterize the symmetry of prediction data and golden data, and our experiments show that the prediction correlation coefficient is more than 0.96 and the average error is no more than 1.3 mV for two industry designs, which are of 2.4 million and 3.7 million instances, respectively, and that the analysis is speeded up over 4.3 times compared with the IR-drop analysis by commercial tool, Redhawk. Full article

A 16-nm-L_g p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias. Full article

This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio ($7.73\times {10}^7$) and the best SS value were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased; therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance. Full article

The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25–125 °C). A similar temperature dependence of threshold voltage (V_TH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (μ_eff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak N_inv (= 5 × 10¹² cm²/V∙s), both GAA NW-FET and FinFET are mainly limited by phonon scattering in μ_eff. On the other hand, at strong N_inv (= 1.5 × 10¹³ cm²/V∙s), GAA NW-FET shows 10 times higher dμ_eff/dT and 1.6 times smaller mobility degradation coefficient (α) than FinFET. GAA NW-FET is less limited by surface roughness scattering, but FinFET is relatively more limited by surface roughness scattering in carrier transport. Full article

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (V_t) tuning of the metal gate in contact with HfO₂/SiO₂/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning. Full article

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated. Full article