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Device Modeling for TCAD and Circuit Simulation

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A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (1 July 2023) | Viewed by 38022

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Prof. Dr. Yun Seop Yu

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Guest Editor

Department of Electrical, Electronic and Control Engineering Hankyong National University, Anseong 17579, Republic of Korea
Interests: compact modeling for circuit simulation; device modeling for TCAD simulation; device characterization; steep-switching device; GAA NW-FET; 2D material transistor; neuromorphic device
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Special Issue Information

Dear Colleagues,

Because CMOS technology has been scaling according to Moore’s law, it is approaching its basic physical limits. In order to replace and expand the current CMOS devices and circuits, various types of new device, such as steep-switching transistors, 2D material transistors, neuromorphic devices, and so on, have been reported. It is necessary to analyze the characteristics of newly proposed devices, and their accurate and physics-based compact models are also needed to efficiently design and simulate the circuits comprising them or CMOSs.

This Special Issue solicits original research papers and review articles with numerical or analytical models of various novel devices based on theoretical approaches for technology computer-aided design (TCAD) and circuit simulations.

Potential topics include, but are not limited to, the following:

Compact modeling for circuit simulation;
Device modeling for TCAD simulation;
Steep-switching device modeling: tunnel field-effect transistor (TFET), negative-capacitance field-effect transistor (NCFET), feedback field-effect transistor (FBFET), and so on;
FinFET modeling;
Gate-all-around (GAA) nanowire (NW) FET modeling;
Ultra-thin silicon-on-insulator (SOI) modeling;
Two-dimensional material (e.g., MoS₂, WSe₂) transistors modeling;
Graphene FET modeling;
Nanowire and nanotube FET modeling;
Neuromorphic device modeling;
Volatile memory device modeling;
Non-volatile memory device modeling;
Progress in modeling methodology and approaches.

Prof. Yun Seop Yu
Guest Editor

Manuscript Submission Information

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Keywords

compact modeling
device modeling
steep-switching device modeling: tunnel field-effect transistor (TFET), negative-capacitance field-effect transistor (NCFET), feedback field-effect transistor (FBFET) and so on
FinFET modeling
gate-all-around (GAA) nanowire (NW) FET modeling
ultra-thin fully-depleted silicon-on-insulator (UT-SOI) modeling
2D material transistor modeling
graphene FET modeling
nanowire and nanotube FET modeling
neuromorphic device modeling
monolithic 3D basic cell modeling
volatile memory device modeling
non-volatile memory device modeling
progress in modeling methodology and approaches

Published Papers (12 papers)

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Research

8 pages, 3345 KiB

Open AccessCommunication

Analysis of Ruggedness of 4H-SiC Power MOSFETs with Various Doping Parameters

by Min-Seok Jang, Jee-Hun Jeong and Ho-Jun Lee

Appl. Sci. 2023, 13(1), 427; https://doi.org/10.3390/app13010427 - 29 Dec 2022

Cited by 2 | Viewed by 1382

Abstract

This work investigates the effect of the doping concentration of SiC power metal-oxide–semiconductor field-effect transistors (MOSFETs) under an unclamped inductive switching (UIS) condition. Switching circuits such as inverters and motor-drive circuits often face unexpected operating conditions; therefore, a UIS test is performed to assess the avalanche ruggedness of the device, and design parameters such as the doping concentration should be considered to improve the UIS characteristics. Technology computer-aided design circuit simulation results, such as the current flows during failure and electrical changes, were obtained by changing the doping concentration of each region in the SiC power MOSFET. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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19 pages, 23653 KiB

Open AccessArticle

A Computationally Efficient Model for FDSOI MOSFETs and Its Application for Delay Variability Analysis

by Zhiyi Mao, Yuping Wu, Lan Chen and Xuelian Zhang

Appl. Sci. 2022, 12(10), 5167; https://doi.org/10.3390/app12105167 - 20 May 2022

Cited by 1 | Viewed by 1363

Abstract

This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied to avoid the numerical iterations required in the evaluation of surface potential, which directly improves the computational efficiency. The accuracy of the explicit surface potential approximation is 190.3 nV, which allows for fast convergence. Surface potential and current calculations achieve 1.8× and 1.4× acceleration compared with BSIM-IMG, respectively. To establish the relationship between delay and underlying process parameters, we introduce the effective current and propose a process variation-aware delay prediction model. Higher-order derivatives are calculated to compensate the nonlinearity of delay variations with respect to process parameters. Experiments show a significant improvement in the prediction accuracy with higher-order derivatives, which are proved to be able to handle nonlinearity under process variations. The front gate work function contributes the most to the nonlinearity of the delay variation and the accuracy of the third-order prediction is 4.07%. Under the variation in the channel length and width, front and back gate oxide thickness and body thickness, delay variations have similar characteristics and the second-order prediction is found to be sufficient to model the nonlinearity with a maximum relative error of 1.22%. The delay prediction model only requires a single-point HSPICE DC or transient simulation and is universal for different voltages and different cells. Compared with the Monte Carlo (MC) simulation, the accuracy of the first-order prediction in the above-threshold region (0.8 V) is 0.94%. In the sub-threshold region (0.3 V), a prediction accuracy of 2.01% can be obtained while achieving a 21× reduction in computational time. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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12 pages, 7719 KiB

Open AccessFeature PaperArticle

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

by Tae Jun Ahn, Sung Kyu Lim and Yun Seop Yu

Appl. Sci. 2021, 11(24), 12151; https://doi.org/10.3390/app112412151 - 20 Dec 2021

Cited by 2 | Viewed by 1864

Abstract

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness T_ILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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10 pages, 2349 KiB

Open AccessArticle

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

by Je-Hyuk Kim, Youngjin Seo, Jun Tae Jang, Shinyoung Park, Dongyeon Kang, Jaewon Park, Moonsup Han, Changwook Kim, Dong-Wook Park and Dae Hwan Kim

Appl. Sci. 2021, 11(11), 4838; https://doi.org/10.3390/app11114838 - 25 May 2021

Cited by 7 | Viewed by 2597

Abstract

Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (V_T) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al₂O₃ gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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9 pages, 2571 KiB

Open AccessFeature PaperArticle

Analysis of Circuit Simulation Considering Total Ionizing Dose Effects on FinFET and Nanowire FET

by Hyeonjae Won and Myounggon Kang

Appl. Sci. 2021, 11(3), 894; https://doi.org/10.3390/app11030894 - 20 Jan 2021

Cited by 5 | Viewed by 2611

Abstract

In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to the structural aspect through comparison of the two devices. Similar to n-type devices, p-type NW-FETs are less affected than FinFETs by the TID effect. For the inverter TID circuit simulation, both n- and p-types of FinFET and NW-FET were analyzed regarding the TID effect. The inverter operation considering the TID effect was verified using the Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. In addition, an inverter circuit composed of the NW-FET exhibited a smaller change by the TID than that of an inverter circuit composed of the FinFET. Therefore, the gate controllability of the gate-all-around (GAA) device had an excellent tolerance to not only short-channel effects (SCE) but also TID effects. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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11 pages, 2136 KiB

Open AccessArticle

Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET

by Tae Jun Ahn and Yun Seop Yu

Appl. Sci. 2021, 11(1), 277; https://doi.org/10.3390/app11010277 - 30 Dec 2020

Cited by 1 | Viewed by 2160

Abstract

In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (T_ILD) and gate channel length (L_g) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as T_ILD decreases and they increase as L_g increases, and thus there is a strong coupling in M3INV at the range of T_ILD ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same T_ILD and L_g. The switching threshold voltage (V_m) and noise margins (NMs) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the V_m variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of V_m, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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9 pages, 4895 KiB

Open AccessArticle

Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

by Min Woo Kang and Woo Young Choi

Appl. Sci. 2020, 10(24), 8880; https://doi.org/10.3390/app10248880 - 11 Dec 2020

Viewed by 2103

Abstract

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (I_on) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (T_ins). Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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9 pages, 1035 KiB

Open AccessArticle

Lateral Capacitance–Voltage Method of NanoMOSFET for Detecting the Hot Carrier Injection

by Atabek E. Atamuratov, Ahmed Yusupov, Zukhra A. Atamuratova, Jean Chamberlain Chedjou and Kyandoghere Kyamakya

Appl. Sci. 2020, 10(21), 7935; https://doi.org/10.3390/app10217935 - 09 Nov 2020

Cited by 4 | Viewed by 1892

Abstract

In this paper, the dependence of the capacitance of lateral drain–substrate and source–substrate junctions on the linear size of the oxide trapped charge in MOSFET is simulated. It is shown that, at some range of linear sizes of the trapped charge, the capacitance of lateral junctions linearly depends on the linear size of the trapped charge. The dependence of the difference between drain–substrate and source–substrate capacitances on the linear size of trapped charges is also simulated. The revealed dependence can be used in measurements to estimate the linear size of oxide trapped charges induced by hot carrier injection, which can occur during MOSFET operation at defined conditions. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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11 pages, 2063 KiB

Open AccessArticle

Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET

by Atabek E. Atamuratov, Mahkam M. Khalilloev, Ahmed Yusupov, A. J. García-Loureiro, Jean Chamberlain Chedjou and Kyamakya Kyandoghere

Appl. Sci. 2020, 10(15), 5327; https://doi.org/10.3390/app10155327 - 01 Aug 2020

Cited by 1 | Viewed by 2295

Abstract

In this paper, different physical models of single trap defects are considered, which are localized in the oxide layer or at the oxide–semiconductor interface of field effect transistors. The influence of these defects with different sizes and shapes on the amplitude of the random telegraph noise (RTN) in Junctionless Fin Field Effect Transistor (FinFET) is modelled and simulated. The RTN amplitude dependence on the number of single charges trapped in a single defect is modelled and simulated too. It is found out that the RTN amplitude in the Junctionless FinFET does not depend on the shape, nor on the size of the single defect area. However, the RTN amplitude in the subthreshold region does considerably depend on the number of single charges trapped in the defect. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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12 pages, 2440 KiB

Open AccessArticle

Compact Trap-Assisted-Tunneling Model for Line Tunneling Field-Effect-Transistor Devices

by Faraz Najam and Yun Seop Yu

Appl. Sci. 2020, 10(13), 4475; https://doi.org/10.3390/app10134475 - 28 Jun 2020

Cited by 9 | Viewed by 4656

Abstract

Trap-assisted-tunneling (TAT) is a well-documented source of severe subthreshold degradation in tunneling field-effect-transistors (TFET). However, the literature lacks in numerical or compact TAT models applied to TFET devices. This work presents a compact formulation of the Schenk TAT model that is used to fit experimental drain-source current (I_ds) versus gate-source voltage (V_gs) data of an L-shaped and line tunneling type TFET. The Schenk model incorporates material-dependent fundamental physical constants that play an important role in influencing the TAT generation (G_TAT) including the lattice relaxation energy, Huang–Rhys factor, and the electro-optical frequency. This makes fitting any experimental data using the Schenk model physically relevant. The compact formulation of the Schenk TAT model involved solving the potential profile in the TFET and using that potential profile to calculate G_TAT using the standard Schenk model. The G_TAT was then approximated by the Gaussian distribution function for compact implementation. The model was compared against technology computer-aided design (TCAD) results and was found in reasonable agreement. The model was also used to fit an experimental device’s I_ds–V_gs characteristics. The results, while not exactly fitting the experimental data, follow the general experimental I_ds–V_gs trend reasonably well; the subthreshold slope was loosely similar to the experimental device. Additionally, the ON-current, especially to make a high drain-source bias model accurate, can be further improved by including effects such as electrostatic degradation and series resistance. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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19 pages, 5264 KiB

Open AccessArticle

Understanding of Feedback Field-Effect Transistor and Its Applications

by Changhoon Lee, Juho Sung and Changhwan Shin

Appl. Sci. 2020, 10(9), 3070; https://doi.org/10.3390/app10093070 - 28 Apr 2020

Cited by 17 | Viewed by 5865

Abstract

Feedback field-effect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent subthreshold swing (~0 mV/decade at 300 K), a high on-/off current ratio (~10¹⁰), and a clear saturation region. The power consumption of both the turn-on state and turn-off state is significantly low until operation commences. In addition, the hysteresis caused by the carriers accumulated in the potential wall allows the FBFET to act as a memory device. Moreover, the power consumption of neuromorphic devices can be suppressed by ~100 times with the use of FBFETs. In this work, we analyze the device structure and operating principle of the FBFET and summarize its applications. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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7 pages, 2523 KiB

Open AccessArticle

Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET

by Soohyun Kim, Jungchun Kim, Doyoung Jang, Romain Ritzenthaler, Bertrand Parvais, Jerome Mitard, Hans Mertens, Thomas Chiarella, Naoto Horiguchi and Jae Woo Lee

Appl. Sci. 2020, 10(8), 2979; https://doi.org/10.3390/app10082979 - 24 Apr 2020

Cited by 16 | Viewed by 6579

Abstract

The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25–125 °C). A similar temperature dependence of threshold voltage (V_TH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (μ_eff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak N_inv (= 5 × 10¹² cm²/V∙s), both GAA NW-FET and FinFET are mainly limited by phonon scattering in μ_eff. On the other hand, at strong N_inv (= 1.5 × 10¹³ cm²/V∙s), GAA NW-FET shows 10 times higher dμ_eff/dT and 1.6 times smaller mobility degradation coefficient (α) than FinFET. GAA NW-FET is less limited by surface roughness scattering, but FinFET is relatively more limited by surface roughness scattering in carrier transport. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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