Special Issue "Abridging the CMOS Technology"

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: 31 August 2022 | Viewed by 3316

Special Issue Editor

Prof. Dr. Hei Wong
E-Mail Website
Guest Editor
Department of Electrical Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong, China
Interests: CMOS integrated circuits; high-k dielectric thin films; nanoelectronics; semiconductor device models; MOSFET; approximation theory; ballistic transport; circuit optimisation; electrostatics; elemental semiconductors; field effect transistors; nanowires; numerical analysis; sensitivity; silicon; surface potential; surface roughness; silicon compounds; dielectric thin films; tunnelling; interface states; X-ray photoelectron spectra; electron traps; hafnium compounds, SPICE

Special Issue Information

Dear Colleagues,

From either a physics device, fabrication technology, or process economics point of view, the downsizing of silicon-based CMOS devices will shortly be over. Although new revolutionized materials and new technologies for further integrated electronics advancement are on the horizon already, considering the development of nanoscale-sized devices, as well as giga-scale in integration density, complexity in fabrication technology, and the widespread application of the present CMOS technology, which is a cumulative outcome resulted from the relentless advancement and innovation of over seven decades, the emerging new materials and new devices are unlikely to replace CMOS technology in the short term. A possible scenario is that the existing CMOS technology will still be, at baseline, the mainstream integration technology for decades to come; alongside this, new material discovery and new technology innovation, on the one hand, could serve as technological options for overcoming some of the constraints in CMOS devices and fabrication technology, and, on the other hand, could enrich and enhance the CMOS technology in certain aspects.    

This Special Issue, titled “Abridging the CMOS Technology, serves as a forum for multi-disciplinary experts to address various aspects of recent advancements in nanomaterials and nanotechnology that could be abridged to further CMOS technology advancement at the end of More Moore. The format of articles includes full papers, communications, and reviews. Topics include but are not limited to:

  • CMOS device characteristic enhancement with nanomaterials;
  • Nanotechnology for CMOS fabrication;
  • Silicon and 2D material integration;
  • Silicon/2D material interaction and characterization;
  • Enriching CMOS technology with 2D material-based devices, sensors and transducers;
  • Nanophotonics–CMOS integration;
  • Interconnects with nanomaterials;
  • Nanoscale modeling and computation;
  • CMOS thermal management with nanomaterials.

Prof. Dr. Hei Wong
Guest Editor

Manuscript Submission Information

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Published Papers (5 papers)

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Research

Article
Silicon-Controlled Rectifier Embedded Diode for 7 nm FinFET Process Electrostatic Discharge Protection
Nanomaterials 2022, 12(10), 1743; https://doi.org/10.3390/nano12101743 - 19 May 2022
Viewed by 153
Abstract
A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of 1.77 V. Compared with conventional SCR [...] Read more.
A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of 1.77 V. Compared with conventional SCR and diode string, the proposed SCR-D has an additional conduction path constituting by two additional inherent diodes, which results in a 1.8-to-2.2-times current surge capability as compared with the simple diode string and conventional SCR with the same size. The results show that the proposed device meets the 7 nm FinFET process ESD design window and has already been applied in actual circuits. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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Article
On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node
Nanomaterials 2022, 12(10), 1739; https://doi.org/10.3390/nano12101739 - 19 May 2022
Viewed by 171
Abstract
This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by [...] Read more.
This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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Article
Robust Simulations of Nanoscale Phase Change Memory: Dynamics and Retention
Nanomaterials 2021, 11(11), 2945; https://doi.org/10.3390/nano11112945 - 03 Nov 2021
Viewed by 591
Abstract
A robust simulation framework was developed for nanoscale phase change memory (PCM) cells. Starting from the reaction rate theory, the dynamic nucleation was simulated to capture the evolution of the cluster population. To accommodate the non-uniform critical sizes of nuclei due to the [...] Read more.
A robust simulation framework was developed for nanoscale phase change memory (PCM) cells. Starting from the reaction rate theory, the dynamic nucleation was simulated to capture the evolution of the cluster population. To accommodate the non-uniform critical sizes of nuclei due to the non-isothermal conditions during PCM cell programming, an improved crystallization model was proposed that goes beyond the classical nucleation and growth model. With the above, the incubation period in which the cluster distributions reached their equilibrium was captured beyond the capability of simulations with a steady-state nucleation rate. The implications of the developed simulation method are discussed regarding PCM fast SET programming and retention. This work provides the possibility for further improvement of PCM and integration with CMOS technology. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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Article
Numerical Investigation of Phononic Crystal Based Film Bulk Acoustic Wave Resonators
Nanomaterials 2021, 11(10), 2547; https://doi.org/10.3390/nano11102547 - 28 Sep 2021
Viewed by 768
Abstract
Film bulk acoustic resonator (FBAR)-based filters have attracted great attention because they can be used to build high-performance RF filters with low cost and small device size. Generally, FBARs employ the air cavity and Bragg mirror to confine the acoustic energy within the [...] Read more.
Film bulk acoustic resonator (FBAR)-based filters have attracted great attention because they can be used to build high-performance RF filters with low cost and small device size. Generally, FBARs employ the air cavity and Bragg mirror to confine the acoustic energy within the piezoelectric layer, so as to achieve high quality factors and low insertion loss. Here, two-dimensional (2D) phononic crystals (PhCs) are proposed to be the acoustic energy reflection layer for an FBAR (PhC-FBAR). Four kinds of PhC structures are investigated, and their bandgap diagrams and acoustic wave reflection coefficients are analyzed using the finite element method (FEM). Then, the PhCs are used as the acoustic wave reflectors at the bottom of the piezoelectric stack, with high reflectivity for elastic waves in the specific frequency range. The results show that the specific PhC possesses a wide bandgap, which enables the PhC-FBAR to work at a broad frequency range. Furthermore, the impedance spectra of PhC-FBARs are very smooth with few spurious modes, and the quality factors are close to those of traditional FBARs with air cavities, showing the application potential of the PhC-FBAR filters with wide bandwidth and high power capability. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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Article
Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices
Nanomaterials 2021, 11(8), 2118; https://doi.org/10.3390/nano11082118 - 20 Aug 2021
Viewed by 1059
Abstract
As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more [...] Read more.
As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more significant surface roughness-induced local electric field fluctuation and thus leads to a large device characteristic variability. This paper presents a comprehensive study and detailed discussion on the gate leakage variabilities of nanoscale devices corresponding to the surface roughness effects. By taking the W/La2O3/Si structure as an example, capacitance and leakage current variabilities were found to increase pronouncedly for samples even with a very low-temperature thermal annealing at 300 °C. These results can be explained consistently with the increase in surface roughness as a result of local oxidation at the La2O3/Si interface and the interface reactions at the W/La2O3 interface. The surface roughness effects are expected to be severe in future generations’ devices with even thinner gate dielectric film and smaller size of the devices. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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