Self-Heating Effect Coupled Compact Model to Predict Hot Carrier Injection Degradation in Nanoscale Bulk FinFETs Under Different Conditions

Abstract

The HCI effect has been the focus of research as a common reliability consideration under advanced nodes in semiconductors. In this paper, a new compact model that takes into account the self-heating effect, width dependence, and substrate voltage dependence is proposed in the framework of a self-saturated power–law model containing oxide defects. The compact model employs different parameters in different carrier energy regions to improve the accuracy of the model. The predictions of the model fit well with experimental data extracted from the literature and the TCAD data, proving the validity of the model. Meanwhile, the model is used in this paper to predict and analyze the HCI’s degradation as well as lifetime under different conditions.

1. Introduction

Tri-gate FinFET structures have been adopted in industry since the 22 nm technology node, due to their three-dimensional design that improves short-channel effect control and reduces leakage currents. However, this also leads to more pronounced hot carrier injection (HCI) effects in short-channel devices [1]. HCI-induced degradation causes threshold voltage drift and reduced mobility, significantly impacting device performance and life. It also contributes to delayed degradation in circuits, affecting their operational speed. Increasingly, research and circuit design are incorporating the effects of the aging of HCI early in the design phase and physical implementation, requiring the support of relevant aging models [2].

In 1985, Hu et al. proposed the lucky electron model (LEM), which includes the Si-H bond breaking process. According to this model, electrons in the channel gain sufficient energy from the maximum electric field to overcome the interfacial potential barrier, causing the Si-H bond to dissociate. Consequently, the maximum electric field in the channel becomes a key parameter in this model [3]. In addition to modeling chemical bond dissociation, many researchers have focused on the carrier energies responsible for bond dissociation. In 2002, McMahon proposed a model for generating interfacial traps through multiple electron vibrations. This model links the lifetime of the device to the magnitude of the source leakage current, suggesting that a larger leakage current increases the probability of multiple electron vibrations, which, in turn, accelerates bond dissociation and device degradation [4]. Subsequently, instead of an electric-field-driven mechanism, a model based on an energy-driven mechanism was proposed. This highlights the significant impact of electron–electron scattering on the energy distribution function (EDF) [5]. Through continuous refinement, single vibrational excitation (SVE), electron–electron scattering (EES), and multiple vibrational excitation (MVE) have been integrated, highlighting the significant role of carriers in a low-energy state in the degradation caused by cold channel carriers (CHC). It also effectively explains the transition of the worst stress condition for hot carriers injected at low-tech nodes, from $V_G={\displaystyle \frac{V_D}{2}}$ to $V_G=V_D$ [6]. The model has been widely used in HCI studies, showing strong predictive performance for reliability data in LDMOSFETs, devices of high and low thresholds, and devices in various nodes of technology [7,8]. Also, it is used in Sentaurus technology CAD (TCAD) and the reliability simulation tool MOSRA, showing a good fit to the experimental data [9].

At low technology nodes, the HCI effect is inadequately described by previous models in two main ways. First, the structure of FinFETs introduces additional reliability and process challenges, including the following:

(a)

The three-dimensional structure of FinFETs leads to varying crystal orientations in the silicon substrate, creating multiple interfaces between the silicon and oxide. This increases the number of sidewall traps on the fins, thereby enhancing HCI degradation [10].

(b)

The use of high-K and metal gates (HKMG) alters the dominant HCI degradation and trap generation mechanisms.

(c)

The heat generated by current flow through the channel is difficult to dissipate, resulting in self-heating. In FinFETs, the complex fin heat dissipation structure causes a more obvious increase in channel temperature, making self-heating a significant coupling effect that must be considered [11].

On the other hand, most of the aforementioned models have limitations. The aging function is typically expressed as $\mathrm{Age}\propto {\left({\displaystyle \frac{I_{\mathrm{sub}}}{I_{\mathrm{ds}}}}\right)}^m$ in both electric-field-driven models and energy-driven models, where the aging lifetime under HCI is written as $\tau \propto {\left(I_{\mathrm{sub}}^m\right)}^{-l}$ [12]. This makes the substrate current an important measure of HCI severity, while it can no longer accurately reflect HCI degradation due to other factors’ influences, such as the gate leakage current and junction current at nanoscale nodes [13]. As the single power–law relationship cannot explain the saturation of HCI degradation, which has been reported, a self-saturation power–law framework is proposed. Sharma et al. developed a compact model based on this self-saturating power–law framework in their work [14]. Regarding the mechanism of trap generation, the two-stage effect observed in HCI degradation in FinFETs indicates that different types of traps are generated, making it essential to understand their time/voltage dependence [15]. In addition, it has been reported that substrate voltage may be helpful in improving HCI performance [6,16], and the effect of fin width as well as the number of fins on HCI has also been investigated [14,16]. It is essential to include these factors in modeling considerations.

This article develops a compact model of HCI degradation based on reaction–diffusion (R-D) theory to account for coupled self-heating effects (SHE) across different $V_{\mathrm{gs}}/V_{\mathrm{ds}}$ spans. It integrates the impact on device structural parameters, temperature, and substrate potential, on the basis of the results in [17], and is validated for n-type Bulk FinFETs at the 14 nm node. The main sections of the article are as follows: In the first section, the background of HCI modeling and the previous models are introduced. The second section describes the physical mechanisms, including the reaction–diffusion theory, multi-vibrational excitation theory, and theory of bond dissociation. On basis of the physical theory, we establish a new compact model. The third section extracts relevant aging parameters and validates the results. We also compare the prediction of the compact model with the TCAD simulation results, and we analyze the life prediction made by the compact model and traditional self-saturating model.

2. Compact Model and Physics

2.1. Reaction–Diffusion Framework

Similar to trap generation caused by NBTI, the mechanism of interfacial trap generation due to hot carrier (HC) stress can also be explained by reaction–diffusion (R-D) theory. This theory suggests that hot carriers acquire sufficient kinetic energy from the high transverse electric field, leading to the breaking of Si-H bonds and the formation of dangling bonds. If the energy is high enough, the carriers may also be trapped in the oxide layer, resulting in oxide defects. The reaction process can be represented as Figure 1 [18], while $k_f$ is the forward reaction rate (the rate of bond dissociation), and $k_r$ is the reverse rate.

The R-D model consists of two stages: (1) the trap generation process, which involves the formation of interfacial traps at the gate oxide layer interface under external electrical stress, and (2) the diffusion process, which describes the movement of the reaction products from the interface toward the gate electrode due to the density gradient. These two processes are represented by the following equations:

$${\displaystyle \frac{d{N}_{\mathrm{IT}}}{dt}}=k_F(N_0-N_{\mathrm{IT}})-k_R{N}_H{N}_{\mathrm{IT}}$$

(1)

$${\displaystyle \frac{d{N}_H}{dt}}=D_H{\nabla }^2{N}_H$$

(2)

$N_0$ is the maximum trap concentration. $N_{IT}$ is the interfacial trap concentration, and $N_H$ is the hydrogen atom concentration. $D_H$ is the diffusion coefficient, which indicates the rate of hydrogen diffusion and varies across different dielectric layers. The H diffusion process is shown in Figure 2.

To solve Equations (1) and (2), there are two assumptions: (1) The trap generation rate is assumed to be negligible at the beginning of device stress, so ${\displaystyle \frac{d{N}_{\mathrm{IT}}}{dt}}=0$; (2) the dissociation and diffusion of each hydrogen atom are assumed to create a trap vacancy at the interface. The trap concentration can be derived from the hydrogen atom concentration, $N_H$, within the oxide layer across the entire diffusion region. The integral of $N_H$ is then computed to obtain the desired result.

$$N_{\mathrm{IT}}\left(t\right)={\displaystyle \frac{1}{WL}}\int N_H(r,t)d^{3}r$$

(3)

For the solution of (2), it is usually in the form of a Gaussian solution, that is,

$$N_H(t,r)={\displaystyle \frac{N_{H0}}{{\left(4\pi D_{H}t\right)}^{3/2}}}exp\left(-{\displaystyle \frac{{\left|r\right|}^2}{4D_{H}t}}\right)$$

(4)

Bringing (4) into the reaction–diffusion equation (Equation (1)) gives

$${\displaystyle \frac{d{N}_{\mathrm{IT}}}{dt}}=k_F(N_0-N_{\mathrm{IT}})-k_R{N}_{\mathrm{IT}}{\displaystyle \frac{N_{H0}}{{\left(4\pi D_{H}t\right)}^{3/2}}}exp\left(-{\displaystyle \frac{{\left|r\right|}^2}{4D_{H}t}}\right)$$

(5)

Substituting $d{N}_{IT}/dt=0$ in the assumption into (5), and also assuming that the process of Si-H bond dissociation occurs only where the Si-SiO₂ interface is, i.e., the vector r = 0, the final form of the solution obtained through (3) and (5) is

$$N_{\mathrm{IT}}\approx N_0\left[1-exp\left(-AR{t}^m\right)\right]$$

(6)

AR represents the aging rate, which indicates how fast the device ages under hot carrier stress. The threshold voltage degradation caused by HCI is proportional to the trap concentration, written as

$$\Delta V_{\mathrm{TH}}={\displaystyle \frac{q}{C_{\mathrm{ox}}}}{N}_{\mathrm{IT}}$$

(7)

So, electron mobility degradation under HC stress is written as (8). ${\mu }_{eff}$ is the effective mobility. The empirical parameters $\alpha$ and m come from [19].

$$\mu ={\displaystyle \frac{{\mu }_{\mathrm{eff}}}{{\left(1+\alpha N_{\mathrm{IT}}\right)}^m}}$$

(8)

2.2. Discussion on Aging Rate (AR)

The aging rate (AR) is inversely proportional to the device’s lifetime, i.e., $AR\propto {\displaystyle \frac{1}{\tau }}$, and $\tau \propto k_{f/r}$. The forward reaction rate as well as the reverse reaction rate are related to the maximum electric field in the channel, so the aging rate can be written as $AR\propto exp(-{\varphi }_{\mathrm{it}}/q\lambda E_m)$. The maximum lateral electric field in the channel is given by $E_m=(V_{ds}-\eta V_{\mathrm{dsat}})/l$, where $V_{dsat}$ is the saturation voltage, calculated as $V_{\mathrm{dsat}}=V_{gs}-V_{\mathrm{TH}0}$; l is the characteristic length of the three-gate silicon FinFET device; and $\eta$ is a dimensionless fitting parameter (ranging from 0 to 1) that models the short-channel effect [13].

In MVE theory, channel carriers are categorized into three modes based on their energy. Under a high horizontal electric field, carriers gain energy from the field. In this mode, Si-H bond dissociation at the interface is solely driven by single-carrier processes. When the horizontal electric field is lower, the dissociation of the bond by multiple carriers raises the vibrational state of the bond, eventually providing enough energy (denoted as $E_B$) for dissociation, which is shown in Figure 3. When the energy of the carriers does not reach the MVE region, the degradation is dominated by electron–electron scattering. Corresponding to the stress voltage, the low-energy region and the high-energy region of the carriers are in the following two voltage ranges: $V_{ds}<V_{gs}$ and $V_{gs}\le V_{ds}$ [6]. Thus, the lifetime corresponding to the above three modes is inversely proportional to the current between the drain and source, so the aging rate can be written as $AR\propto {\left(I_{\mathrm{ds}}\right)}^k$. Replacing $I_{ds}$ with voltage yields, the AR can be written as

$$AR=A{\left(V_{\mathrm{gs}}-V_T\right)}^{n_1}exp\left(-{\displaystyle \frac{H_1}{V_{ds}-\eta V_{\mathrm{dsat}}}}\right)exp\left(-{\displaystyle \frac{E_{a}k}{k_{B}T}}\right)$$

(9)

$$H_1={\displaystyle \frac{{\varphi }_{\mathrm{it}}}{q\lambda l}}$$

(10)

2.3. Discussion on Oxide Traps and Substrate Voltage

In conventional theory, HCI degradation is usually considered to be caused by one type of interfacial trap, adhering to a simple single-stage power–law model or a self-saturation power–law model. However, a two-stage phenomenon under certain specific voltage conditions in HKMG devices has been found. One possible explanation is the existence of at least two different traps that contribute to HCI degradation, and they may each play a dominant role at different times of degradation. In the literature [6,20], it can be observed that the subthreshold swing ratio (SS) decreases with time both in single-stage power–law phenomena and in two-stage power–law phenomena, implying that the production of interfacial traps saturates with time, accompanied by at least one type of oxide trap. Figure 4 demonstrates the distribution of the two traps in the oxide layer.

The model of the generation of oxide traps can be described as

$$N_{\mathrm{ox}}=A{R}_{\mathrm{ox}}log(1+ct)$$

(11)

The aging rate related to oxide traps $A{R}_{ox}$ follows the same form as that of interface traps, but is strongly correlated with the gate impulse current and, therefore, is affected by the bias of the substrate. When reverse back-bias is applied to SOTB devices, energetic hot electrons generated by high drain bias are injected into the gate oxide layer under the enhanced vertical electric field $E_y$, creating capture sites at the drain edge. As a result, electron capture is considered the dominant mechanism in reverse back-biasing [21]. The enhancement of HCI degradation due to substrate bias is related to impact ionization, and the ionization current can be written as $I_G=I_{G_{o,ii}}exp\left({\alpha }_i{V}_b\right)$. So, the aging rate is

$$A{R}_{\mathrm{ox}}=B{\left(V_{\mathrm{gs}}-V_T\right)}^{n_2}exp\left(-{\displaystyle \frac{H_2}{V_{ds}-\eta V_{\mathrm{dsat}}}}\right)exp\left(-{\displaystyle \frac{E_{a}k}{k_{B}T}}\right)exp\left({\alpha }_i{V}_b\right)$$

(12)

2.4. Discussion on Fin Width

The special 3D structure of FinFETs results in a different spatial distribution of traps, thus causing degradation relying on structural parameters, especially the device width. The diffusion of hydrogen produced during bond dissociation in the three-dimensional FinFET structure can be effectively modeled, showing a clear relationship between trap distribution and the fin width-to-length ratio. In the modeling process, it is assumed that traps are generated at fixed locations without redistribution over time.

As illustrated in Figure 5, there are several different forms of diffusion of H at the oxide interface. Considering the different diffusion forms, the equations for the corresponding diffusion forms are substituted into Equations (3) and (1) and solved to obtain the distribution equation of the trap as follows [18]:

$$N_{\mathrm{IT}}\left(t\right)\propto {\left[{\displaystyle \frac{{\left(D_{H}t\right)}^{1/2}}{2}}+{\displaystyle \frac{\pi \left(D_{H}t\right)}{6(W_{\mathrm{Fin}}+2H_{\mathrm{Fin}})}}+{\displaystyle \frac{\pi \left(D_{H}t\right)}{12(L_c-\Delta L)}}+{\displaystyle \frac{\pi {\left(D_{H}t\right)}^{3/2}}{24(L_c-\Delta L)(W_{\mathrm{Fin}}+2H_{\mathrm{Fin}})}}\right]}^{1/2}$$

(13)

When the stress voltage $V_{gs}=V_{ds}$ is low, the channel cutoff region length $\Delta L$ approaches zero, and (13) can be simplified. The semi-empirical relationship between AR and fin width is written as $AR\propto N_{\mathrm{IT}}\propto {(1/W_{\mathrm{eff}})}^{a_n}$.

2.5. Coupling Effects of Self-Heating

The lateral confinement of the nanoscale Fin size and phonon scattering result in higher thermal resistance, preventing efficient heat dissipation during operation and leading to HCI deterioration, which is reported to be severe, especially in the DC mode. As the technology node continues to shrink, SHE becomes a severe factor that has a significant impact on HCI, in contrast to other thermal effects, such as thermal noise, that can be neglected. Although HCI and self-heating (SH) are both well established in modeling, their coupling has not been thoroughly studied. The coupled modeling of the self-heating effect and HCI degradation through channel temperature corrections due to self-heating was accomplished in this study, regardless of changes due to other factors.This method has been reported and confirmed [22]. The temperature correction equation takes the same form as in the literature [14] and is shown below:

$$\Delta T_{SH}=\Theta V_g{V}_d$$

(14)

The model directly relates the variation in the average temperature inside the channel to the stress voltage. For the coefficient $\Theta$, it is considered to be extracted from the temperature increase curve obtained from the simulation of the analytical thermal resistance network model.

The analytical model constructs a thermal resistance framework based on heat dissipation patterns and offers accurate predictions of temperature changes, which has been widely used in SHE modeling [23].

According to the analytical model, in DC mode, the temperature rise due to SH is written in the following form:

$$\Delta T_{\mathrm{SH}}(f=0)=R_{\mathrm{th}}\times P_{\mathrm{disp}}$$

(15)

$$P_{\mathrm{disp}}=I_D\times V_D$$

(16)

The method is based on thermal transport and device structure, which defines several different models for modeling the thermal resistance of dissipation based on the analysis of the main heat dissipation paths of the device [24]. The single-fin and multi-fin thermal resistance networks are shown in Figure 6.

Adding the temperature correction for self-heating, the temperature-dependent exponential term is written as $exp\left(-{\displaystyle \frac{E_a}{kT}}\left({\displaystyle \frac{1}{T_0}}-{\displaystyle \frac{1}{\Delta T_{\mathrm{SH}}}}\right)\right)$.

The whole model is given in Figure 7.

3. Results and Discussion

3.1. Model Parameter Fitting

The temperature variation inside the device is simulated using the analytic thermal resistance network model to obtain the relationship between $\Delta T$ and the dissipated power $P_{disp}$. While $P_{disp}\propto V_{ds}\ast I_{ds}$, the drain/source current is modeled by the power–law model $I_{ds}\propto B{(V_{gs}-V_{th})}^n$. The parameters B and n are obtained from the literature [13], and n is approximated as 1. If we divide $P_{disp}/I_{ds}$ by $I_{ds}/V_{gs}$, we can obtain the self-heating parameter $\Theta$. Figure 8a shows the relationship between thermal resistance and the number of fins obtained using the thermal resistance network model. Figure 8b shows the relationship between the temperature change due to self-heating and the dissipated power obtained from the analytical model simulation, and the extracted self-heating coefficients are labeled in the figure. The results can be corroborated with the coefficients from the literature [14], which are about 60 in both cases. The device structure parameters and thermal conductivity parameters used in the analytical modeling are shown in

Table 1. Bulk FinFET structure key parameters.

Fin Width (nm)	Fin Height (nm)	Channel Length (nm)
10	30	20

and

Table 2. Material thermal conductivity key parameters for Bulk FinFETs.

Channel (W/m·K)	Source/Drain (W/m·K)	Gate Oxide SiO2 (W/m·K)
14	62	1.4

, respectively.

For the established compact model, parameter extraction was carried out using data from the literature [17]. In this literature, 16/14 nm bulk FinFETs were used to measure the HCI degradation under different voltage stress levels.

The extraction of the HCI parameters was performed step by step. We first used Equation (17) to extract the parameters mentioned in it. Cross-validation was used to ensure the stability of the parameters, and to avoid the overfitting phenomenon, using four sets of data under different experimental conditions.

$$\Delta V=V_{m,i}\times \left[1-exp\left(-AR·t^n\right)\right]+V_{m,ox}\times log\left(1+c·t\right)$$

(17)

Then, the parameters $n_1$, $n_2$, $H_1$, $H_2$, A, and B were extracted in order in the form of (18) and (19). The final fitting results are shown in Figure 9. Figure 9a,b show the curves of threshold voltage degradation over time for different $V_{gs}$ and $V_{ds}$ values, measured in the SVE region. Figure 9c,d show the threshold voltage degradation in the MVE region for varying $V_{gs}$ and $V_d$ over time. The fitted parameters for the two different energy regions are listed in

Table 3. Model parameters fitted using data from [16,17].

Parameters	SVE Region	MVE Region
n	0.38324	0.3422
c (${\mathrm{s}}^{-1}$)	0.02505	0.1344
$n_1$	2.99	11.907
$n_2$	1.889	2.082
$H_1\left(\mathrm{V}\right)$	7.545	2.38693
$H_2\left(\mathrm{V}\right)$	0.6403	3.76661
$E_a\left(\mathrm{eV}\right)$	0.076	0.076
${\alpha }_i$	$1.68\pm \delta$	$1.68\pm \delta$
$a_n$	$3.65\pm \delta$	$3.65\pm \delta$
$A \left({\mathrm{m}}^{a_n}{\mathrm{V}}^{-n_1}{\mathrm{s}}^{-n}\right)$	$2.37\times {10}^{-24}\pm \delta$	$2.88\times {10}^{-27}\pm \delta$
$B \left({\mathrm{V}}^{-n_2}{\mathrm{m}}^{a_n}\right)$	$1.9\times {10}^{-27}\pm \delta$	$1.28\times {10}^{-26}\pm \delta$

. Some of the parameters in the table contain the process variation $\delta$, which is a fuzzy parameter that needs to be specifically extracted in different processes.

$$A{R}_i=A·{\left(V_{gs}-V_{T0}\right)}^{n_1}·exp\left(-{\displaystyle \frac{H_1}{V_{ds}-\eta V_{dsat}}}\right)·exp\left(-{\displaystyle \frac{E_{ak}}{k_{B}T}}\right)·exp{\left({\displaystyle \frac{1}{W_{eff}}}\right)}^{a_n}$$

(18)

$$V_{m,ox}=B·{\left(V_{gs}-V_T\right)}^{n_2}·exp\left(-{\displaystyle \frac{E_{ak}}{k_{B}T}}\right)·exp\left(-{\displaystyle \frac{H_2}{V_{ds}-\eta V_{dsat}}}\right)·{\left({\displaystyle \frac{1}{W_{eff}}}\right)}^{a_n}·exp\left({\alpha }_i{V}_b\right)$$

(19)

The relevant parameters related to substrate voltage and width were extracted using data from the literature [16] containing a FinFET device with HKMG at the 45 nm node, which had a total fin height of 30 nm and a width of around 10 to 25 nm. The fitted parameters $a_n$ and ${\alpha }_i$ are also shown in Table 3. The fitted curves compared with raw data are presented in Figure 10.

We compared the model predictions with the degradation data from the literature [11,25]. The model was implemented with the parameters mentioned in Table 3. The accuracy of the model in predicting degradation was verified in different energy regions as well as at different temperatures. The results are shown in Figure 11.

3.2. Model Validation Using TCAD Data

We performed 3D self-consistent electrothermal simulations using the commercial TCAD simulator from Synopsys to analyze the degradation characteristics of the 14 nm node bulk device under HC stress and compared them with the simulation results using the compact model mentioned before.

The nFinFET TCAD model was carefully calibrated to reproduce the I-V characteristics extracted from the reported Intel 14 nm FinFET measurement data [26]. Figure 12a shows the 3D structure of the device, while Figure 12b gives the $I_{DS}-V_{GS}$ curves after calibration. The device parameters are the same as those given in Table 1, except that the source/drain length has been shortened. The device structure was created using the TCAD Silvaco Device Editor (SDE) tool (Silvaco, Santa Clara, CA, USA).

A Fermi model was used to describe the carrier distribution in the heavily doped region of the device during the electrical calibration simulations. The high-field-saturation model was calibrated to describe the mobility degradation, while the QuantumPotential model took into account the quantum confinement effects due to the small device size. The simulations also included a hydrodynamic model as well as a thermodynamic model, which were used in the thermal simulation to study the SHE in bulk FinFETs. And trap model containing a lucky electron model as a gate current model was used for HCI stress simulation.

We simulated HCI degradation with and without self-heating under a stress voltage of 2 V using TCAD. The threshold voltage of the device and the carrier effective mobility were extracted. The threshold voltage was extracted using the constant current method, and the carrier’s effective mobility was obtained by integrally averaging the carrier mobility distribution inside the channel. Figure 13 shows the results with and without self-heating; the scatter points represent the TCAD simulation results, while the lines represent the predictions of the compact model, which is not fitted. The root-mean-square error between the model’s prediction of threshold voltage degradation and the simulation results is $5.82\%$ with self-heating and $16.7\%$ without self-heating. Similarly, the root-mean-square error for the prediction of mobility is $4.44\%$ with self-heating and $4.92\%$ without self-heating. Meanwhile, the simulation results indicate that the threshold voltage degradation due to HCI rises by $46.3\%$ in the case of coupled self-heating, while the mobility drops by $12.42\%$. As a consequence, it is very necessary to consider the self-heating effect in HCI degradation.

Figure 14 illustrates the comparison between the simulation results and the predictions of the compact model for different numbers of fins and fin widths, which are consistent with the degradation trends reported in [12,16]. The root-mean-square error is kept below $12\%$. The results show that the effects of these two factors on HCI degradation gradually decrease as the number of fins increases or the fin width increases to a certain extent.

The lifetime of devices under HC stress is the time taken for the threshold voltage to degrade by $10\%$. Under HC stress conditions, the device experiences accelerated degradation.

Table 4. Stress lifetime under different $V_b$ values.

Lifetime Under HC Stress (2 V)	${\mathit{V}}_{\mathit{b}}=0$	${\mathit{V}}_{\mathit{b}}=-0.5$ V	${\mathit{V}}_{\mathit{b}}=0.5$ V
TCAD data	$0.980\times {10}^3$ s	$1.009\times {10}^3$ s	$0.889\times {10}^3$ s
Compact model	$0.933\times {10}^3$ s	$1.028\times {10}^3$ s	$0.803\times {10}^3$ s

presents the stress lifetime obtained from both the simulation and model predictions with substrate bias voltage. As reported in [6], HCI degradation is exacerbated under forward bias, resulting in a shorter lifetime, while reverse bias alleviates degradation to some extent. As shown in Table 4, the improvement in lifetime due to reverse bias is minimal. Furthermore, the device’s lifetime under operational voltage was predicted using both the conventional model (self-saturation model) and the compact model for comparison. The results were obtained under 0.74 V DC mode, and the lifetime extracted from [11] was also listed. The results are shown in

Table 5. Working lifetime predicted by different models.

	Compact Model	Traditional Model	Lifetime Obtained from [11]
Lifetime under working condition (0.74 V)	$3.18\times {10}^8\mathrm{s}\left(10\mathrm{years}\right)$	$3.78\times {10}^8\mathrm{s}\left(12\mathrm{years}\right)$	$3.33\times {10}^8\mathrm{s}\left(10\mathrm{years}\right)$

. The lifetime prediction from the conventional model is overly optimistic, as it only accounts for interface traps, neglecting the impact of oxide traps, which play a significant role in long-term degradation. Additionally, the conventional model does not incorporate the self-heating effect. In contrast, the model developed in this study predicts a device lifetime of approximately 10 years, which is consistent with the typical operational lifespan of similar devices.

4. Conclusions

This study presents a compact model for HCI-induced degradation in Bulk FinFETs. The model is based on solving the reaction–diffusion equation, incorporating both the self-saturating power–law behavior of interfacial traps and the long-term effects of oxide traps, which can capture the two-stage degradation phenomenon. Further refinement of the model accounts for the influences of self-heating, fin width, and substrate voltage, providing a comprehensive explanation of experimental data across different temperatures and stress–voltage conditions. Parameters specific to different stress regions are extracted from experimental data at the 14 nm node. We compare the model’s degradation predictions with our simulation and experimental results, as well as the predicted lifetimes, all of which show good consistency. The model is applicable in Bulk FinFET devices around the 14 nm–50 nm node, and further model extension studies could include process variation modeling as well as modeling of other structures such as SOI and GAAFET devices.