Search Results (387)

A 3.0 V bandgap reference (BGR) for battery management integrated circuit (BMIC) is presented, achieving a low temperature coefficient (TC) and a high power supply rejection ratio (PSRR). Precision is enhanced through two techniques: (1) a base current correction technique eliminates errors from the bipolar junction transistor (BJT) base current, and (2) a high-order temperature compensation circuit counteracts the inherent nonlinearity of the BJT’s base-emitter voltage (V_BE). Furthermore, an improved flipped voltage follower (FVF) pre-regulation structure is integrated for efficient power supply noise suppression. The circuit is designed based on a 180 nm BiCMOS process, occupying a layout area of 0.0459 mm². Post-layout simulation results demonstrate that the BGR achieves a temperature coefficient of 1.59 ppm/°C over the −40 °C to 125 °C temperature range. Within a supply voltage range of 4.7 V to 5.3 V, the line regulation is 0.00058 mV/V. At a 5.0 V supply voltage, the quiescent current is 23 μA, and the PSRR is −128.89 dB@1 Hz and −102.9 dB@1 kHz. Full article

NMOSFET, whose gate is on the top of the n-p-n junction with gate oxide in between, is called the n-channel transistor. This bipolar junction underneath the gate oxide may provide an n-n-n-conductive channel as the gate is applied with a positive bias over the threshold voltage (V_th). Conceptually, the definition of an n-type or p-type semiconductor depends on whether the corresponding Fermi energy is higher or lower than the intrinsic Fermi energy, respectively. The positive bias applied to the gate would bend down the intrinsic Fermi energy until it is lower than the original p-type Fermi energy, which means that the p-type becomes strongly inverted to become an n-type. First, the thickness of the inversion layer is derived and presented in a planar 40 nm MOSFET, a 3D 240 nm FinFET, and a power discrete IGBT, with the help of the p (1/m³) of the p-type semiconductor. Different ways of finding p (1/m³) are, thus, proposed to resolve the strong inversion layers. Secondly, the conventional formulas, including the triode region and saturation region, are already modified, especially in the triode region from a continuity point of view. The modified formulas then become necessary and available for fitting the measured characteristic curves at different applied gate voltages. Nevertheless, they work well but not well enough. Thirdly, the electromagnetic wave (EM wave) generated from accelerating carriers (radiation by accelerated charges, such as synchrotron radiation) is proposed to demonstrate phonon scattering, which is responsible for the Source–Drain current reduction at the adjoining of the triode region and saturation region. This consideration of reduction makes the fitting more perfect. Fourthly, the strongly inverted layer may be formed but not conductive. The existing trapping would stop carriers from moving (nearly no mobility, μ) unless the applied gate bias is over the threshold voltage. The quantum confinement addressing the quantum well, which traps the carriers, is to be estimated. Full article

The choice of a suitable isolated and bidirectional DC/DC converter (IBDC) topology is an important step in the design of a bidirectional electric vehicle (EV) charging system. In this context, six 10 kW rated silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET)-based dual-active bridge (DAB) converter topologies, supplied by a +750/0/−750 V bipolar DC link, are analyzed and compared in this article. The evaluation criteria include the required volt-ampere semiconductor ratings, loss distribution, efficiency, and thermal considerations of the considered converter configurations. The IBDC topologies are compared based on the observations and results obtained from theoretical analysis, electro-thermal simulations, and experiments, considering the same voltage and power conditions. The advantages and disadvantages of the topologies, in terms of the considered evaluation criteria, are discussed. It is shown that the series-resonant (SR) input-series output-parallel (ISOP) full-bridge (FB) DAB converter configuration is the most suitable design choice for the considered EV charging application based on the chosen operating conditions and evaluation criteria. Full article

This study presents an Artificial Neural Network (ANN)-based adaptive switching frequency control strategy for series Direct current (DC) motor drives used in battery-powered mining locomotives, aiming to extend the lifetime of critical power-electronic components such as Insulated Gate Bipolar Transistors (IGBTs) and DC bus capacitors. In embedded systems for electric traction, two dominant degradation factors, motor current ripple and IGBT temperature fluctuation, significantly shorten component lifetimes. Conventional fixed switching frequencies impose a trade off: higher frequencies reduce current ripple but increase IGBT losses and temperature, while lower frequencies yield the opposite effect. Consequently, an adaptive variable switching frequency control algorithm is proposed to perform real-time decision making by predicting the optimal switching frequency that minimizes both motor current ripple and IGBT thermal fluctuations. The proposed algorithm was trained with a dataset acquired from current sensors, NTC temperature sensors, and a potentiometer defining the target current (PWM duty). Performance comparisons with a fixed frequency demonstrate that the ANN-driven approach maintains an average current ripple of less than 5% (average) and 10% (maximum), while the lifetime of the IGBT and capacitors improves. A fairness index was defined to quantify the relative lifetime improvement of the IGBT and capacitor, revealing that the proposed variable frequency switching model enhances the overall system performance by up to 13 times compared to fixed-frequency operation. These results confirm that the integration of embedded machine learning and adaptive control algorithms can substantially enhance the durability and efficiency of power-electronic systems in real-time industrial applications. Full article

Silicon carbide (SiC) is a key material for electronics operating in harsh environments due to its wide bandgap, high thermal conductivity, and radiation hardness. In this work, we present a SPICE model for a 4H-SiC BJT and TTL inverter exposed to gamma radiation. The devices were fabricated using a dedicated SiC bipolar process at KTH (Sweden) and tested at the ⁶⁰Co Calliope (Italy) facility up to 800 krad _(Si). Experimental data, including Gummel plots and inverter transfer characteristics, were used to calibrate and refine a VBIC-based SPICE model. The adjusted model accounts for both bulk and surface degradation mechanisms by extracting parameters of forward current gain (βF), saturation current (IS), base resistance (RB), and forward transit time (TF). Results show a uniform degradation of BJTs, primarily manifested as reduced current gain and increased base resistance, while the inverter maintained functional operation up to 600 krad_(Si). Extrapolation of the SPICE model predicts a failure threshold near 16 Mrad_(Si), far exceeding the tolerance of conventional silicon circuits. By linking radiation-induced defects at the material and interface levels to circuit-level behavior, the proposed model enables realistic design and lifetime prediction of SiC integrated circuits for satellites, planetary missions, and other radiation-intensive applications. Full article

In radio frequency (RF) systems, the mixer is a critical component for achieving frequency conversion in electromagnetic sensor backends. This paper proposes a mixer design methodology aimed at improving noise figure and conversion gain specifically for sensor signal processing applications. This design employs a process incorporating high-quality bipolar junction transistors (BJTs) and adopts a mixer-first architecture instead of a conventional low noise amplifier (LNA). By optimizing the layout and symmetry of the BJTs, the input impedance can be flexibly adjusted, thereby simplifying the receiver front-end while simultaneously improving local oscillator (LO) feedthrough. Design and simulation were completed using Advanced Design System (ADS) 2020 software. Simulation results demonstrate that the proposed mixer exhibits significant advantages in suppressing noise and interference while enhancing conversion gain, making it particularly suitable for electromagnetic sensor backend applications. Full article

Reliable multilevel inverter IGBT modules require precise loss and heat management, particularly in severe traction applications. This paper presents a comprehensive modeling framework for three-level T-type neutral-point clamped (TNPC) inverters using a high-power Insulated Gate Bipolar Transistor (IGBT) module that combines model predictive control (MPC) with space vector pulse width modulation (SVPWM). The particle swarm optimization (PSO) algorithm is used to methodically tune the MPC cost function weights for minimization, while achieving a balance between output current tracking, stabilization of the neutral-point voltage, and, consequently, a uniform distribution of thermal stress. The proposed SVPWM-MPC algorithm selects optimal switching states, which are then utilized in a chip-level loss model coupled with a Cauer RC thermal network to predict transient chip-level junction temperatures dynamically. The proposed framework is executed in MATLAB R2024b and validated with experiments, and the SemiSel industrial thermal simulation tool, demonstrating both control effectiveness and accuracy of the electro-thermal model. The results demonstrate that the proposed control method can sustain neutral-point voltage imbalance of less than 0.45% when operating at 25% load and approximately 1% under full load working conditions, while accomplishing a uniform junction temperature profile in all inverter legs across different working conditions. Moreover, the results indicate that the proposed control and modeling structure is an effective and common-sense way to perform coordinated electrical and thermal management, effectively allowing for predesign and reliability testing of high-power TNPC inverters. Full article

The reliability and lifetime of insulated gate bipolar transistors (IGBTs) are critical to ensuring the stability and safety of power electronic systems. IGBTs are widely used in electric vehicles, renewable energy systems, and industrial automation. However, their degradation over time poses a significant risk to system performance. Therefore, this paper proposes a data-driven approach based on a Long Short-Term Memory (LSTM) network optimized by a Genetic Algorithm (GA) to predict IGBT degradation. The study examines the health monitoring of insulated gate bipolar transistors from a device physics perspective. Degradation mechanisms that alter parasitics and electro-thermal stress produce characteristic changes in the turn-off overvoltage and the on-state voltage. Using power-cycling data from packaged half-bridge modules, an LSTM-based sequence model configured by a genetic algorithm search reduces error against an identically trained baseline (RMSE = 0.0073, MAE = 0.057, MAPE = 0.726%) under the shared protocol, with the clearest advantages in the early stage of degradation. These results support predictive maintenance and health management in power-electronic systems. Full article

New energy vehicles (NEVs) rely heavily on Insulated-Gate Bipolar Transistors (IGBTs) to perform frequent battery voltage conversions for operations such as acceleration, deceleration, and hill climbing. Consequently, effective thermal management of the IGBT junction temperature is critically important. This study investigates the junction temperature of IGBT modules equipped with pin-fin heat sinks of varying spacings under diverse operating conditions. The effects of the coolant inlet flow velocity and temperature on the junction temperature were examined. Furthermore, the pin-fin heat sink structure was optimized to enhance temperature uniformity across the IGBT chips. The results indicate that (1) IGBT modules with small-spacing pin-fin heat sinks exhibit improved thermal performance and enhanced temperature uniformity under specific conditions; (2) coolant inlet flow velocity is positively correlated with both module cooling efficiency and temperature uniformity; (3) coolant inlet temperature is inversely correlated with module junction temperature and chip junction temperature uniformity; and (4) among the three optimization schemes evaluated, the dual-channel, non-uniformly spaced pin-fin heat sink delivered the optimal performance, reducing the maximum junction temperature difference between IGBT chips to approximately 0.5 °C and that between diode chips to approximately 1.0 °C. Full article

The advent of silicon carbide (SiC) semiconductors in electric traction enables several benefits, including the shift to passive cooling. However, it requires a conjugate heat transfer analysis to understand the temperature distribution and variation. While steady-state solutions exist, transient conditions in rail vehicles remain challenging. This paper develops two analytical models to predict temperature distribution and variation, validated against numerical simulations. An electric motor model estimates power losses in the converter, defining heat dissipation. The complete model is tested under realistic drive cycles, linking operational conditions to power losses and free flow speed. The results show the model effectively captures temperature variations, with higher losses during acceleration and larger temperature surges of around 70 K at lower speeds. Furthermore, the temperature at the junction was observed to be 20 K higher than at the base position and to exceed 420 K at a more downstream location. Thus, the proposed method captures the temperature variations considering different physical effects with reasonable accuracy and significantly faster computation times than transient numerical simulations. Full article

This paper provides an in-depth review of degradation mechanisms and condition monitoring methods for critical components in modular multilevel converter (MMC) high-voltage direct current (HVDC) systems, including insulated gate bipolar transistors (IGBTs), metallized film capacitors, and cross-linked polyethylene (XLPE) DC cables. This study systematically evaluates the strengths and limitations of existing technologies, while also projecting future trends in technological advancements. By exploring the multi-fields-coupled degradation processes of these components, the mechanisms of switching oscillations, and the flexible and controllable applications of MMC, this review offers valuable insights for improving the accuracy, real-time performance, and reliability of component condition monitoring. The findings aim to contribute to the advancement and broader application of MMC HVDC systems in modern power networks. Full article

In high-power insulated gate bipolar transistor (IGBT) module thermal management, the structural design of microchannel cooling plates plays a crucial role in determining heat dissipation efficiency and temperature uniformity. This study focuses on the effects of honeycomb-structured unit dimensions and arrangements, as well as inlet/outlet configurations of the cooling plate on its thermal and flow performance. Additionally, the influence of different coolant inlet velocities and temperatures is investigated. Under constant coolant flow rate and boundary conditions, four design configurations with varying pore widths and channel spacings were evaluated numerically. The results indicate that the optimized honeycomb structure can reduce the module’s peak temperature by approximately 8.7 K while significantly improving temperature uniformity and maintaining a moderate pressure drop. Moreover, increasing the number of inlets and outlets effectively lowers the pressure drop and enhances thermal uniformity. Although increasing the coolant flow rate and reducing the inlet temperature can further improve cooling performance, these measures also lead to notable increases in energy consumption and pressure loss. Therefore, a trade-off between thermal enhancement and system energy efficiency must be considered in practical applications. The findings of this study provide practical guidance for the design optimization of high-efficiency microchannel liquid cooling systems in power electronic applications. Full article

In this article, thermal investigation methods for electrically insulating and thermally conductive substrate materials will be presented. The investigations were performed in their real-world application environment, i.e., in the form of IGBT (insulated gate bipolar transistor) module substrate plates. First, the overall thermal resistance and thermal structure function of the system in a multivariable parameter space were revealed using CFD (computational fluid dynamics) simulations. Afterwards, thermal transient testing was performed on real samples, with the help of which the thermal resistance values of the modules were determined using the thermal dual interface test method. The presented tests are not intended to determine material parameters, but to rank different substrate materials based on their thermal performance. Full article

A reliable prediction of the remaining useful life of critical electronic components, such as insulated gate bipolar transistors, is necessary for preventing failures in many industrial applications. Recently, diverse machine-learning techniques have been used for this task. However, they are generally focused on capturing the temporal dependencies or on representing the probabilistic nature of the degradation of the device. This work proposes a neural network architecture that combines long short-term memory and mixture density networks to address both targets simultaneously when modeling the remaining useful life. The proposed model was trained and evaluated using a real dataset of insulated gate bipolar transistors, demonstrating a high capacity for predicting the remaining useful life of the validation devices. The proposed model outperformed the other algorithms considered in the study in terms of root mean squared error and coefficient of determination. In general terms, an average reduction of at least 18% of the root mean squared error was obtained when compared with the second-best model among those considered in this work, but in some specific cases, the root mean squared error during the prediction of remaining useful life decreased up to 21%. In addition to the high performance obtained, the characteristics of the network output also facilitated the creation of confidence intervals, which are more informative than solely exact values for decision-making. Full article

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article