Search Results (238)

Silicon carbide (SiC) MOSFETs, as one of the representative power electronic devices, have faced reliability challenges due to threshold voltage (V_th) instability under dynamic gate stress. To explore the underlying mechanisms, this work investigates 4H-SiC MOS structures (P-MOS and N-MOS) under AC bias temperature instability (AC BTI) stress, utilizing a laser to generate minority carriers and simulate realistic switching conditions. Through combined capacitance–voltage (C-V) and gate current–voltage (J_g-V_g) characterizations on P-MOS and N-MOS devices before and after degradation at different temperatures, we reveal a critical temperature dependence in defect interactions. At room temperature, degradation is dominated by electron trapping in shallow interface states and near-interface traps (NITs). In contrast, high-temperature stress activates charge exchange with deep-level, slow states. Notably, a positive V_FB shift is consistently observed in both N-MOS and P-MOS devices under AC stress, confirming that electron trapping is the dominant cause of the commonly observed positive V_th shift in SiC MOSFETs. These findings clarify the distinct defect-mediated mechanisms governing dynamic V_th instability in SiC devices, providing fundamental insights for interface engineering and reliability assessment. Full article

Bidirectional switches are highly required power electronics units for the design of power converters, especially for direct matrix converters. This article presents the design and implementation of a compact bidirectional switch based on SiC-MOSFET technology, aimed at high-efficiency, high-density power electronics applications. The proposed architecture employs surface-mount components, optimizing both the occupied area and electrical performance. The selected switching device is the IMBG120R053M2H from Infineon, a SiC-MOSFET known for its low on-resistance, high reverse-voltage blocking capability, and excellent switching speed. To drive the power devices, the UCC21521 gate driver integrates two independent isolated outputs in a single package, enabling precise control and reduced electromagnetic interference (EMI). The developed design supports bidirectional current conduction and voltage blocking, offering a robust and scalable solution for next-generation power converters. Design criteria, simulation results, and experimental validations are discussed. Full article

Silicon carbide (SiC) power converters are increasingly used in automotive, renewable energy, and industrial applications. While reliability assessments are typically performed at either the device or system level, an integrative approach that simultaneously evaluates both levels remains underexplored. This article presents a novel system-level simulation method with two strategies to evaluate the reliability of power devices and a resonant converter under varying temperatures and total ionizing doses (TIDs). Temperature-sensitive electrical parameters (TSEPs), such as on-state resistance ($R_{\mathrm{ON}}$) and threshold voltage shift ($\Delta V_{\mathrm{TH}}$), are calibrated and analyzed using a B1505A curve tracer. These parameters are incorporated into the system-level simulation of a 300 W resonant converter with a boosting cell. Both Silicon (Si) and SiC-based power resonant converters are assessed for power application in space engineering and harsh environments. Additionally, gate-oxide degradation and $\Delta V_{\mathrm{TH}}$-related issues are discussed based on the simulation results. The thermal-strategy results indicate that SiC MOSFETs maintain a more stable conduction loss at elevated temperatures, exhibiting higher reliability due to their high thermal conductivity. Conversely, increased TIDs result in a negative shift in conduction losses across all SiC devices under the radiation strategy, affecting the long-term reliability of the power converter. Full article

This work presents a highly compact and scalable 1.2-kV SiC MOSFET half-bridge building-block module enabled by a die-integrated 3D PCB packaging technology. Compared with conventional DBC-based or TO-247-based SiC half-bridge modules, the proposed design reduces the physical volume and weight by more than 90% while maintaining full compatibility with standard PCB manufacturing processes. The vertically laminated DC+/DC− conductors and symmetric PCB–die–PCB stack establish a tightly confined commutation loop, resulting in a measured power-loop inductance of 2.2 nH and a 3.8 nH gate-loop inductance—representing up to 94% and 89% reduction relative to discrete device implementations. Because the parasitic parameters are intrinsically well-balanced across replicated units and the mutual inductance between adjacent modules remains extremely small, the structure naturally supports current sharing during parallel operation. Thermal and insulation evaluations further confirm the suitability of copper filling via high-Tg laminated PCB substrates for high-power SiC applications, achieving withstand voltages exceeding twice the rated bus voltage. The proposed module is experimentally validated through finite-element parasitic extraction and 950 V double-pulse testing, demonstrating controlled dv/dt behavior and robust switching performance. This work establishes a manufacturable and parallel-friendly packaging approach for high-density SiC power conversion systems. Full article

This work presents the simulation and design of 3C-SiC power MOSFETs, focusing on critical parameters including avalanche impact ionization, breakdown voltage, bulk and channel mobilities, and the trade-off between on-resistance and breakdown voltage. The device design is carried out by evaluating the blocking voltage of scaled structures as a function of the blocking layer’s doping concentration. To mitigate edge-effect breakdown at the p-well/n-drift interface, a step-profile doping strategy is employed. Multiple transistor layouts with varying pitches are developed using a commercially available device simulator. Results are benchmarked against a one-dimensional analytical model, validating the on-state resistance, current–voltage behavior, and overall accuracy of the simulation approach. For the selected material properties, simulations predict that a 600 V 3C-SiC MOSFET achieves an on-state resistance of 0.8 mΩ·cm², corresponding to a 7 μm drift layer with a doping concentration of 1 × 10¹⁶ cm⁻³. Full article

Power semiconductor devices are fundamental components in modern electronic power conversion. In applications demanding high power density and efficiency, the choice between silicon (Si) IGBTs and Silicon Carbide (SiC) MOSFETs is critical. SiC MOSFETs, owing to their high critical electric field, superior thermal conductivity, wide band gap, and low power loss, realize significant performance improvements and compact design. This work presents a comprehensive, simulation-driven comparative investigation under identical setups, evaluating both technologies across various parameters. The effects of temperature variations on gate-source threshold voltage drift, current slew rate, device stress, and energy dissipation during switching transitions are evaluated. Furthermore, the characteristic switching behavior when the DC-bus voltage, gate resistance, and load current are varied is investigated. This study addresses a current scarcity of systematic investigation by presenting a comprehensive comparative evaluation of switching losses and efficiency across varied operating conditions, providing validated conclusions for the design of advanced WBG converters. The results demonstrate that SiC exhibits lower losses and faster switching speeds than Si IGBTs, with minimal temperature-dependent loss variations, unlike Si devices, whose losses rise significantly with temperature. Si shows distinct tail currents during turn-off, absent in SiC devices. A conclusive comparative evaluation of switching energy losses under varied operating conditions demonstrates that SiC devices can effectively retrofit Si counterparts for fast, low-loss, high-efficiency applications. Full article

4H-SiC has been studied and applied in power semiconductor devices due to its wider band gap and higher thermal conductivity than those of Si and hence has great potential for power devices operating at high powers and high temperatures. The introduction of the superjunction (SJ) structure for the power MOSFETs enables further reduction in the ON resistance while maintaining the breakdown voltage. In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the Atlas device simulator. The simulation results suggest the step-shape SJ DMOSFET can further reduce the specific ON resistance and the gate-drain capacitance while maintaining the breakdown voltage compared with the optimized conventional SJ DMOSFET. In addition, that the multi-pillar SJ DMOSFET demonstrates better performance than that of the optimized conventional SJ DMOSFET was also verified in this work. Full article

In pursuit of enhancing the performance of power converters, high-frequency power devices have become indispensable due to their superior switching capabilities, reduced conduction loss, and enhanced thermal performance. However, optimizing their efficiency requires a profound comprehension of the interplay between various parameters (the current, voltage, and gate resistance) on switching dynamics and power losses. This study presents a comprehensive framework of loss characterization with multi-parametric variations. The influence of drain-source current $\left(I_{ds}\right)$, DC voltage $\left(V_{dc}\right)$, and gate resistor $\left(R_g\right)$ on switching and conduction losses are explicitly quantified. A significant contribution of this study lies in the comprehensive analytical and empirical characterization of the turn-on and turn-off power dissipation dynamics in SiC MOSFETs, emphasizing the intricate interplay between parameters and efficiency. Conventional studies primarily focus on empirical loss characterization, yet this work advances the field by introducing a predictive loss model that systematically correlates $R_g$, $I_{ds}$, and $V_{dc}$ variations with induced switching dynamics, and EMI mitigation strategies. Increasing $R_g$ effectively suppresses voltage overshoots and mitigates ringing effects, concurrently prolonging switching events, thereby broadening the power dissipation profile and influencing system-level performance. Furthermore, this study rigorously evaluates the commutation behavior of the SiC MOSFET/SBD pair, providing an in-depth examination of its dynamic loss characterization under varying conditions. This novel insight establishes a crucial framework for efficiency drive optimization. Full article

This work investigates bias-temperature instability (BTI) in 1700 V 4H-SiC MOSFETs under realistic 1 MHz switching conditions with simultaneous gate and drain stress. Threshold-voltage measurements reveal that the degradation does not follow the classical Reaction–Diffusion behavior typically assumed for silicon devices. Instead, the power-law exponent n shows a clear increase at the largest negative gate bias (−10 V), indicating a field-driven trap-generation mechanism. Temperature-dependent stress tests further show a negative activation energy (−0.466 eV), consistent with degradation accelerating at lower temperatures due to suppressed detrapping. The results demonstrate that conventional silicon BTI models cannot be directly applied to SiC technologies and that fixed-n lifetime extrapolation leads to significant errors. A bias-dependent, field-driven framework for estimating time-to-failure is proposed, offering more accurate and practical reliability prediction for high-power SiC converter applications. Full article

A Si/SiC heterojunction double-trench MOSFET with improved conduction characteristics is proposed. By replacing the N+ source and P-ch regions with silicon, the device forms a Si/SiC heterojunction that exhibits Schottky-like characteristics, effectively deactivating the parasitic PiN body diode and improving third-quadrant performance. A high-k gate dielectric is incorporated to induce a strong electron accumulation layer at the heterointerface, thinning the energy barrier and enabling tunneling-dominated current transport, thereby significantly enhancing the first-quadrant performance. TCAD simulation results demonstrate that the proposed device achieves a specific on-resistance (R_on,sp) of 1.78 mΩ·cm², representing a 20.5% reduction compared to the conventional SiC DTMOS, while maintaining a comparable breakdown voltage (BV) of approximately 1380 V. A significant reduction in the third-quadrant turn-on voltage (V_on) is achieved with the proposed structure, from 2.74 V to 1.53 V. Meanwhile, the unipolar conduction mechanism similar to that of Schottky effectively suppresses bipolar degradation. To enhance device reliability, the design incorporates a trenched source and heavily doped P-well, which collectively mitigate high electric field concentrations at the trench corners. The proposed device offers an integration strategy enhancing both forward conduction and reverse conduction in high-voltage power electronics. Full article

The choice of a suitable isolated and bidirectional DC/DC converter (IBDC) topology is an important step in the design of a bidirectional electric vehicle (EV) charging system. In this context, six 10 kW rated silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET)-based dual-active bridge (DAB) converter topologies, supplied by a +750/0/−750 V bipolar DC link, are analyzed and compared in this article. The evaluation criteria include the required volt-ampere semiconductor ratings, loss distribution, efficiency, and thermal considerations of the considered converter configurations. The IBDC topologies are compared based on the observations and results obtained from theoretical analysis, electro-thermal simulations, and experiments, considering the same voltage and power conditions. The advantages and disadvantages of the topologies, in terms of the considered evaluation criteria, are discussed. It is shown that the series-resonant (SR) input-series output-parallel (ISOP) full-bridge (FB) DAB converter configuration is the most suitable design choice for the considered EV charging application based on the chosen operating conditions and evaluation criteria. Full article

SiC MOSFETs face prominent reliability issues due to higher voltage resistance requirements and continued device miniaturization. The lifetime prediction of SiC MOSFET plays a crucial role in improving the reliability of devices and systems. However, existing methods still face challenges in terms of adaptability, stability, and accuracy due to the complexity of the failure process in SiC MOSFET. This article proposes an improved grey wolf optimizer-based long short-term memory (IGWO-LSTM) model for SiC MOSFET lifetime prediction. The model introduces a Tent chaotic mapping to generate an initial population with optimal distribution, ensuring comprehensive search space coverage and enhancing dynamic search adaptability. Then, a nonlinear control parameter strategy and the principle of particle swarm optimization (PSO) are added. The feature extraction capability of the model is strengthened, and the exploration and exploitation phases are dynamically balanced. The optimizations enable faster discovery of the global optimum while maintaining solution quality, thereby improving prediction accuracy and stability. Finally, power cycling experiments were conducted on two types of SiC MOSFETs with different internal resistances to validate the effectiveness of the proposed model. The proposed IGWO-LSTM model achieves high prediction accuracy, with R² values of 96.2%, 94.8%, 94.1%, and 93.9% for four SiC MOSFETs, and RMSE values as low as 0.0117, 0.0143, 0.0152, and 0.0158, respectively. This represents an average improvement in R² by 16%, 8%, and 4%, and a reduction in RMSE by up to 67.03%, 50.39%, and 31.57% compared with other intelligent models. Similarly, IGWO-LSTM achieves reductions in MAE of approximately 68%, 50%, and 30%, with corresponding reductions in MAPE of about 70%, 48%, and 26%, respectively. The results demonstrate superior performance in prediction accuracy, stability, and adaptability of the proposed model. Full article

Silicon carbide (SiC) power converters are attracting increasing interest due to their significant advantages in terms of efficiency, switching speed, and greater temperature tolerance compared to traditional silicon-based converters. Tools to improve the design process, such as those to predict the switching behavior of silicon carbide-based power converters, can be of great help, e.g., in studying critical electrical/thermal stress in power devices. This work aims to present an effective multi-objective optimization method to identify the main parasitic parameters of a SiC half-bridge power converter related to the board layout and device packaging. This goal was achieved by minimizing the errors between the system responses carried out by the simulated power converter and the measurements collected from a limited number of experimental tests. The feasibility and effectiveness of the method are verified by tests performed on a 1200 V, 75 A, SiC half-bridge converter. Although this methodology has been validated for a specific converter topology, it can be extended to model more complex power converter structures. Full article

Accurately assessing the remaining useful life (RUL) is a significant challenge to the reliability of Silicon Carbide (SiC) MOSFETs and is crucial for their safe operation. Consequently, this paper proposes a novel data-driven prediction method that integrates Successive Variational Mode Decomposition (SVMD), the Sparrow Search Algorithm (SSA), and the Transformer model. The threshold voltage V_th is selected as the degradation parameter for prediction. Firstly, SVMD is utilized to decompose the original V_th data into a degradation trend component and several fluctuation components with different central frequencies, thereby providing a more precise feature for prediction models. Subsequently, based on the Transformer model, trend predictions are conducted on each intrinsic mode function (IMF) derived from SVMD, and these results are aggregated as the final predicted value of V_th. The hyperparameters of the Transformer are optimized using SSA to enhance prediction accuracy. Ultimately, a power cycling platform is constructed to acquire the dataset of the device, where the device is subjected to rated current and 80 °C junction temperature fluctuation stress during testing. Building upon this, the difference between the number of cycles when V_th reaches its upper limit and the current number of cycles is determined as the predicted RUL value. Results demonstrate that compared to both a single Transformer model and the SVMD-Transformer model, the proposed method achieves a higher coefficient of determination (R²) and a lower root mean square error (RMSE), indicating superior prediction performance. Full article

Ultra-bandgap semiconductor material, β-gallium oxide (β-Ga₂O₃), has great potential for fabricating the next generation of high-temperature, high-voltage power devices due to its superior material properties and cost competitiveness. In addition, β-Ga₂O₃ has the advantages of high-quality, large-size, low-cost, and controllable doping, which can be realized by the melt method. It has a wide bandgap of 4.7–4.9 eV, a large breakdown field strength of 8 MV/cm, and a Baliga figure of merit (BFOM) as high as 3000, which is approximately 10 and 4 times that of SiC and GaN, respectively. These properties enable β-Ga₂O₃ to be strongly competitive in power diodes and metal-oxide-semiconductor field-effect transistor (MOSFET) applications. Most of the current research is focused on electrical characteristics of those devices, including breakdown voltage (V_BR), specific on-resistance (R_ON,SP), power figure of merit (PFOM), etc. Considering the rapid development of β-Ga₂O₃ diode technology, this review mainly introduces the research progress of different structures of β-Ga₂O₃ power diodes, including vertical and lateral structures with various advanced techniques. A detailed analysis of Ga₂O₃-based high-voltage power diodes is presented. This review will help our theoretical understanding of β-Ga₂O₃ power diodes as well as the development trends of β-Ga₂O₃ power application schemes. Full article