Temperature-Dependent Degradation in SiC MOS Structures Under Laser-Assisted AC BTI

Abstract

Silicon carbide (SiC) MOSFETs, as one of the representative power electronic devices, have faced reliability challenges due to threshold voltage (V_th) instability under dynamic gate stress. To explore the underlying mechanisms, this work investigates 4H-SiC MOS structures (P-MOS and N-MOS) under AC bias temperature instability (AC BTI) stress, utilizing a laser to generate minority carriers and simulate realistic switching conditions. Through combined capacitance–voltage (C-V) and gate current–voltage (J_g-V_g) characterizations on P-MOS and N-MOS devices before and after degradation at different temperatures, we reveal a critical temperature dependence in defect interactions. At room temperature, degradation is dominated by electron trapping in shallow interface states and near-interface traps (NITs). In contrast, high-temperature stress activates charge exchange with deep-level, slow states. Notably, a positive V_FB shift is consistently observed in both N-MOS and P-MOS devices under AC stress, confirming that electron trapping is the dominant cause of the commonly observed positive V_th shift in SiC MOSFETs. These findings clarify the distinct defect-mediated mechanisms governing dynamic V_th instability in SiC devices, providing fundamental insights for interface engineering and reliability assessment.

1. Introduction

As the key device for the next generation of power electronics, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have a wide range of applications, including electric vehicles, rail transportation, and photovoltaic power generation, due to the superior material properties such as a high critical breakdown field, high thermal conductivity, and high electron saturation velocity [1,2,3,4]. However, due to the high-density traps on and near the SiC/SiO₂ interface, SiC MOSFETs suffer from threshold voltage instability, which deteriorates the safe operation [4,5,6].

In order to investigate the threshold voltage instability under realistic operating conditions, gate switching instability (GSI), also known as AC bias temperature instability (AC BTI), has been extensively studied [7,8,9,10,11,12,13,14]. Research mainly focused on various stress parameters, including stress time, gate bias, switching speed, switching frequency, and operating temperature. Studies have shown that [15,16], at low frequencies, the threshold voltage (V_th) shift under AC gate stress can be approximated as a simple superposition of positive and negative static BTI effects. In contrast, at high frequencies, the shift is primarily triggered by the switching process itself. The dynamic V_th drift has been found to correlate with the accumulation of switching cycles rather than the frequency [9,17]. Generally, the duty cycle has minimal impact on dynamic V_th drift in SiC MOSFETs, with effects observed only under extreme conditions [18]. Furthermore, a faster turn-on time leads to more pronounced V_th drift, while the turn-off time shows negligible influence [19,20]. While most studies have focused on the electrical characteristics of full SiC MOSFET devices, there has been relatively little investigation into the more fundamental SiC MOS capacitor structure. This gap exists partly because the simple capacitor structure is often considered insufficient to represent the complicated degradation behavior of the MOSFETs.

In this work, differing from existing AC BTI studies, we address this limitation by employing an extra laser to generate minority carriers during the AC BTI process, thereby simulating the alternating presence of electrons and holes at the interface of the MOS structure under AC stress conditions. It provides a direct method for detecting the impact of AC stress on the SiC/SiO₂ interface with a more straightforward characterization of the behavior of interface and near-interface traps. The main goal of this study is to elucidate the underlying mechanisms of defect interaction under AC BTI stress in SiC MOS structures through combined capacitance–voltage (C-V) and gate current–voltage (J_g-V_g) measurements. Our principal findings reveal a temperature-dependent difference in defect interaction mechanisms: electron trapping in shallow states dominates at room temperature, while thermal activation enables charge exchange with deep-level defects at high temperature, leading to distinct impacts on flat-band voltage stability and tunneling characteristics in P-MOS and N-MOS structures.

2. Experiments

In this work, N-MOS and P-MOS structures are simultaneously manufactured utilizing a commercial SiC fabrication process with mainstream parameters. As schematically shown in Figure 1a,b, the devices are fabricated on the same wafer in which an n-type epitaxial layer is grown on 4H-SiC [0001] with a 4° off-axis toward $\left[11\overline{2}0\right]$. Around 57 nm-thick gate oxide is thermally grown in dry oxygen, followed by nitric oxide annealing, and then poly-Si and the multi-layer gate metal are deposited on it. Particularly, the P-MOS structures are built on regions with the same p-well doping (N_D = 2 × 10¹⁷ cm⁻³) as the channel region of the SiC MOSFETs, and the N-MOS structures are fabricated on the SiC epilayer (N_A = 1 × 10¹⁶ cm⁻³), corresponding to the doping condition in the JFET region. The gate area of both N-MOS and P-MOS structures is 7.0686 × 10⁻⁴ cm². To stimulate the effects of AC stress on the channel region and JFET region of MOSFETs, this work applies AC BTI to the gates of P-MOS and N-MOS structures while simultaneously introducing laser irradiation to provide minority carriers simulating more realistic conditions. All measurements are performed at room temperature using a power device analyzer (Agilent B1505A, which is manufactured in Switzerland) on a probe station. During high-temperature degradation, the C-V and I-V measurements are conducted after the probe station cooled to room temperature. The C-V measurement is conducted at a frequency of 10 kHz. A standard calibration procedure was performed prior to C-V measurements at the measurement frequency of 10 kHz to account for and minimize parasitic effects. Measure–stress–measure (MSM) sequence, as shown in Figure 1c, is used to evaluate the C-V and I-V shift in devices under AC stress. In order to avoid altering defect charge states during I-V sweep, perform I-V scanning followed by C-V scanning before device degradation, and conduct C-V scanning before I-V measurement after device degradation. The AC BTI stress was performed for 24 h at a frequency of 5 kHz and at two temperatures (25 °C and 175 °C), using a square-wave gate bias alternating between +20 V and −10 V with a 50% duty cycle and rise/fall times of approximately 1000 V/μs, without noticeable voltage overshoot. During the AC degradation, a continuous-wave laser with a wavelength of 405 nm and a power of 150 mW is used to irradiate the gate and its surrounding SiC area of the MOS structure, enabling minority carriers generated at the SiC surface to effectively diffuse to the SiC/SiO₂ interface. The local heating effect from the laser is negligible. The 405 nm laser wavelength was selected because its photon energy (approximately 3.06 eV) is high enough to achieve controllable and sufficient minority carrier injection, thereby simulating alternating carrier conditions under the influence of alternating gate stress.

3. Results and Discussion

3.1. Effects of AC BTI on P-MOS Characteristics at Different Temperatures

As shown in Figure 2a, the P-MOS device shows a flat-band voltage shift of 0.3 V at room temperature, whereas under high-temperature stress, the C-V curve develops a distinct hump, but no significant flat-band voltage shift is observed. It is generally known that flat-band voltage drift is caused by effective charges in the oxide layer. However, such a hump, which has been previously reported [21,22], is attributed to slow-state traps (NITs or deep-level interface states). In this experiment, during ACBTI stress, electrons neutralize holes trapped in slow-state traps in the P-MOS, leading to the de-trapping of these deep-level defects. Consequently, during the subsequent C-V sweep (from depletion to accumulation), these deep-level defects are refilled with holes, resulting in the observed hump. The density of the slow-state traps (N_st) is calculated by the following expression [21,22]:

$$N_{\mathrm{st}} = ∆V_{\mathrm{hump}}{C}_{\mathrm{ox}}/\mathrm{q}$$

(1)

where $C_{\mathrm{ox}}$ is the capacitance of the gate oxide, $\mathrm{q}$ is the electronic charge, and $∆V_{\mathrm{hump}}$ is the voltage shift in the hump in the C-V measurement. Accordingly, the N_st in Figure 2b is estimated to be 4.92 × 10¹¹ cm⁻². It indicates that the shift in the C-V curves during AC BTI stress is primarily attributed to electron trapping at the interface.

Figure 3 shows the energy band diagrams at the SiC/SiO₂ interface under AC BTI stress with V_g = 20 V at different temperatures. At room temperature, electrons tend to be captured by relatively shallow near-interface traps (NITs), while the existing deep-level slow states, which were introduced during the fabrication process, remain stably filled [22]. However, when the temperature rises to 175 °C, the intrinsic carrier concentration increases, shifting the Fermi level closer to mid-gap. As a result, under inversion conditions, the degree of band bending is reduced, and a higher density of electrons accumulates near the interface. The elevated temperature also provides electrons with higher active energy, enabling them to neutralize holes trapped in deep-level slow states, leading to the de-trapping.

As shown in Figure 4, the density of interface states near the valence band in P-MOS devices is not significantly influenced by AC stress, either at room or high temperature. The D_it is calculated using the C-φ method via the following equation:

$$D_{it}={\displaystyle \frac{{{(C}_D+C_{it})}_{lf}-C_{\mathrm{D},\mathrm{t}\mathrm{h}\mathrm{e}\mathrm{o}\mathrm{r}\mathrm{y}}}{Sq}}$$

(2)

$$C_{\mathrm{D},\mathrm{t}\mathrm{h}\mathrm{e}\mathrm{o}\mathrm{r}\mathrm{y}}({\psi }_{\mathrm{S}})={\displaystyle \frac{S{qN}_D\left|exp\left(\frac{q{\psi }_{\mathrm{S}}}{kT}\right)-1\right|}{\sqrt{\frac{2kT{N}_D}{{\epsilon }_S}\left\{exp\left(\frac{q{\psi }_{\mathrm{S}}}{kT}\right)-\frac{q{\psi }_{\mathrm{S}}}{kT}-1\right\}}}}$$

(3)

where N_D is the donor concentration, ε_S is the dielectric constant of the semiconductor, k is the Boltzmann constant, T is the absolute temperature, and S is the electrode area. The results further confirm that the flat-band voltage shift under AC stress is primarily caused by electron trapping in defects.

Figure 5 presents the J_g-V_g characteristics of the P-MOS structures before and after AC BTI stress. The FN barrier height (Φ_FN) was determined from the slope of the linear region in the ln(J_g/E_ox²) versus 1/E_ox plot, following the established method [23]. It can be observed that after the degradation at room temperature, the Φ_FN increases noticeably, whereas after high-temperature aging, it slightly decreases. This can be explained by the temperature-dependent trapping of electrons at defects with different energy levels. It should be noted that the J_g-V_g measurements were performed after the C-V sweep. As already inferred from Figure 3, at room temperature, electrons are trapped mainly in shallow NITs in the P-MOS, leading to the rightward shift in the C-V curve. Consequently, during the subsequent J_g-V_g measurement, the trapped electrons in the near-interface oxide layer enhance band bending when a large negative bias is applied, thereby increasing the Φ_FN. In contrast, under high-temperature AC stress, the dominant effect is the de-trapping of slow states, which subsequently recapture holes during the C-V sweep. As a result, no significant flat-band voltage shift is observed, and the Φ_FN remains largely unchanged.

3.2. Effects of AC BTI on N-MOS Characteristics at Different Temperatures

Figure 6 shows that after AC stress, the N-MOS exhibits a clear rightward shift in the C-V curve under both room temperature and high temperature, indicating electron trapping by defects. Specifically, the measured ΔV_FB is 0.3 V at room temperature and 0.45 V at high temperature, corresponding to trapped electron densities of ΔN_RT = 1.14 × 10¹¹ cm⁻² and ΔN_HT = 1.7 × 10¹¹ cm⁻², respectively.

Figure 7 illustrates the effect of AC BTI on the interface state density (D_it) of the N-MOS structure. It can be observed that after the degradation at room temperature, the D_it near the conduction band edge increases to some extent, while it remains largely unchanged after high-temperature stress.

Figure 8 presents the J_g-V_g characteristics of the N-MOS structure before and after AC BTI stress. After degradation at room temperature, no significant change is observed in the Φ_FN, whereas a clear reduction is seen after high-temperature aging. This behavior can be explained as Figure 9, the rightward V_FB shift at room temperature is mainly caused by the increase in interface defects below the flat-band Fermi level that capture electrons, which has little influence on the FN tunneling barrier. In contrast, at high temperature, the V_FB shift is primarily due to electron trapping by NITs, which lowers the potential in the near-interface oxide layer and thereby reduces the Φ_FN. It is worth noting that the defect density observed in the P-MOS capacitor (4.92 × 10¹¹ cm⁻²) is significantly higher than that in the N-MOS structure (1.7 × 10¹¹ cm⁻²) at 175 °C. This difference likely originates from the fabrication process: the P-MOS capacitor is built on a p-well created by ion implantation into the epitaxial layer, which can introduce more deep-level defects near the SiC/SiO₂ interface compared to the N-MOS capacitor fabricated directly on the n-type epitaxial layer.

4. Conclusions

In summary, this work systematically investigates the interface degradation mechanisms in 4H-SiC P-MOS and N-MOS capacitor structures under laser-assisted AC BTI stress, which is designed to stimulate the effects of AC stress on the channel region and JFET region of MOSFETs, respectively. It is noteworthy that the flat-band voltage shifts positively in both P-MOS and N-MOS structures after the AC BTI at 25 °C, indicating that the AC stress predominantly leads to electron trapping, which ultimately results in the positive threshold voltage shift commonly reported in SiC MOSFETs under similar dynamic stress conditions. According to the results, the instability under AC BTI in SiC MOS structures is impacted by temperature-activated interactions with specific defect bands. AC stress at 25 °C predominantly affects shallower interface states or NITs. At 175 °C, by providing greater thermal energy, AC stress activates interactions with deeper, slower states, leading to complex trapping/de-trapping dynamics. Specifically, in P-MOS, the deep energy level donor-like traps are released by capturing electrons, while in N-MOS, it behaves as NITs capturing electrons. These findings provide fundamental insights into the defect kinetics that underlie threshold voltage instability in SiC power MOSFETs, and future work will incorporate more comprehensive characterization techniques, such as DLTS, to further validate the defect mechanisms of this study.