Simulation of the Effects of the Pillar Configurations on 1.2 kV 4H-SiC Superjunction DMOSFET

Abstract

4H-SiC has been studied and applied in power semiconductor devices due to its wider band gap and higher thermal conductivity than those of Si and hence has great potential for power devices operating at high powers and high temperatures. The introduction of the superjunction (SJ) structure for the power MOSFETs enables further reduction in the ON resistance while maintaining the breakdown voltage. In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the Atlas device simulator. The simulation results suggest the step-shape SJ DMOSFET can further reduce the specific ON resistance and the gate-drain capacitance while maintaining the breakdown voltage compared with the optimized conventional SJ DMOSFET. In addition, that the multi-pillar SJ DMOSFET demonstrates better performance than that of the optimized conventional SJ DMOSFET was also verified in this work.

1. Introduction

Silicon carbide (SiC) has been investigated and utilized for manufacturing power semiconductor devices in recent decades [1,2,3]. So far, SiC can replace silicon for some power semiconductor devices [3]. SiC has a wide band gap of 2.3–3.3 eV depending on its crystal structure. The most attractive SiC crystal structure is 4H-SiC because of its large band gap (about 3.2 eV). It exhibits about 10 times higher critical electric field and 3 times higher thermal conductivity than Si, making it promising for power devices operating at higher powers and higher temperatures. To improve the performance of 4H-SiC power MOSFETs, the so-called superjunction (SJ) structure has also been employed in the 4H-SiC power MOSFETs [4,5,6,7,8,9,10,11]. The SJ structure, in which the p-pillars were formed in the n-drift layer of the power MOSFETs, can reduce the ON resistance by increasing the doping of the drift layer without decreasing the breakdown voltage. This is because, if the charge balance condition can be attained between the p-pillars and the n-drift region, the depletion region will uniformly spread throughout the whole n-drift layer and will result in higher breakdown voltage than that of the n-drift layer without the p-pillars. In this work, we investigated the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the device simulator, Atlas (Silvaco Inc., Santa Clara, CA, USA). We proposed a novel “step-shape” p-pillar structure which is different from the step-doping profile in the p-pillars [4,6] and evaluated its performance compared with the optimized conventional SJ DMOSFET. The main difference between the proposed step-shape p-pillars and the step-doping p-pillars in [4,6] is that, for the step-shape p-pillars, the geometric shapes of the p-pillars are step-like with the same doping concentration within the p-pillars. However, the geometric shapes of the step-doping p-pillars in [4,6] are column-like, with different doping concentrations within the p-pillars. In addition, the number of the p-pillars, i.e., the multi-pillar configuration, will affect the device performance, as indicated in [7]. Therefore, the performance of the multi-pillar SJ DMOSFET was also examined in this work.

2. Device Structures and Simulation Approach

Figure 1a–d show the half-cell device structures of the four types of 1.2 kV 4H-SiC DMOSFETs examined in this work: Figure 1a is the conventional DMOSFET; Figure 1b is the conventional SJ DMOSFET; Figure 1c is the SJ DMOSFET with the “step-shape” p-pillar; and Figure 1d is the multi-pillar SJ DMOSFET. The complete unit cells of the four kinds of power DMOSFETs can be obtained by mirroring the half ones in Figure 1a–d at the left or right boundary. In our simulation, the band gap of 4H-SiC at room temperature is 3.23 eV and its relative dielectric constant is 9.7. For all four devices, the channel length is 0.5 μm and the gate oxide (SiO₂) thickness is 60 nm. The gate material is n⁺ polysilicon with a work function of 3.95 eV. The thickness and the doping concentration of the p-base region are 1.5 μm and 1.5 × 10¹⁷ cm⁻³, respectively. The thickness and the doping concentration of the n⁺ source are 0.3 μm and 1 × 10¹⁹ cm⁻³, respectively. The thickness of the n-drift layer is 10.5 μm. The doping concentration of the n-drift layer is 8 × 10¹⁵ cm⁻³ for the conventional DMOSFET. The values of the conventional DMOSFET structural parameters are similar to those of the fabricated 1.2 kV 4H-SiC inversion-mode DMOSFET [12]. For the other three SJ devices, the doping concentration of the n-drift layer varies, as shown in

Table 1. The doping concentrations of the n-drift layer and p-pillars for the four examined DMOSFETS *.

Structural Parameters	DMOSFET	SJ DMOSFET	Step-Shape SJ DMOSFET	Multi-Pillar SJ DMOSFET
n-drift doping (cm−3)	8 × 1015	2.8 × 1016	3.6 × 1016	5.6 × 1016
p-pillar doping (cm−3)	Not applicable	3.5 × 1016	4.5 × 1016	7 × 1016

* The channel length, gate oxide thickness, the thicknesses and doping concentrations of the p-base and n⁺ source, as well as the thickness of the n-drift layer, are the same as those described in Section 2 for all four devices.

, in order to attain the lower specific ON resistance with the breakdown voltage higher than 1400 V. In this work, we assumed the doping concentration of the p-pillar is 1.25 times that of the n-drift layer (or the doping concentration of the n-drift layer is 0.8 times that of the p-pillar). The purpose of this assumption is to facilitate achieving charge balance for the SJ devices. The charge balance condition here means

N_pillar ×  A_pillar = N_drift ×  A_drift,

(1)

where N_pillar and A_pillar are the doping concentration and the area of the p-pillar regions, respectively; and N_drift and A_drift are the doping concentration and the area of the remaining n-drift regions, respectively. Ideally, if N_pillar equals N_drift, then A_pillar will be equal to A_drift. However, since the p-pillars were formed in the n-drift layer, it is easier to implement the p-pillars with the doping concentration higher than that of the n-drift layer by ion implantation. Therefore, that the doping concentration of the p-pillar is slightly higher than that of the n-drift layer was assumed, and a similar approach can be found in [7]. Figure 1b shows the optimized conventional SJ DMOSFET when the p-pillar width is 3 μm, which occupies half the width of the n-drift layer. In Figure 1b, the optimized doping concentrations of the p-pillar and the n-drift layer are 3.5 × 10¹⁶ and 2.8 × 10¹⁶ cm⁻³, respectively, and the optimized p-pillar thickness is 8 μm, which also achieved the charge balance condition between the p-pillar and the n-drift region (regardless of the JFET region). The optimized doping concentration and thickness of the p-pillar for the conventional SJ DMOSFET were determined by the massive TCAD simulation experiments. In the simulation experiments, the variables are the doping concentration and the thickness of the p-pillar. The p-pillar doping concentration varies from 1 × 10¹⁶ to 9 × 10¹⁶ cm⁻³ with an increment of 5 × 10¹⁵ cm⁻³ and the p-pillar thickness varies from 1 to 9 μm with an increment of 1 μm. The optimized p-pillar doping concentrations for the step-shape SJ DMOSFET in Figure 1c and the multi-pillar SJ DMOSFET in Figure 1d were determined using a similar approach, except that the p-pillar thickness was fixed at 8 μm and the p-pillar area was fixed at 24 μm², as that of the optimized SJ DMOSFET (8 μm × 3 μm), for achieving the charge balance condition. Note that, since Figure 1b is a half unit cell, the actual p-pillar width is 6 μm. In Figure 1c, the doping concentrations of the p-pillar and the n-drift layer are 4.5 × 10¹⁶ and 3.6 × 10¹⁶ cm⁻³, respectively. The step height was tentatively set to 1 μm in Figure 1c, and the effect of step height variation will be investigated in future studies. In Figure 1d, the doping concentrations of the p-pillar and the n-drift layer are 7 × 10¹⁶ and 5.6 × 10¹⁶ cm⁻³, respectively. In the multi-pillar SJ configuration, the p-pillar width was assumed to be 2 μm, which is one-third of that of the conventional SJ DMOSFET in Figure 1b. The spacing between p-pillars in Figure 1d was consequently determined to be 1 μm, based on the p-base width, which is 8 μm. The effects of pillar width and spacing, together with the number of the p-pillars in the multi-pillar SJ configuration, will be simulated and analyzed further.

As for the simulation approach, the device simulator, Atlas, version 5.38.0.R, was used to evaluate the device performance. The anisotropic mobility model [13] was adopted to simulate the I-V characteristics. In this work, the y (vertical) direction is the <0001> direction, and the x (horizontal) direction is the <11$\overline{2}$0> direction. The mobility model considers the high-field velocity saturation due to the parallel electric field and the doping dependent mobility degradation. The incomplete ionization of the dopants was considered by the two-level incomplete ionization model [13]. The breakdown voltage is determined by the avalanche multiplication process and Selberherr’s impact ionization model was used [13]. Selberherr’s impact ionization model basically follows Chynoweth’s law, i.e., the impact ionization rates for electron and hole are determined by the magnitude of the electric field along the current direction [14]. Anisotropy of the impact ionization was not considered. The mesh size for the simulated devices varied from 0.01 to 0.05 μm for both x (horizontal) and y (vertical) directions. For the conventional DMOSFET, the number of mesh points is 26,831 and the mesh picture is shown in Figure 2.

3. Simulation Results and Discussion

Based on the aforementioned four device structures in Figure 1 and the simulation approach, the simulation results are presented and discussed in this section. Figure 3 shows the I_D–V_G curves of the four devices shown in Figure 1 under V_D = 10 V. The threshold voltages (V_T) of the four devices are 6.0 V. Figure 4 shows the I_D–V_D curves of the four devices shown in Figure 1 under V_G = 20 V. A significant reduction is observed in the specific ON resistance (R_on,sp) for the SJ devices compared with the conventional DMOSFET due to the increase in n-drift doping concentration. In addition, both the step-shape p-pillar SJ DMOSFET and the multi-pillar SJ DMOSFET demonstrated the lower specific ON resistance than that of the optimized conventional SJ DMOSFET, since the n-drift doping concentration can be further raised in these two devices without lessening the breakdown voltage. Figure 5 shows the breakdown characteristics of the four devices shown in Figure 1. The low reverse-bias current in Figure 5 is attributed to the low generation rate of carriers in the wide band gap semiconductor, like 4H-SiC. The breakdown voltage was set at 1.4 kV or above to ensure that the devices can be safely rated at 1.2 kV. The dc performance (e.g., R_on,sp and BV) for the four devices was shown in

Table 2. The dc and ac performance of the four examined DMOSFETS.

Performance	DMOSFET	SJ DMOSFET	Step-Shape SJ DMOSFET	Multi-Pillar SJ DMOSFET
VT (V)	6.0	6.0	6.0	6.0
Ron,sp 1 (mΩ-cm2)	19.2	8.60	6.95	6.49
BV (V)	1426	1495	1518	1540
dcFoM (MW/cm2)	106	260	332	365
Cgs,sp 2 (nF/cm2)	10.0	9.56	9.49	9.16
Cgd,sp 2 (pF/cm2)	181	158	143	137
Cds,sp 2 (pF/cm2)	372	404	590	518
Ciss,sp 2 (nF/cm2)	10.2	9.72	9.63	9.30
acFoM1 (ps)	3.48	1.36	0.99	0.89
acFoM2	56.4	61.5	67.3	67.9

¹ The specific ON resistance was obtained at V_G = 20 V. ² The specific capacitances were obtained at the frequency of 1 MHz under V_D = 1 kV and V_G = 0 V.

. The dcFoM in Table 2 is defined by the following:

dcFoM = BV²/R_on,sp.

(2)

A higher dcFoM indicates better dc performance, i.e., higher breakdown voltage and lower ON resistance. In Table 2, the SJ devices show 2–3 times higher dcFoM than that of the conventional DMOSFET, especially the step-shape SJ DMOSFET and the multi-pillar SJ DMOSFET. This is because the SJ devices have the lower specific ON resistance than that of the conventional DMOSFET, but their breakdown voltage is even slightly larger than that of the conventional DMOSFET. Figure 6a–d show the electric-field distributions at the breakdown of the four devices shown in Figure 1. The high-field area of the SJ devices is obviously larger than that of the conventional DMOSFET, which means high electric field does not concentrate locally for the SJ devices. Therefore, the SJ devices can maintain their breakdown voltage under increased n-drift doping concentrations. Although the high-field region of the conventional DMOSFET (Figure 6a) is not prominent, the punch-through effect between the source and the n-drift region is more pronounced in the conventional DMOSFET than those in the SJ devices. Consequently, the conventional DMOSFET generates the same current for the breakdown criterion under a lower electric field. Figure 7 shows the one-dimensional electric-field distributions at breakdown along the y-axis at x = 4 μm (which is the edge of the p-base region) of the four devices shown in Figure 1. A local peak of electric field appears for each device structure at y = 1.5 μm, corresponding to the junction depth of the p-base region. For the SJ devices, the electric field continues to spread over several micrometers instead of decreasing linearly, as in the conventional DMOSFET. Therefore, the SJ devices can keep the breakdown voltage under the raised n-drift doping concentrations. We also conducted a preliminary examination on the sensitivity of the breakdown voltage to the p-pillar doping concentration for the SJ devices with different p-pillar configurations, as shown in Figure 8. In Figure 8, the conventional SJ DMOSFET and the step-shape SJ DMOSFET exhibit lower breakdown-voltage sensitivity than that of the multi-pillar SJ DMOSFET. The underlying reason is still under investigation, but may be related to the higher p-pillar doping concentration of the multi-pillar SJ DMOSFET.

We also evaluated the ac performance by extracting the capacitances between the terminals of the simulated devices at the frequency of 1 MHz under V_D = 1 kV and V_G = 0 V. The ac performance (e.g., C_gs,sp and C_gd,sp) for the four devices is also shown in Table 2. The simulated values of the conventional DMOSFET in Table 2 and the measurement data of the inversion-mode DMOSFETs in Table I of [12] are of the same order of magnitude, which confirms the validity of the simulation data. The SJ devices have lower C_gs,sp and C_gd,sp than those of the conventional DMOSFET. Since the p-pillars can be regarded as the lightly doped p-base extension, the p-pillars will reduce the capacitance between the gate and the p-base, which is a component of C_gs,sp. However, the gate oxide capacitance still dominates C_gs,sp, and the reduction in C_gs,sp by the p-pillars is less than 10%. The reduction of C_gd,sp by the p-pillars is attributed to the reduction in the n-drift region under the gate. When the p-pillar edge is closer to the p-base edge, as shown in Figure 1b–d, the n-drift depletion region controlled by the gate decreases; consequently, C_gd,sp decreases. The C_gd,sp of the multi-pillar SJ DMOSFET is approximately 75% of that of the conventional DMOSFET. However, the SJ devices have higher C_ds,sp than that of the conventional DMOSFET because the area of the p–n junctions in the SJ devices are larger than that in the conventional DMOSFET. Note that the specific input capacitance C_iss,sp in Table 2 is defined by C_gs,sp plus C_gd,sp. The acFoM1 and acFoM2 in Table 2 are defined by the following:

acFoM1 = R_on,sp × C_gd,sp,

(3)

acFoM2 = C_iss,sp/C_gd,sp.

(4)

A lower acFoM1 indicates better switching capacity, i.e., higher switching speed and lower switching power losses. As shown in Table 2, the acFoM1 of the SJ devices is only 0.25–0.4 times that of the conventional DMOSFET. This is because both the R_on,sp and the C_gd,sp of the SJ devices are lower than those of the conventional DMOSFET. Another metric used to evaluate the switching performance is acFoM2. The C_gd,sp results in the Miller effect, which brings the so-called “Miller plateau” in the Q_g–V_g curve and reduces the switching efficiency. Therefore, a higher acFoM2 indicates better switching capacity. In Table 2, the SJ devices show higher acFoM2 than the conventional DMOSFET, mainly due to their lower C_gd,sps. In summary, since the step-shape p-pillar SJ DMOSFET and the multi-pillar SJ DMOSFET have lower C_gd,sp and R_on,sp than those of the conventional DMOSFET and the optimized conventional SJ DMOSFET, the step-shape p-pillar SJ DMOSFET and the multi-pillar SJ DMOSFET showed the superior acFoM1 and acFoM2 than those of the other two devices.

4. Conclusions

In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ DMOSFET with different configurations of pillars by the TCAD simulation. The simulation results indicate the SJ devices can have better dc and ac performance than that of the conventional DMOSFET. In addition, both the step-shape p-pillar SJ DMOSFET and the multi-pillar SJ DMOSFET can have better dc and ac performance than that of the optimized conventional SJ DMOSFET. The step-shape p-pillar SJ DMOSFET structure has a lower p-pillar aspect ratio than that of the multi-pillar SJ DMOSFET. Therefore, considering the difficulty of the manufacturing process, the step-shape p-pillar SJ DMOSFET structure is considerably promising according to our simulation results. A more comprehensive investigation with a detailed analysis of the sensitivities of the dc and ac performance to the doping concentrations of the SJ devices with different p-pillar configurations will be work for the future.