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Special Issue "Special Issue on the 2017 International Image Sensor Workshop (IISW)"

A special issue of Sensors (ISSN 1424-8220).

Deadline for manuscript submissions: closed (31 October 2017)

Special Issue Editors

Guest Editor
Mr. Vladimir Koifman

Analog Value Ltd., 32 Burla St. Rishon Lezion, 75736 Israel
Website | E-Mail
Interests: CCD and CMOS image sensors; pinned photodiodes; pixel; 1/f and RTS noise; global shutter and rolling shutter sensors; high dynamic range imaging; time-of-flight imagers; X-ray imagers, astronomy and space imaging; photon counting; novel image sensor concepts
Co-Guest Editor
Prof. Dr. Shoji Kawahito

Imaging Devices Laboratory, Research Institute of Electronics, Shizuoka University, 3-5-1, Johoku, Naka-ku, Hamamatsu, 432-8011, Japan
Website | E-Mail
Co-Guest Editor
Dr. Daniel Van Blerkom

Forza Silicon Corp., 2947 Bradley Street, Suite 130, Pasadena, CA 91107, USA
Website | E-Mail
Interests: CMOS image sensors; infrared ROICs; X-ray sensors; low noise readouts; image sensor ADC architecture; stacked sensors; global shutter sensors; pixel design; pixel process/device simulation; HDR sensor design
Co-Guest Editor
Dr. Guy Meynants

ams Sensors, Coveliersstraat 15, 2600 Antwerpen, Belgium
Website | E-Mail
Interests: CMOS image sensors; global shutter pixels; high frame rate image sensors; read noise, large area imagers; high dynamic range imaging; ADCs for image sensors; miniature camera modules

Special Issue Information

Dear Colleagues,

The International Image Sensor Workshop (IISW) is the world’s largest technology forum, fully devoted to image sensor design and research. The workshop papers span across a wide range of imaging devices: From small pixel mobile image sensors to large format X-ray and astronomy imagers, from sensors for high end scientific applications to low-cost mass produced stacked sensors, from time-resolving and photon counting imagers to rad-hard sensors for space applications.

This Special Issue provides the expanded versions of 20 invited papers from the workshop covering novel and innovative approaches in image sensors, as well as state-of-the-art incremental improvements on known techniques.

Other paper submissions are strictly limited to IISW 2017 participants.

Mr. Vladimir Koifman
Prof. Dr. Shoji Kawahito
Dr. Guy Meynants
Dr. Daniel Van Blerkom
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Sensors is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • CCD
  • CMOS Sensor
  • CMOS Pixel
  • Photodiode
  • 1/f Noise
  • Flicker Noise
  • RTN
  • RTS Noise
  • HDR
  • WDR
  • Dark current
  • Conversion gain
  • Photon counting
  • Single photon detection
  • BSI
  • FSI
  • Global shutter
  • Rolling shutter

Published Papers (18 papers)

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Research

Open AccessArticle Multiband Imaging CMOS Image Sensor with Multi-Storied Photodiode Structure
Sensors 2018, 18(6), 1688; https://doi.org/10.3390/s18061688
Received: 24 February 2018 / Revised: 21 May 2018 / Accepted: 22 May 2018 / Published: 24 May 2018
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Abstract
We developed a multiband imaging CMOS image sensor (CIS) with a multi-storied photodiode structure, which comprises two photodiode (PD) arrays that capture two different images, visible red, green, and blue (RGB) and near infrared (NIR) images at the same time. The sensor enables
[...] Read more.
We developed a multiband imaging CMOS image sensor (CIS) with a multi-storied photodiode structure, which comprises two photodiode (PD) arrays that capture two different images, visible red, green, and blue (RGB) and near infrared (NIR) images at the same time. The sensor enables us to capture a wide variety of multiband images which is not limited to conventional visible RGB images taken with a Bayer filter or to invisible NIR images. Its wiring layers between two PD arrays can have an optically optimized effect by modifying its material and thickness on the bottom PD array. The incident light angle on the bottom PD depends on the thickness and structure of the wiring and bonding layer, and the structure can act as an optical filter. Its wide-range sensitivity and optimized optical filtering structure enable us to create the images of specific bands of light waves in addition to visible RGB images without designated pixels for IR among same pixel arrays without additional optical components. Our sensor will push the envelope of capturing a wide variety of multiband images. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs
Sensors 2018, 18(5), 1313; https://doi.org/10.3390/s18051313
Received: 19 December 2017 / Revised: 15 March 2018 / Accepted: 9 April 2018 / Published: 24 April 2018
PDF Full-text (4763 KB) | HTML Full-text | XML Full-text
Abstract
We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with
[...] Read more.
We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle High Dynamic Range Imaging at the Quantum Limit with Single Photon Avalanche Diode-Based Image Sensors
Sensors 2018, 18(4), 1166; https://doi.org/10.3390/s18041166
Received: 1 November 2017 / Revised: 4 April 2018 / Accepted: 5 April 2018 / Published: 11 April 2018
PDF Full-text (26646 KB) | HTML Full-text | XML Full-text
Abstract
This paper examines methods to best exploit the High Dynamic Range (HDR) of the single photon avalanche diode (SPAD) in a high fill-factor HDR photon counting pixel that is scalable to megapixel arrays. The proposed method combines multi-exposure HDR with temporal oversampling in-pixel.
[...] Read more.
This paper examines methods to best exploit the High Dynamic Range (HDR) of the single photon avalanche diode (SPAD) in a high fill-factor HDR photon counting pixel that is scalable to megapixel arrays. The proposed method combines multi-exposure HDR with temporal oversampling in-pixel. We present a silicon demonstration IC with 96 × 40 array of 8.25 µm pitch 66% fill-factor SPAD-based pixels achieving >100 dB dynamic range with 3 back-to-back exposures (short, mid, long). Each pixel sums 15 bit-planes or binary field images internally to constitute one frame providing 3.75× data compression, hence the 1k frames per second (FPS) output off-chip represents 45,000 individual field images per second on chip. Two future projections of this work are described: scaling SPAD-based image sensors to HDR 1 MPixel formats and shrinking the pixel pitch to 1–3 µm. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors
Sensors 2018, 18(3), 707; https://doi.org/10.3390/s18030707
Received: 21 November 2017 / Revised: 28 January 2018 / Accepted: 13 February 2018 / Published: 27 February 2018
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Abstract
This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling
[...] Read more.
This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Second Generation Small Pixel Technology Using Hybrid Bond Stacking
Sensors 2018, 18(2), 667; https://doi.org/10.3390/s18020667
Received: 2 November 2017 / Revised: 26 January 2018 / Accepted: 13 February 2018 / Published: 24 February 2018
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Abstract
In this work, OmniVision’s second generation (Gen2) of small-pixel BSI stacking technologies is reviewed. The key features of this technology are hybrid-bond stacking, deeper back-side, deep-trench isolation, new back-side composite metal-oxide grid, and improved gate oxide quality. This Gen2 technology achieves state-of-the-art low-light
[...] Read more.
In this work, OmniVision’s second generation (Gen2) of small-pixel BSI stacking technologies is reviewed. The key features of this technology are hybrid-bond stacking, deeper back-side, deep-trench isolation, new back-side composite metal-oxide grid, and improved gate oxide quality. This Gen2 technology achieves state-of-the-art low-light image-sensor performance for 1.1, 1.0, and 0.9 µm pixel products. Additional improvements on this technology include less than 100 ppm white-pixel process and a high near-infrared (NIR) QE technology. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout
Sensors 2018, 18(2), 584; https://doi.org/10.3390/s18020584
Received: 10 November 2017 / Revised: 8 February 2018 / Accepted: 11 February 2018 / Published: 14 February 2018
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Abstract
In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light
[...] Read more.
In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light conditions and logarithmic response in high light conditions. The charge transfer readout efficiently suppresses the reset (KTC) noise by using true correlated double sampling (CDS) in low light conditions. In high light conditions, thanks to charge domain logarithmic compression, it has been demonstrated that 3000 electrons should be enough to cover a 120 dB dynamic range with a mobile phone camera-like signal-to-noise ratio (SNR) over the whole dynamic range. This low electron count permits the use of ultra-small floating diffusion capacitance (sub-fF) without charge overflow. The resulting large conversion gain permits a single photon detection capability with a wide dynamic range without a complex sensor/system design. A first prototype sensor with 320 × 240 pixels has been implemented to validate this charge domain logarithmic pixel concept and modeling. The first experimental results validate the logarithmic charge compression theory and the low readout noise due to the charge-transfer-based readout. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology
Sensors 2018, 18(2), 449; https://doi.org/10.3390/s18020449
Received: 31 October 2017 / Revised: 24 January 2018 / Accepted: 28 January 2018 / Published: 3 February 2018
Cited by 1 | PDF Full-text (21222 KB) | HTML Full-text | XML Full-text
Abstract
Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and
[...] Read more.
Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel
Sensors 2018, 18(2), 349; https://doi.org/10.3390/s18020349
Received: 31 October 2017 / Revised: 22 January 2018 / Accepted: 23 January 2018 / Published: 25 January 2018
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Abstract
We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at
[...] Read more.
We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e/s at 60 °C. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Single-Photon Tracking for High-Speed Vision
Sensors 2018, 18(2), 323; https://doi.org/10.3390/s18020323
Received: 1 November 2017 / Revised: 8 January 2018 / Accepted: 19 January 2018 / Published: 23 January 2018
PDF Full-text (3878 KB) | HTML Full-text | XML Full-text
Abstract
Quanta Imager Sensors provide photon detections at high frame rates, with negligible read-out noise, making them ideal for high-speed optical tracking. At the basic level of bit-planes or binary maps of photon detections, objects may present limited detail. However, through motion estimation and
[...] Read more.
Quanta Imager Sensors provide photon detections at high frame rates, with negligible read-out noise, making them ideal for high-speed optical tracking. At the basic level of bit-planes or binary maps of photon detections, objects may present limited detail. However, through motion estimation and spatial reassignment of photon detections, the objects can be reconstructed with minimal motion artefacts. We here present the first demonstration of high-speed two-dimensional (2D) tracking and reconstruction of rigid, planar objects with a Quanta Image Sensor, including a demonstration of depth-resolved tracking. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessFeature PaperArticle A Real-Time Ultraviolet Radiation Imaging System Using an Organic Photoconductive Image Sensor
Sensors 2018, 18(1), 314; https://doi.org/10.3390/s18010314
Received: 31 October 2017 / Revised: 12 January 2018 / Accepted: 18 January 2018 / Published: 22 January 2018
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Abstract
We have developed a real time ultraviolet (UV) imaging system that can visualize both invisible UV light and a visible (VIS) background scene in an outdoor environment. As a UV/VIS image sensor, an organic photoconductive film (OPF) imager is employed. The OPF has
[...] Read more.
We have developed a real time ultraviolet (UV) imaging system that can visualize both invisible UV light and a visible (VIS) background scene in an outdoor environment. As a UV/VIS image sensor, an organic photoconductive film (OPF) imager is employed. The OPF has an intrinsically higher sensitivity in the UV wavelength region than those of conventional consumer Complementary Metal Oxide Semiconductor (CMOS) image sensors (CIS) or Charge Coupled Devices (CCD). As particular examples, imaging of hydrogen flame and of corona discharge is demonstrated. UV images overlapped on background scenes are simply made by on-board background subtraction. The system is capable of imaging weaker UV signals by four orders of magnitude than that of VIS background. It is applicable not only to future hydrogen supply stations but also to other UV/VIS monitor systems requiring UV sensitivity under strong visible radiation environment such as power supply substations. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle A 750 K Photocharge Linear Full Well in a 3.2 μm HDR Pixel with Complementary Carrier Collection
Sensors 2018, 18(1), 305; https://doi.org/10.3390/s18010305
Received: 1 November 2017 / Revised: 12 January 2018 / Accepted: 14 January 2018 / Published: 20 January 2018
PDF Full-text (5392 KB) | HTML Full-text | XML Full-text
Abstract
Mainly driven by automotive applications, there is an increasing interest in image sensors combining a high dynamic range (HDR) and immunity to the flicker issue. The native HDR pixel concept based on a parallel electron and hole collection for, respectively, a low signal
[...] Read more.
Mainly driven by automotive applications, there is an increasing interest in image sensors combining a high dynamic range (HDR) and immunity to the flicker issue. The native HDR pixel concept based on a parallel electron and hole collection for, respectively, a low signal level and a high signal level is particularly well-suited for this performance challenge. The theoretical performance of this pixel is modeled and compared to alternative HDR pixel architectures. This concept is proven with the fabrication of a 3.2 μm pixel in a back-side illuminated (BSI) process including capacitive deep trench isolation (CDTI). The electron-based image uses a standard 4T architecture with a pinned diode and provides state-of-the-art low-light performance, which is not altered by the pixel modifications introduced for the hole collection. The hole-based image reaches 750 kh+ linear storage capability thanks to a 73 fF CDTI capacitor. Both images are taken from the same integration window, so the HDR reconstruction is not only immune to the flicker issue but also to motion artifacts. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process
Sensors 2018, 18(1), 203; https://doi.org/10.3390/s18010203
Received: 10 November 2017 / Revised: 22 December 2017 / Accepted: 7 January 2018 / Published: 12 January 2018
PDF Full-text (3131 KB) | HTML Full-text | XML Full-text
Abstract
To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm
[...] Read more.
To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke. Readout noise under the highest pixel gain condition is 1 e with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias
Sensors 2018, 18(1), 118; https://doi.org/10.3390/s18010118
Received: 30 October 2017 / Revised: 28 December 2017 / Accepted: 28 December 2017 / Published: 3 January 2018
Cited by 2 | PDF Full-text (7346 KB) | HTML Full-text | XML Full-text
Abstract
A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes
[...] Read more.
A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors
Sensors 2017, 17(12), 2867; https://doi.org/10.3390/s17122867
Received: 31 October 2017 / Revised: 23 November 2017 / Accepted: 8 December 2017 / Published: 10 December 2017
Cited by 2 | PDF Full-text (5441 KB) | HTML Full-text | XML Full-text
Abstract
Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras
[...] Read more.
Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III–V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10−6 A/cm2 at −2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Development of Gentle Slope Light Guide Structure in a 3.4 μm Pixel Pitch Global Shutter CMOS Image Sensor with Multiple Accumulation Shutter Technology
Sensors 2017, 17(12), 2860; https://doi.org/10.3390/s17122860
Received: 31 October 2017 / Revised: 4 December 2017 / Accepted: 6 December 2017 / Published: 9 December 2017
PDF Full-text (7381 KB) | HTML Full-text | XML Full-text
Abstract
CMOS image sensors (CISs) with global shutter (GS) function are strongly required in order to avoid image degradation. However, CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is
[...] Read more.
CMOS image sensors (CISs) with global shutter (GS) function are strongly required in order to avoid image degradation. However, CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is remarkable in small pixel pitch. The newly developed 3.4 µm pitch GS CIS solves this problem by using multiple accumulation shutter technology and the gentle slope light guide structure. As a result, the developed GS pixel achieves 1.8 e temporal noise and 16,200 e full well capacity with charge domain memory in 120 fps operation. The sensitivity and parasitic light sensitivity are 28,000 e/lx·s and −89 dB, respectively. Moreover, the incident light angle dependence of sensitivity and parasitic light sensitivity are improved by the gentle slope light guide structure. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Recent Enhancements to Interline and Electron Multiplying CCD Image Sensors
Sensors 2017, 17(12), 2841; https://doi.org/10.3390/s17122841
Received: 26 September 2017 / Revised: 28 November 2017 / Accepted: 30 November 2017 / Published: 7 December 2017
Cited by 3 | PDF Full-text (5907 KB) | HTML Full-text | XML Full-text
Abstract
This paper describes recent process modifications made to enhance the performance of interline and electron-multiplying charge-coupled-device (EMCCD) image sensors. By use of MeV ion implantation, quantum efficiency in the NIR region of the spectrum was increased by 2×, and image smear was reduced
[...] Read more.
This paper describes recent process modifications made to enhance the performance of interline and electron-multiplying charge-coupled-device (EMCCD) image sensors. By use of MeV ion implantation, quantum efficiency in the NIR region of the spectrum was increased by 2×, and image smear was reduced by 6 dB. By reducing the depth of the shallow photodiode (PD) implants, the photodiode-to-vertical-charge-coupled-device (VCCD) transfer gate voltage required for no-lag operation was reduced by 3 V, and the electronic shutter voltage was reduced by 9 V. The thinner, surface pinning layer also resulted in a reduction of smear by 4 dB in the blue portion of the visible spectrum. For EMCCDs, gain aging was eliminated by providing an oxide-only dielectric under its multiplication phase, while retaining the oxide-nitride-oxide (ONO) gate dielectrics elsewhere in the device. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel
Sensors 2017, 17(12), 2816; https://doi.org/10.3390/s17122816
Received: 16 October 2017 / Revised: 28 November 2017 / Accepted: 28 November 2017 / Published: 5 December 2017
Cited by 3 | PDF Full-text (8714 KB) | HTML Full-text | XML Full-text
Abstract
A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of
[...] Read more.
A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e/s at 60 °C, an ultra-low read noise of 0.90 e·rms, a high full well capacity (FWC) of 4100 e, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Statistical Analysis of the Random Telegraph Noise in a 1.1 μm Pixel, 8.3 MP CMOS Image Sensor Using On-Chip Time Constant Extraction Method
Sensors 2017, 17(12), 2704; https://doi.org/10.3390/s17122704
Received: 18 October 2017 / Revised: 20 November 2017 / Accepted: 21 November 2017 / Published: 23 November 2017
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Abstract
A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source.
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A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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