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Open AccessArticle

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs

Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan
Sony LSI Design, Japan, 4-16-1 Okada, Atsugi-shi, Kanagawa 243-0021, Japan
Graduate School of Information Science and Technology, The University of Tokyo, 7 Chome-3-1 Hongo, Bunkyō, Tokyo 113-8654, Japan
Author to whom correspondence should be addressed.
Sensors 2018, 18(5), 1313;
Received: 19 December 2017 / Revised: 15 March 2018 / Accepted: 9 April 2018 / Published: 24 April 2018
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning. View Full-Text
Keywords: vision chip; high-speed image sensor; detection; tracking vision chip; high-speed image sensor; detection; tracking
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Nose, A.; Yamazaki, T.; Katayama, H.; Uehara, S.; Kobayashi, M.; Shida, S.; Odahara, M.; Takamiya, K.; Matsumoto, S.; Miyashita, L.; Watanabe, Y.; Izawa, T.; Muramatsu, Y.; Nitta, Y.; Ishikawa, M. Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs . Sensors 2018, 18, 1313.

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