Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †
by
Atsushi Nose 1,*, Tomohiro Yamazaki 1, Hironobu Katayama 1, Shuji Uehara 1, Masatsugu Kobayashi 1, Sayaka Shida 1, Masaki Odahara 2, Kenichi Takamiya 2, Shizunori Matsumoto 2, Leo Miyashita 3, Yoshihiro Watanabe 3, Takashi Izawa 1, Yoshinori Muramatsu 1, Yoshikazu Nitta 1 and Masatoshi Ishikawa 3
Atsushi Nose 1,*, Tomohiro Yamazaki 1, Hironobu Katayama 1, Shuji Uehara 1, Masatsugu Kobayashi 1, Sayaka Shida 1, Masaki Odahara 2, Kenichi Takamiya 2, Shizunori Matsumoto 2, Leo Miyashita 3, Yoshihiro Watanabe 3, Takashi Izawa 1, Yoshinori Muramatsu 1, Yoshikazu Nitta 1 and Masatoshi Ishikawa 3
1
Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan
2
Sony LSI Design, Japan, 4-16-1 Okada, Atsugi-shi, Kanagawa 243-0021, Japan
3
Graduate School of Information Science and Technology, The University of Tokyo, 7 Chome-3-1 Hongo, Bunkyō, Tokyo 113-8654, Japan
*
Author to whom correspondence should be addressed.
Sensors 2018, 18(5), 1313; https://doi.org/10.3390/s18051313
Received: 19 December 2017 / Revised: 15 March 2018 / Accepted: 9 April 2018 / Published: 24 April 2018
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.
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Keywords:
vision chip; high-speed image sensor; detection; tracking
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MDPI and ACS Style
Nose, A.; Yamazaki, T.; Katayama, H.; Uehara, S.; Kobayashi, M.; Shida, S.; Odahara, M.; Takamiya, K.; Matsumoto, S.; Miyashita, L.; Watanabe, Y.; Izawa, T.; Muramatsu, Y.; Nitta, Y.; Ishikawa, M. Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †. Sensors 2018, 18, 1313.
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