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Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 December 2025) | Viewed by 13616

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Special Issue Editors

Dr. Ygor Aguiar

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Guest Editor

CERN, CH-1211 Genève, Switzerland
Interests: soft errors; radiation-hardening-by-design (RHBD) techniques; prediction methods; Monte Carlo; dosimetry

Dr. Corinna Martinella

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Guest Editor

Advanced Power Semiconductor Laboratory (APS), ETH Zurich, Physikstrasse 3, 8092 Zürich, Switzerland
Interests: wide-bandgap power devices; basic mechanisms; single-event effects; total ionizing dose; displacement damage

Special Issue Information

Dear Colleagues,

Single-event effects (SEEs), caused by high-energy particles, pose significant challenges to the reliability and safety of electronic systems in both space and terrestrial environments. Traditionally, research in SEEs has focused on soft errors such as single-event upsets (SEUs), single-event transients (SETs), and single-event functional interrupts (SEFIs). However, with the scaling of semiconductor technologies, the use of wide-bandgap semiconductors, and the increasing complexity of applications—from space exploration to autonomous cars—other critical effects, such as single-event latch-up (SEL), single-event burnout (SEB), single-event gate rupture (SEGR), and single-event leakage current (SELC), are becoming equally significant and require novel approaches in modeling, prediction, testing, and mitigation.

This Special Issue aims to gather high-quality submissions that address both fundamental and advanced topics in SEE research, with a focus on comprehensive methodologies for modeling, prediction, testing, and hardening. SEEs will be explored across a wide range of applications and technology platforms, from traditional space systems to emerging ground-level environments, like autonomous vehicles, high-performance computing, medical devices, and particle accelerators. Additionally, this Special Issue will highlight new approaches in alternative SEE testing methodologies—using tools like lasers and high-energy heavy ions—and discuss the challenges in the radiation monitoring and dosimetry needs involved in ensuring accurate SEE characterization and rate prediction. The topics of interest include, but are not limited to, the following:

Modeling and prediction of single-event effects:
- Mechanisms of soft errors (SEUs, SETs, and SEFIs);
- Mechanisms of destructive effects (SEL, SEB, SEGR, and SELC);
- Simulation and prediction tools.
Experimental characterization of single-event effects in the following:
- Advanced technologies (FinFETs, GAA, etc.);
- Mixed-signal, RF, power, and digital circuits (such as radar circuits, RISC-V processors, and custom SoC designs).
Testing methodologies:
- Alternative SEE testing methods, such as laser testing, mixed-field, and high-energy heavy-ion irradiation;
- Innovations in SEE test facilities, including the calibration of ion beams and the related radiation monitoring as well as dosimetry.
Radiation-hardening-by-design (RHBD) techniques:
- Novel layout-level hardening techniques;
- Novel circuit-level hardening techniques;
- Novel system-level hardening techniques;
- Design automation tools for integrating radiation-hardened techniques into advanced ICs and system-on-chip designs.
Radiation-hardening-by-process (RHBP) techniques:
- Innovations in device-level hardening by using materials and novel architectures that exhibit natural SEE resilience.
Single-event effects in disruptive technologies like quantum computing, silicon photonics, and AI-driven applications.

Dr. Ygor Aguiar
Dr. Corinna Martinella
Guest Editors

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Keywords

single-event effects
soft errors
SEE modeling and prediction
wide-bandgap semiconductors
radiation testing
hardening techniques

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Published Papers (10 papers)

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Research

42 pages, 2537 KB

Open AccessArticle

UPSET: A Comprehensive Probabilistic Single Event Transient Analysis Flow for VLSI Circuits Using Static Timing Analysis

by Christos Georgakidis, Dimitris Valiantzas, Nikolaos Chatzivangelis, Marko Andjelkovic, Christos Sotiriou and Milos Krstic

Electronics 2026, 15(4), 818; https://doi.org/10.3390/electronics15040818 - 13 Feb 2026

Viewed by 274

Abstract

The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single-Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel “Electrical Masking Window” (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. The experimental results over some featured benchmarks demonstrate a speedup of more than 25,000× compared with SPICE while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaining scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF, DEF, LIB, or SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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22 pages, 1274 KB

Open AccessArticle

A Predictive Approach for the Early Reliability Assessment in Embedded Systems Using Code and Trace Embeddings via Machine Learning

by Felipe Restrepo-Calle, Enrique Abma Romero and Sergio Cuenca-Asensi

Electronics 2026, 15(3), 543; https://doi.org/10.3390/electronics15030543 - 27 Jan 2026

Viewed by 378

Abstract

Radiation-induced transient faults pose a growing challenge for safety-critical embedded systems, yet traditional radiation testing and large-scale statistical fault injection (SFI) remain costly and impractical during early design stages. This paper presents a predictive approach for early reliability assessment that replaces handcrafted feature engineering with automatically learned vector representations of source code and execution traces. We derive multiple embeddings for traces and source code, and use them as inputs to a family of regression models, including ensemble methods and linear baselines, to build predictive models for reliability. Experimental evaluation shows that embedding-based models outperform prior approaches, reducing the mean absolute percentage error (MAPE) from 6.24% to 2.14% for correct executions (unACE), from 20.95% to 10.40% for Hangs, and from 49.09% to 37.69% for silent data corruptions (SDC) after excluding benchmarks with SDC below 1%. These results show that source code and trace embeddings can serve as effective estimators for expensive fault injection campaigns, enabling early-stage reliability assessment in radiation-exposed embedded systems without requiring any manual feature engineering. This capability provides a practical foundation for supporting design-space exploration during early development phases. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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14 pages, 3212 KB

Open AccessArticle

A Radiation-Hardened 4-Bit Flash ADC with Compact Fault-Tolerant Logic for SEU Mitigation

by Naveed and Jeff Dix

Electronics 2025, 14(21), 4176; https://doi.org/10.3390/electronics14214176 - 26 Oct 2025

Viewed by 818

Abstract

This paper presents a radiation-hardened 4-bit flash analog-to-digital converter (ADC) implemented in a 22 nm fully depleted silicon-on-insulator (FD-SOI) process for high-reliability applications in radiation environments. To improve single-event upsets (SEU) tolerance, the design introduces a compact fault-tolerant logic scheme based on Dual Modular Redundancy (DMR), offering reliability comparable to Triple Modular Redundancy (TMR) while using two storage nodes instead of three, and a simple XOR-based check in place of a majority voter. A distributed sampling architecture mitigates SEU vulnerabilities in the input path, while thin-oxide devices are used in analog-critical circuits to enhance total ionizing dose (TID) resilience. Post-layout simulations demonstrate SEU detection within 200 ps and correction within ~600 ps. The ADC achieves an active area of 0.089 mm², power consumption below 30 µW, and provides a scalable solution for radiation-tolerant data acquisition in aerospace and other high-reliability systems. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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30 pages, 2873 KB

Open AccessArticle

Quasar—A Process Variability-Aware Radiation Robustness Evaluation Tool

by Bernardo Borges Sandoval, Lucas Yuki Imamura, Ana Flávia D. Reis, Leonardo Heitich Brendler, Rafael B. Schvittz and Cristina Meinhardt

Electronics 2025, 14(15), 3131; https://doi.org/10.3390/electronics14153131 - 6 Aug 2025

Viewed by 974

Abstract

This work presents Quasar, an open-source tool developed to boost the characterization of how variability effects impact radiation sensitivity in digital circuits. Quasar receives a SPICE netlist as input and automatically determines robustness metrics, such as the critical Linear Energy Transfer, for every configuration in which a Single Event Transient fault can propagate an error. The tool can handle ranges from small basic cells to median multi-gate circuits in a few seconds, speeding up the traditional fault injection mechanism based on a large number of electrical simulations. The tool’s workflow explores logical masking to reduce the design space exploration, i.e., reducing the necessary number of electrical simulations, as well as regression methods to speed up variability evaluations. Quasar already has shown the potential to provide useful results, and a prototype has also been published. This work presents a more polished and complete version of the tool, one that optimizes the tool’s search process and allows not only for a fast evaluation of the radiation robustness of a circuit, but also for an analysis of how fabrication process metrics impact this robustness, such as Work Function Fluctuation. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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22 pages, 10412 KB

Open AccessArticle

Design and Evaluation of Radiation-Tolerant 2:1 CMOS Multiplexers in 32 nm Technology Node: Transistor-Level Mitigation Strategies and Performance Trade-Offs

by Ana Flávia D. Reis, Bernardo B. Sandoval, Cristina Meinhardt and Rafael B. Schvittz

Electronics 2025, 14(15), 3010; https://doi.org/10.3390/electronics14153010 - 28 Jul 2025

Cited by 1 | Viewed by 1264

Abstract

In advanced Complementary Metal-Oxide-Semiconductor (CMOS) technologies, where diminished feature sizes amplify radiation-induced soft errors, the optimization of fault-tolerant circuit designs requires detailed transistor-level analysis of reliability–performance trade-offs. As a fundamental building block in digital systems and critical data paths, the 2:1 multiplexer, widely used in data-path routing, clock networks, and reconfigurable systems, provides a critical benchmark for assessing radiation-hardened design methodologies. In this context, this work aims to analyze the power consumption, area overhead, and delay of 2:1 multiplexer designs under transient fault conditions, employing the CMOS and Differential Cascode Voltage Switch Logic (DCVSL) logic styles and mitigation strategies. Electrical simulations were conducted using 32 nm high-performance predictive technology, evaluating both the original circuit versions and modified variants incorporating three mitigation strategies: transistor sizing, D-Cells, and C-Elements. Key metrics, including power consumption, delay, area, and radiation robustness, were analyzed. The C-Element and transistor sizing techniques ensure satisfactory robustness for all the circuits analyzed, with a significant impact on delay, power consumption, and area. Although the D-Cell technique alone provides significant improvements, it is not enough to achieve adequate levels of robustness. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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11 pages, 2109 KB

Open AccessArticle

SEU Cross-Section Estimation Using ECORCE TCAD Tool

by Cleiton M. Marques, Alain Michez, Frédéric Wrobel, Ygor Q. Aguiar, Frédéric Saigné, Luigi Dilillo and Rubén García Alía

Electronics 2025, 14(15), 2997; https://doi.org/10.3390/electronics14152997 - 27 Jul 2025

Viewed by 827

Abstract

This work introduces an innovative approach for estimating the Single-Event Upset (SEU) cross-sections in Static Random-Access Memory (SRAM) devices, addressing challenges related to limited technological information and the complexity of Technology Computer-Aided Design (TCAD) simulations. The proposed methodology is designed to be accessible even to users without in-depth TCAD expertise, enabling a streamlined yet accurate SEU cross-section estimation. Using simplified mixed-modeling (TCAD-based 2D modeling with circuit-level SPICE simulations), this approach significantly reduces computational efforts while maintaining good correlation with experimental data. Furthermore, this study identifies key parameters that influence TCAD modeling accuracy and proposes strategies for approximating unknown parameters, enhancing the reliability of SEU cross-section predictions. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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33 pages, 1298 KB

Open AccessArticle

Exploring Circuit-Level Techniques for Soft Error Mitigation in 7 nm FinFET Full Adders

by Rafael Oliveira, Rafael B. Schvittz and Cristina Meinhardt

Electronics 2025, 14(15), 2937; https://doi.org/10.3390/electronics14152937 - 23 Jul 2025

Viewed by 1625

Abstract

This work investigates the effects of radiation on FinFET-based full adders, which are crucial components of arithmetic units, particularly in aerospace and space applications. While FinFETs offer significant advantages, they remain susceptible to single-event transients (SETs) induced by radiation, which can cause computational errors. We assess three circuit-level mitigation techniques against SETs in FinFET adders: decoupling cells (DCELLs), transistor sizing (TS), and a combined approach incorporating both methods. Our results demonstrate that the most sensitive nodes and critical vectors in the adders vary depending on the mitigation strategy, underscoring their impact on overall radiation resilience. By analyzing these techniques alongside critical node evaluation, we identify their advantages and limitations, providing insights to enhance the robustness of FinFET-based processors in radiation-prone environments. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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16 pages, 4344 KB

Open AccessArticle

Ion-Induced Charge and Single-Event Burnout in Silicon Power UMOSFETs

by Saulo G. Alberton, Vitor A. P. Aguiar, Nemitala Added, Alexis C. Vilas-Bôas, Marcilei A. Guazzelli, Jeffery Wyss, Luca Silvestrin, Serena Mattiazzo, Matheus S. Pereira, Saulo Finco, Alessandro Paccagnella and Nilberto H. Medina

Electronics 2025, 14(11), 2288; https://doi.org/10.3390/electronics14112288 - 4 Jun 2025

Viewed by 1032

Abstract

The U-shaped Metal-Oxide-Semiconductor Field-Effect Transistor (UMOS or trench FET) is one of the most widely used semiconductor power devices worldwide, increasingly replacing the traditional vertical double-diffused MOSFET (DMOSFET) in various applications due to its superior electrical performance. However, a detailed experimental comparison of ion-induced Single-Event Burnout (SEB) in similarly rated silicon (Si) UMOS and DMOS devices remains lacking. This study presents a comprehensive experimental comparison of ion-induced charge collection mechanisms and SEB susceptibility in similarly rated Si UMOS and DMOS devices. Charge collection mechanisms due to alpha particles from ²⁴¹Am radiation source are analyzed, and SEB cross sections induced by heavy ions from particle accelerators are directly compared. The implications of the unique gate structure of Si UMOSFETs on their reliability in harsh radiation environments are discussed based on technology computer-aided design (TCAD) simulations. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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21 pages, 4988 KB

Open AccessArticle

Analysis of the SEU Tolerance of an FPGA-Based Time-to-Digital Converter Using Emulation-Based Fault Injection

by Roza Teklehaimanot Siecha, Getachew Alemu, Jeffrey Prinzie and Paul Leroux

Electronics 2025, 14(11), 2176; https://doi.org/10.3390/electronics14112176 - 27 May 2025

Cited by 2 | Viewed by 2336

Abstract

In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources of performance degradation even in terrestrial areas. Hence, the need to test and mitigate the effects of SEUs on FPGA-based TDCs is crucial to ensure that the design achieves reliable performance under critical conditions. The TMR SEM IP provides real-time fault injection, and dynamic SEU monitoring and correction in safety critical conditions without intervening with the functionality of the system, unlike traditional fault injection methods. This paper presents a scalable and fast fault emulation framework that tests the effects of SEUs on the configuration memory of a 5.7 ps-resolution TDC implemented on ZedBoard. The experimental results demonstrate that the standard deviation in mean bin width is 2.4964 ps for the golden TDC, but a 0.8% degradation in the deviation is observed when 3 million SEUs are injected, which corresponds to a 0.02 ps increment. Moreover, as the number of SEUs increases, the degradation in the RMS integral non-linearity (INL) of the TDC also increases, which shows 0.04 LSB (6.8%) and 0.05 LSB (8.8%) increments for 1 million and 3 million SEUs injected, respectively. The RMS differential non-linearity (DNL) of the faulty TDC with 3 million SEUs injected shows a 0.035 LSB (0.8%) increase compared to the golden TDC. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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11 pages, 11863 KB

Open AccessArticle

Single-Event Upset Characterization of a Shift Register in 16 nm FinFET Technology

by Federico D’Aniello, Marcello Tettamanti, Syed Adeel Ali Shah, Serena Mattiazzo, Stefano Bonaldo, Valeria Vadalà and Andrea Baschirotto

Electronics 2025, 14(7), 1421; https://doi.org/10.3390/electronics14071421 - 31 Mar 2025

Cited by 1 | Viewed by 1948

Abstract

Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸

N i

and ²⁸

S i

, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs. Full article

(This article belongs to the Special Issue Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening)

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