Special Issue "Nanoscale CMOS Technologies"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics and Optoelectronics".

Deadline for manuscript submissions: 31 January 2020.

Special Issue Editors

Prof. Dr. Kamal El-Sankary
E-Mail Website
Guest Editor
Electrical & Computer Engineering Department, Dalhousie University, C367 Halifax, NS, Canada
Interests: microelectronics, analog, mixed-signal, digital and RF integrated circuits design in nanoscale CMOS technologies, and embedded systems design
Dr. Tejinder Sandhu
E-Mail Website
Guest Editor
Mixed signal design engineer at Synopsys Inc. Toronto, Canada
Interests: analog and digital circuit design; low power integrated circuits; switched capacitor circuits; analog to digital converters; delay locked loops; phase locked loops

Special Issue Information

Dear Colleagues,

CMOS technology will continue to expand its dominance for the next decade or so despite challenges resulting from the continuous reduction of transistor dimensions. Several promising alternatives to CMOS technology are being actively developed, but CMOS will remain at the forefront of integrated circuit design in the near future owing to process maturity, low manufacturing costs, high speed, and low power consumption.

Continuous transistor scaling comes with many trade-offs: On one hand, it reduces gate delay, which allows transistors to switch faster. Alternatively, size scaling necessitates reduced supply voltages, which severely limits the allowable voltage dynamic range, thereby degrading the signal to noise ratio. Therefore, it is increasingly difficult to design high-speed, low-noise integrated circuits while maintaining the operational reliability of complex ultra-low power devices.  

The scope of this Special Issue is to focus and report on the development of emerging techniques to overcome these challenges.

Specifically, the research portfolio for this issue includes research on low-power RF, mixed-signal and analog CMOS design of circuits and systems, and power-efficient integrated circuit design for communications, sensing and biomedical applications. The topics of primary research include but are not limited to:

  • Recent developments in nanoscale circuits and systems including mixed-signal circuits, RFICs and analog building blocks;
  • Circuit design for emerging 2.5D or 3D IC CMOS technologies;
  • Sub-threshold digital and analog circuits;
  • Process and mismatch insensitive integrated circuit design;
  • Signal processing and digital assisted methods for high performances circuits;
  • Biologically-Inspired system and circuit design;
  • Optimization methods for energy-efficient integrated circuits

Prof. Kamal El-Sankary
Dr. Tejinder Sandhu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (5 papers)

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Research

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Open AccessArticle
High-CMRR Low-Noise Fully Integrated Front-End for EEG Acquisition Systems
Electronics 2019, 8(10), 1157; https://doi.org/10.3390/electronics8101157 - 12 Oct 2019
Abstract
We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR [...] Read more.
We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 . Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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Open AccessArticle
K-Band Low Phase Noise VCO Based on Q-Boosted Switched Inductor
Electronics 2019, 8(10), 1132; https://doi.org/10.3390/electronics8101132 - 08 Oct 2019
Abstract
In this article, the development of the K-band low phase noise voltage-controlled oscillator (VCO) based on Q-boosted switched inductor is presented. Compared with the conventional switched inductor, the eddy current will be decreased using a 2-turn secondary coil, and then the dissipated power [...] Read more.
In this article, the development of the K-band low phase noise voltage-controlled oscillator (VCO) based on Q-boosted switched inductor is presented. Compared with the conventional switched inductor, the eddy current will be decreased using a 2-turn secondary coil, and then the dissipated power from the switch on-resistance will also be decreased, leading to a boosted inductor Q at switch ON-state. The equivalent inductance, quality factor, and self-resonance frequency at switch ON/OFF states are analyzed and derived. For comparison, K-band VCOs have been designed and fabricated in a 130nm BiCMOS process with the Q-boosted and conventional switched inductors. Measured results show that the phase noise has been typically improved by 2–5dB at 100 kHz and 1 MHz offset at switch ON-state, using the Q-boosted switched inductor. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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Open AccessArticle
A PVT-Robust Super-Regenerative Receiver with Background Frequency Calibration and Concurrent Quenching Waveform
Electronics 2019, 8(10), 1119; https://doi.org/10.3390/electronics8101119 - 04 Oct 2019
Abstract
A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center [...] Read more.
A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
Open AccessArticle
Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology
Electronics 2019, 8(9), 954; https://doi.org/10.3390/electronics8090954 - 29 Aug 2019
Abstract
This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power [...] Read more.
This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power dissipation, noise, and distortion. The design is implemented using a 0.13 μm CMOS technology, and to the best of our knowledge, it possesses the best (post-layout simulation) figure of merit (FOM) among the works presented in literature. The FOM is defined as the product of gain and third-order intercept divided the product between average noise figure and power dissipation. Finally, the core of the mixer takes only 31 µm by 28 µm and it draws a current of 1 mA from the 1.5 V DC supply. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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Review

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Open AccessReview
Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview
Electronics 2019, 8(5), 477; https://doi.org/10.3390/electronics8050477 - 29 Apr 2019
Cited by 1
Abstract
Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the [...] Read more.
Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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