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Open AccessArticle

System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks

by Shiming Song * and Yu Sui
1812 Seville Way, San Jose, CA 95131, USA
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(11), 1233; https://doi.org/10.3390/electronics8111233
Received: 30 September 2019 / Revised: 21 October 2019 / Accepted: 24 October 2019 / Published: 28 October 2019
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
This decade has witnessed wide use of data-driven systems, from multimedia to scientific computing, and in each case quality data movement infrastructure is required, many with SerDes as a cornerstone. On the one hand, HPC and machine learning cloud infrastructure carry exabytes of data in a year through the backplanes of data centers. On the other hand, the growing need for edge computing in the IoT places a tight envelope on the energy per bits. In this survey, we give a system level overview of the common design challenges in implementing SerDes solutions under different scenarios and propose simulation methods benefiting from advanced machine learning techniques. Preliminary results with the proposed simulation platform are demonstrated and analyzed through machine learning based design methodologies. View Full-Text
Keywords: SerDes; CMOS; mixed-signal; analog; equalization; CDR; machine learning SerDes; CMOS; mixed-signal; analog; equalization; CDR; machine learning
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Song, S.; Sui, Y. System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks. Electronics 2019, 8, 1233.

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