Hardware-Efficient Stochastic Computing-Based Neural Networks with SNN-Isomorphic LIF Activation

Abstract

Recent advances in artificial intelligence have made power efficiency a primary objective in system design. In this context, stochastic computing (SC), which processes probabilistic bitstreams using simple logic, and spiking neural networks (SNNs), a neuromorphic paradigm, have gained prominence as alternative approaches. This study proposes a Stochastic Computing Neural Network (SC-NN) framework that minimizes the intrinsic errors of stochastic computing and leverages the isomorphism between one-count operations on bitstreams and spike-rate computations in spiking neural networks, yielding improvements in accuracy and hardware efficiency. In contrast to earlier studies that utilized independent random number sequences of 10 bits or higher, our study employed a practically implementable 8-bit linear feedback shift Register (LFSR)-based pseudo-random bitstream. Using 4 taps and 255 seeds improves the realism of the hardware. Despite the inherent accuracy ceiling of pseudo-random sequences, the proposed method achieves higher accuracy. Applied to an 8-bit SC-based neural network accelerator, the proposed design improves accuracy by 35% over a conventional FSM baseline, while reducing power and area by 43.8% and 17.2%, respectively, and decreasing delay by 5.5%. These improvements translate to a 2.3× enhancement in the Figure of Merit (FoM), which was further verified through physical layout and FPGA results. Overall, this work introduces a new paradigm that enables simultaneous gains in accuracy and efficiency for low-power AI by suppressing the error sources and embedding the structural similarity between SNNs and SC into the design.

1. Introduction

As deep-learning inference becomes ubiquitous, even in edge and Internet of Things (IoT) settings, stochastic computing (SC) [1,2], renowned for its area and power efficiency, has regained attention. Conventional binary-integer arithmetic requires complex circuits, such as adders and multipliers [3], which significantly impact power consumption and area. In contrast, SC represents values as probabilistic bitstreams, enabling basic operations such as multiplication and addition to be performed with simple logic gates [4,5].

The strengths of stochastic computing include achieving high parallelism with modest hardware resources [6], exhibiting a high degree of fault tolerance, and reducing memory bandwidth requirements, which in turn improves overall system efficiency [7]. However, a finite bitstream length introduces error in probability estimation and stochastic computing is sensitive to stochastic sequence correlation (SSC), including correlation between inputs and weights, which can degrade accuracy [8,9]. Within the neuromorphic paradigm, spiking neural networks (SNNs) offer strong potential for low-power operation owing to their sparse, event-driven dynamics [10,11]. They are also capable of performing approximate statistical computation through spike rate integration over time [12]. Nevertheless, SNNs continue to encounter notable challenges, including the difficulty of model conversion and training, overhead from discrete time steps, and loss of numerical precision [13,14]. These complementary characteristics suggest that combining the two paradigms judiciously could alleviate the accuracy–resource trade-off in a new way. Although many Stochastic Computing-based Neural Network (SC-NN) studies have attempted to enhance accuracy through longer bitstreams or more complex state machines, these strategies frequently compromise the fundamental goal of low-power operation [15,16,17,18]. To address these limitations, the main contributions of this paper are as follows:

• Preprocessing Layer: We address the main error source in bipolar stochastic multiplication by adding a preprocessing layer that removes the “Dead Zone”. This reduces stochastic error by over 113.7×.
• LIF Activation: Building on the observation that SNNs are computationally isomorphic to SC, we propose a leaky integrate-and-fire (LIF) model for SC-NNs. This method enhances accuracy and improves the figure of merit (FoM) by more than 2.3×.
• On-chip SNG: We replaced an independent random bitstream with a pseudo-random bitstream produced by an implementable 8-bit linear feedback shift register (LFSR) and realized the design on actual SoC hardware.

Collectively, by introducing the minimal preprocessing and a dynamic activation mechanism required for practical SC deployment, we establish a new design paradigm that unifies SC and SNN within a single layer. The remainder of this paper is organized as follows. Section 2 reviews prior work on SC, outlines the operating principles of SNNs, and critically examines the limitations of existing SC-NN approaches. Section 3 presents the proposed SC-NN architecture. Section 4 presents the experimental results. Section 5 concludes with a discussion of the contributions and their implications.

2. Background

2.1. Stochastic Computing

SC represents real numbers as probabilistic bitstreams and performs arithmetic using only simple combinations of logic gates [19]. In a bitstream of length N, the frequency of ones encodes the magnitude of the value. When the stream is sufficiently long and the samples are mutually independent, the expected value converges to the target value. LFSRs serve as the standard for digital pseudo-random number generation where high-precision SNGs are critical [20,21,22], and recent studies have expanded this field by introducing single-device-based sources to achieve high-precision stochastic number generation [23]. A comparator (CMP) or weighted-bit generator (WBG) is then used to encode a fixed-point value y as the frequency of ones in the bitstream [24]. Increasing the stream length N reduces the approximation variance, but increases cycle count, power, and area, necessitating an appropriate balance.

SC offers two encoding schemes: unipolar and bipolar. For the unipolar case where x ranges from 0 to 1, the encoding uses $P(bit=1)=x$, so the probability equals the value itself. For the bipolar case where x ranges from $-1$ to 1, the encoding is $P(bit=1)=(x+1)/2$, and decoding recovers $x=2P(bit=1)-1$[2,3]. For example, with the 8-bit stream “01101101”, the count of ones is 5. Unipolar decoding yields $5/8$. Bipolar decoding yields $(5/8)\times 2-1=2/8$.

Regardless of bitstream types, SSC is critical to accuracy [25]. A shared LFSR or any strong inter-stream correlation reduces computational performance and typically requires multiple SNGs to break the correlation [26]. However, the number of seed combinations for an 8-bit LFSR is only 256, which is smaller than the minimum typical count of inputs and weights/biases in a neural network. In such cases, one can vary the bitstreams by adjusting the LFSR tap positions. To achieve the maximum period $2^N-1$ for a register of width N, the characteristic polynomial over GF(2) must be primitive and therefore irreducible. Specifically,

• Irreducibility: the polynomial must not factor into a product of lower-degree polynomials.
• Primitivity: the polynomial must generate all nonzero elements of the corresponding finite field.

Additionally, under limited bit-width, correlation can be further reduced by techniques such as inserting NOT/XNOR gating within or around the LFSR path, or by mixing CMP and WBG encoders to diversify the generated bitstreams.

2.2. Activation Function Using Stochastic Computing

A key determinant of an artificial neural network’s performance is the activation function, which imparts nonlinearity. When SC relies on gate-level linear operations [27], errors arise not only from the bitstream representation but also from the Taylor-series approximation used for nonlinear functions. Polynomial terms require extra stochastic number generators (SNGs) or cycles to control SSC, increasing energy use [4]. Consequently, there are inherent limits to accurately approximating nonlinear activations such as hyperbolic tangent (tanh) and sigmoid and ReLU using gate-only logic.

To address this issue, the SC approach using a finite-state machine (FSM) was first introduced [28]. Given an input stream of length N, the state increases by $+1$ when the input bit is ‘1’ and decreases by $-1$ when the input bit is ‘0’. A saturating up/down counter evolves the state. When the state crosses preset boundaries [29,30], the circuit outputs 0 or 1, thereby approximating the target function. A larger M improves fidelity but increases latency and resource usage. Previous studies have demonstrated that this FSM approach facilitates useful nonlinear approximations with relatively small area and power requirements [31,32,33].

To overcome the limitations of a one-dimensional FSM, a two-dimensional FSM approach has been proposed as shown in Figure 1 [34]. An SNG converts a real-valued input X into a bitstream with probability $P_X$. Along with calibration control stream with probability $P_K$, this pair drives an M × N FSM that evolves according to the transition rules. Here, parameter K functions as a calibration term, dependent on the target function, that effectively shifts its input axis. State transitions are controlled by the four configurations induced by X and K. According to the transition rules, once a state is asserted, the corresponding weight bitstream $P_W$ is driven to the output Y. For each state, the associated weight bitstream $P_W$ is emitted as output Y, and the accumulated count is subsequently reported by a counter. Unlike a 1-D FSM, the 2-D FSM offers universality for function implementation in principle [24]. However, it requires comparatively greater hardware resources.

Figure 1. Block diagram of the 2-D FSM-based architecture.

2.3. Spiking Neural Network

Artificial neural networks (ANNs) are computing systems inspired by the operating principles of biological neurons in the human brain [35]. Whereas a conventional ANN propagates continuous real-valued activations and applies nonlinear functions to them, an SNN models the biological spiking mechanism and encodes inputs as discrete spikes. Figure 2 illustrates the fundamental operation of an SNN, demonstrating how a pre-synaptic neuron transmits the synaptic weight (W) to a post-synaptic neuron via the frequency of discrete spike signals. Unlike ANNs, a neuron in an SNN emits a spike only when its membrane potential reaches a prescribed threshold voltage $V_{th}$. This communication scheme resembles how the brain conveys information via action potentials. Therefore, SNNs align more closely with neural processes than conventional networks [36,37]. Representative neuron models in SNNs include the leaky integrate and fire (LIF) model and the integrate and fire (IF) model [38,39]. As shown in the timing diagram of Figure 2, the pre-synaptic neuron generates spikes at specific instants. With each incoming spike in the internal state, the membrane potential increases in a stepwise manner. Between spikes, the membrane potential decays due to leakage. When the accumulated input raises the membrane potential above a threshold $V_{th}$, the neuron fires a spike and subsequently resets its potential [40,41]. This mechanism allows SNNs to approximate biological neural computation more effectively than ANNs.

Figure 2. Operating principle of the LIF neuron: input spikes (black), $V_i$ (blue) and output fire (red).

2.4. Stochastic Computing Neural Network

Research on neural networks implemented with stochastic computing has continued to advance [42,43,44]. For each input-weight stream pair, unipolar encoding uses an AND gate and bipolar encoding uses an XNOR gate, and a MUX combines the resulting streams to realize the weighted sum. Neuron outputs are then produced using either gate- or FSM-based activations [45]. Training is generally performed in the real-valued domain, and the learned weights and biases are mapped to hardware. More recently, methods that perform learning directly in the SC domain have been proposed, which effectively mitigate quantization error introduced during mapping [46,47].

SC-NNs offer several advantages. Their simple circuits reduce area, routing complexity, and power consumption [48]. They are also robust to errors [49], since bit-level faults have limited global impact. Furthermore, stream-based processing reduces memory traffic and bandwidth, lowering power [50]. In contrast, achieving higher accuracy often requires longer streams, which increase cycle count, power, and area. In addition, stream correlation degrades accuracy, frequently necessitating multiple SNGs that further increase cost. Attempts to improve accuracy by lengthening streams or adding SNGs also raise circuit complexity, eroding some of SC’s intrinsic simplicity and efficiency. Nevertheless, SC-NNs remain attractive as they achieve substantial power savings while requiring low hardware resources.

3. Proposed SC-NN Architecture

This study proposes an SC-based neural network with a sequential pipeline composed of a Preprocessing Layer, Fully Connected (FC) Layers, and an Output Layer as shown in Figure 3. The FC widths are 784-100-200-10. To reduce computation and energy, FC1 is shrunk to 100. To compensate for any accuracy loss, FC2 is expanded to 200.

Figure 3. Proposed SC-NN block diagram.

All weights, biases, and input data are quantized to signed 8-bit form. From a deployment perspective, we select 8 bits as the default bit-width by considering the minimum transfer granularity of practical systems. Using 10 or 12 bits introduces packing and unpacking logic in the storage and transfer stages [51]. This increases control complexity, the number of clock cycles, area, and power. For example, moving to 10 bits increases memory bandwidth by roughly 25%. Area and power increase by approximately 25% each. The cycle count becomes 4× that of the 8-bit case, so the figure of merit (Power × Delay × Area) worsens by about 6.25×. Therefore, we adopt 8 bits. In an 8-bit LFSR, we select four out of sixteen available tap sets and vary the seed to generate 1024 distinct sequences, which can be shared across the network [24].

3.1. Proposed Preprocessing Layer

In bipolar SC, multiplication can be achieved using a single XNOR gate, which is advantageous in terms of ultra-low power consumption [9]. Consider real numbers X and Y, each taking values from $-1$ to 1, that are linearly mapped to 8-bit two’s complement integers from −128 to 127. Let the bipolar bitstreams corresponding to X and Y be denoted by $P_X$ and $P_Y$; the XNOR-gate error is analyzed as follows. When multiplying completely independent bitstreams $P_X$ and $P_Y$, the Mean Squared Error (MSE) remains substantially consistent even when the absolute values of X and Y are near zero, as illustrated in Figure 4a. However, when pseudo-random bitstreams are generated using an 8-bit LFSR and the XNOR MSE is evaluated, the result shown in Figure 4b is obtained. Based on this, the relative error analysis yields the MSRE distribution shown in Figure 4c. It can be observed that the error increases when the absolute values of X and Y are near zero, and surges significantly when both values are close to zero.

Figure 4. Comparison of error for bipolar SC multiplication. (a) Theoretical MSE. Simulated (b) MSE and (c) MSRE.

Accordingly, this work defines the region in which the XNOR-gate error sharply increases as a Dead Zone. The ratio of this width is denoted as $\tau$, resulting in a total Dead Zone width of 2$\tau$. To eliminate this dead zone, we propose a preprocessing layer as illustrated in Figure 5, which prunes signed 8-bit input values falling within the absolute value of $\tau$, thereby bypassing computation for these inputs. It is crucial to note that the threshold parameter $\tau$ is applied uniformly across all network layers. This is because the Dead Zone arises from the inherent mathematical error characteristics of bipolar SC multiplication, rather than the specific data distribution of a layer. If $\tau$ varies across layers, specifically if a preceding layer has a smaller $\tau$ than a subsequent layer, valid information preserved upstream is discarded downstream, causing information loss. Conversely, a larger upstream $\tau$ followed by a smaller downstream $\tau$ allows noise to propagate, which may be amplified. Consequently, the preprocessing layer counts the number of valid inputs and forwards this statistic as a scalar value to the fully connected layer so that it can be used by the activation for dynamic normalization. Furthermore, to address the Dead Zone along the weight axis, the network is trained to prune weights within the range [$-\tau$,$\tau$]. This effectively eliminates the cross-shaped data distribution near zero, where XNOR gate errors are most prevalent.

Figure 5. Schematic of the preprocessing layer architecture implementing valid signal detector for Dead Zone elimination.

Figure 6 shows the results. The overall average error, represented by the blue line, is reduced to the level of the purple line by removing near-zero weights. With the additional application of the preprocessing layer, the error is further reduced to the level of the green line. Quantitatively, the error is 113.7× lower than the overall and 10.7× lower than using near-zero weight removal alone. Prior SC-NN preprocessing typically stopped at converting real values to bitstreams via SNGs [45]. In contrast, the proposed preprocessing eliminates terms concentrated in error-prone regions and propagates the count of valid terms, serving as the key differentiator.

Figure 6. Average error comparison between the overall, near-zero weights pruning, and the proposed preprocessing method.

3.2. Activation Using Leaky-Integrate Fire Model

Implementations of activation functions with stochastic computing have typically employed FSM [42]. However, the number of states is fixed, and the resulting slope remains steep and fixed, as illustrated in Figure 7. Exploiting the isomorphism between computation on the population of ones in stochastic bitstreams and computation on spike rates in SNNs, we implement a tanh activation in the form of a LIF unit. In the proposed LIF design, the circuit counts the ones and subtracts a baseline determined by the number of valid data items. The LIF also performs per-clock leakage on the accumulated state, enabling an SC-compatible, clock synchronous tanh. Consequently, the design reduces power and area while improving accuracy. The proposed LIF neuron operates as shown in Algorithm 1. For each input vector $X_t$, the unit counts the total number of ones, denoted as $B_t$. A key feature of this model is its adaptive reference value, which is calculated based on the number of valid data points within the current input $X_t$.

Algorithm 1 Proposed LIF Neuron

// ${\mathbf{X}}_{\mathbf{t}}$ is the input bit vector of each column.    // $Y_t$ is Fired value, either 1 or 0.    // $V_i$ is membrane potential of the neuron. LIF Update (${\mathbf{X}}_{\mathbf{t}}$, $Y_t$)    $B_t\leftarrow \mathrm{The}\mathrm{number}\mathrm{of}1\mathrm{s}\mathrm{in}{\mathbf{X}}_{\mathbf{t}}$    $\alpha \leftarrow \mathrm{Input}\mathrm{scaling}$                              // $\alpha$ is leakage    ${Integrate}_t\leftarrow B_t-\left(\mathrm{Number}\mathrm{of}\mathrm{valid}\mathrm{data}\mathrm{in}{\mathbf{X}}_{\mathbf{t}}\right)/2$    $V_i\left(t\right)\leftarrow V_i(t-1)+{Integrate}_t\ast \alpha$    If $V_i\left(t\right)>V_{th}$ then                     // $V_{th}$ is threshold value       $Y_t\leftarrow 1$    else       $Y_t\leftarrow 0$

Figure 7. Comparison of transfer characteristics for the tanh activation between FSM and proposed LIF implementation.

This context-dependent reference is subtracted from $B_t$ to generate an effective input. Instead of applying a traditional leak to the stored potential, our model scales this effective input by a factor $\alpha$ before integration. This input-scaling mechanism functions analogously to leakage by regulating the neuron’s overall excitability and sensitivity to incoming signals. Specifically, $\alpha$ is a configurable parameter that mathematically dictates the slope of the tanh activation function. Unlike FSM-based approaches that are limited to a fixed slope, our design allows for precise slope modulation. Setting $\alpha =1$ results in a sensitivity effectively half that of the conventional FSM, offering a wider dynamic range. Consequently, this parameter provides the mathematical flexibility to implement different activation slopes by simply adjusting the $\alpha$ value as required by various network models. When the membrane potential reaches or exceeds a threshold value $V_{th}$, the unit emits $Y_t=1$; otherwise, it outputs $Y_t=0$. Unlike standard models, the neuron does not perform a hard reset after firing, allowing it to retain a memory of past inputs. This design allows the firing rate to be precisely regulated. While $V_{th}$ is primarily established at half the valid data count to maintain zero-centered symmetry, it can be dynamically adjusted to control output sparsity, mirroring the firing threshold mechanism in biological SNNs. Moreover, this synchronous design with its adaptive baseline and tunable parameters improves accuracy while reducing power and area, as it eliminates complex asynchronous control logic and simplifies state register requirements.

The mathematical process by which the above operation approximates the tanh function is as follows. At each clock, the number of ones $B_t$ in a column follows a binomial distribution with effective input count n and single-bit success probability p. Here, p is the probability that the XNOR result equals 1 at that clock, as given in (1). When the baseline for valid data is set to half of the incoming data in FC1, to 100 in FC2, and to 50 in FC3, the probability that the output bit is 1 is given in (2), where F denotes the CDF of the binomial distribution. Using the central limit theorem (CLT), the continuous approximation in (3) is obtained. In the bipolar setting, $t=2p-1$ and $\varphi$ denotes the standard normal CDF. Thus, the expected output equals the tail probability of a binomial CDF, which forms an S-shaped curve symmetric about $p=1/2$. This curve is well approximated by the logistic function $\sigma$ and, via an affine mapping, by tanh, as given in (4). These results indicate that both the LIF dynamics and the FSM mechanism can serve as tanh activation.

$$\begin{array}{c}B\sim \mathrm{Bin}(n,p),Pr(B=b)=\left({\displaystyle \genfrac{}{}{0pt}{}{n}{b}}\right)p^b{(1-p)}^{n-b}\end{array}$$

(1)

$$\begin{array}{c}Pr(Y=1|p)=Pr\left(B>{\displaystyle \frac{n}{2}}\right)=1-F\left({\displaystyle \frac{n}{2}};n,p\right)\end{array}$$

(2)

$$\begin{array}{c}Pr\left(B>{\displaystyle \frac{n}{2}}\right)\approx \Phi \left(\sqrt{n}(2p-1)\right)=\Phi \left(\sqrt{nt}\right)\end{array}$$

(3)

$$\begin{array}{c}\varphi \left(x\right)\approx \sigma \left(\alpha x\right),y\left(t\right)\approx tanh\left(\kappa t\right)\end{array}$$

(4)

4. Result Analysis

The proposed SC-NN was evaluated on the MNIST dataset with 28 × 28 inputs using 10,000 test samples. All inputs, weights, and biases were represented as signed 8-bit integers and converted into bitstreams using pseudo-random number sequences generated by LFSRs. To evaluate the robustness of the proposed architecture against stochastic fluctuations and sequence correlations, we performed Monte Carlo simulations across multiple LFSR configurations. Specifically, we utilized 4 distinct primitive polynomial taps and 255 initial seeds, resulting in a total of 1020 unique pseudo-random instances. The accuracy metrics reported in this section represent the mean values derived from these extensive trials. The observed standard deviation of the accuracy was minimal, ranging from 0.05% to 0.25%, confirming that the performance gains are stable and not dependent on favorable random number sequences. The design was synthesized using Synopsys Design Compiler in 65 nm CMOS technology under typical conditions (1.0 V, 25 °C) with a target clock period of 10 ns (100 MHz) to analyze the power, delay, and area overhead of a single module. The layout for each activation module in Fully Connected Layer 1 was implemented via Place and Route (PnR) using Cadence Innovus with commercial 65 nm standard cells. Additionally, FPGA performance was validated using Xilinx Vivado 2023.1.

To assess the contribution of the proposed approach, we compared accuracy with and without the preprocessing layer, and additionally evaluated the method against conventional FSM-based activation and the proposed LIF-based activation; the results are summarized in Table 1. The baseline that does not compensate for XNOR error yields an accuracy of 65.5%. Pruning weights with $\left|\omega \right|<0.1$ without modifying the input values increases accuracy by 1.9% points. Notably, applying the proposed preprocessing layer alone to prune inputs within the same range, while retaining all weights, achieves an accuracy of 77.4%, demonstrating that eliminating input-dependent errors is highly effective even without weight constraints. When the preprocessing layer is added to eliminate the cross-shaped input values responsible for XNOR gate errors, the accuracy improves to 82% and 88.4% when using FSM and LIF activation functions, respectively. Compared to the FSM model, the LIF model can more precisely control the effective sensitivity of the tanh-like response, resulting in higher accuracy. With $\alpha =1$, the LIF model achieves an accuracy that is 6.4% points higher than the FSM model. The impact of varying the Dead Zone ratio $\tau$ on accuracy is shown at the bottom of Table 1. Larger $\tau$ degrades accuracy by reducing the amount of usable data, whereas smaller $\tau$ increases stochastic-computing error by retaining near-zero values. These results indicate that $\tau =0.1$ provides the most favorable trade-off. Overall, the proposed 8-bit SC-NN implemented with pseudo-random hardware demonstrates higher accuracy than previously reported 10-bit hardware implementations [50,52].

Table 1. Comparison of SC-NN accuracy on average for the MNIST dataset with FSM-based and proposed LIF-based activation.

SC-NN Activation		Accuracy
Conventional using FSM-based [45]		65.5%
Near-Zero weight removed using FSM-based [45]		67.4%
Proposed preprocessing w/o weight pruning using FSM-based		77.4%
Proposed preprocessing with weight pruning using FSM-based [45]	$\tau =0.4$	73.2%
	$\tau =0.3$	77.9%
	$\tau =0.2$	80.4%
	$\tau =0.1$	82.0%
Proposed preprocessing with weight pruning using proposed LIF-based	$\tau =0.4$	77.8%
	$\tau =0.3$	79.5%
	$\tau =0.2$	82.7%
	$\tau =0.1$	88.4%

Table 2 reports the hardware resource consumption and delay for each single activation module. Unlike the FSM, the LIF module operates only when valid inputs are received, offering power advantages. Furthermore, unlike the FSM, which relies on the number of state registers to define a fixed slope for the activation function, the LIF model requires fewer registers, resulting in reductions in both area and delay. At the activation module level, the proposed design delivers 43.8% lower power, 5.5% reduced delay, and 17.2% smaller area compared to conventional designs. The FoM is defined as the product of power, delay, and area (PPA), representing the overall hardware efficiency. The power, delay, area, and FoM values are normalized to the FSM-based design, where the metrics for the proposed LIF-based design are presented as relative ratios. This translates to a 2.3× improvement in the FoM normalized by power, delay, and area. Furthermore, validation on the Xilinx xc7a100tcsg324-3 demonstrates that the proposed LIF-based activation significantly outperforms the FSM-based activation in terms of hardware efficiency, as illustrated in Table 3. Consistent with the analysis in Table 2, the metrics in Table 3 are normalized to the FSM-based reference. Specifically, the proposed design achieved a 17.6% reduction in power consumption and a 17.1% decrease in critical path delay compared to the FSM baseline. Regarding resource utilization, a significant reduction is observed in both Look-Up Table (LUT) and Flip-Flop (FF) usage. Although both architectures require the same 255 cycles for 8-bit MNIST inference, the reduced critical path delay in the proposed design implies a higher maximum operating frequency, directly leading to lower latency and faster real-time processing.

Table 2. Comparison of hardware overhead and FoM for a single activation module between FSM-based and proposed LIF-based designs in 65 nm CMOS.

SC-NN Activation	Power		Delay		Area		FoM
	(mW)	Norm.	(ns)	Norm.	(μm2)	Norm.	(PPA)	Norm.
FSM-based [45]	0.774	1.0	1.798	1.0	2994.3	1.0	4167	1.0
Proposed LIF-based	0.435	0.56	1.700	0.95	2479.8	0.83	1934	0.44

Table 3. Comparison of power, delay, and resource efficiency for FPGA implementation.

SC-NN Activation	Power		Delay		Cycle		Utilization
	(mW)	Norm.	(ns)	Norm.	(#)	Norm.	LUT	FF
FSM-based [45]	17.0	1.0	3.492	1.0	255	1.0	443	123
Proposed LIF-based	14.0	0.82	2.895	0.83	255	1.0	113	114

Figure 8a,b show the post-PnR layouts of the baseline FSM module and the proposed LIF module, respectively. Both designs were implemented with a target utilization density of 86–87% to ensure a fair comparison. The measurement results indicate that the total area of the FSM module is 63,504 $\mathsf{\mu }{\mathrm{m}}^2$, whereas the proposed LIF module occupies 49,151 $\mathsf{\mu }{\mathrm{m}}^2$. Such a compact physical footprint implies that the proposed approach not only alleviates routing congestion but also enables higher integration density, demonstrating its superior hardware efficiency for SoC implementations.

Figure 8. Post-PnR layouts of activation modules in the first fully connected layer using commercial 65 nm standard cells. (a) Baseline FSM module and (b) proposed LIF module.

5. Discussion and Conclusions

This study proposes a hardware-efficient SC-NN framework designed to minimize intrinsic calculation errors while maximizing hardware efficiency. Prior SC-NN architectures have predominantly relied on FSM-based activation functions, which entail fixed activation slopes and considerable hardware overhead. We address this research gap by introducing a novel activation paradigm that moves beyond conventional FSMs. By leveraging the structural isomorphism between the population count in stochastic bitstreams and the dynamics of SNNs, we implemented a LIF-based activation function. Concurrently, we identified that the error in bipolar SC multiplication is heavily concentrated in a cross-shaped region and implemented a novel Preprocessing Layer to eliminate this Dead Zone. This dual approach effectively integrates error mitigation with a dynamic activation mechanism, enhancing both accuracy and efficiency.

This work is significant in that it moves beyond theoretical simulations to practical hardware realization. We employed pseudo-random bitstreams generated by a realistic 8-bit LFSR and verified the SC-NN based on 8-bit integer quantization at the hardware level. Quantitatively, the proposed design demonstrates distinct advantages over traditional FSM-based baselines: it reduces power consumption by 43.8%, area by 17.2%, and delay by 5.5%, ultimately yielding a 2.3× enhancement in the FoM. Unlike previous SC-NNs that often relied on ideal stochastic sources in software simulation, our results reflect practical hardware constraints and verify that the proposed LIF-based approach offers a superior trade-off between accuracy and hardware cost compared to existing FSM implementations.

Furthermore, the proposed paradigm comprising dead-zone elimination and LIF activation is not limited to specific network topologies but can be applied as a complementary module to enhance the performance of various SC-NN architectures. Although this study primarily verified the architecture on the MNIST dataset using a fully connected topology, the results demonstrate robust scalability. The fundamental validity of the proposed error mitigation and activation schemes suggests that they can be effectively extended to deeper architectures using stochastic computing and more complex datasets, such as CIFAR-10 or ImageNet, which remains a subject for future investigation. Continued research that prioritizes these novel techniques over resource-intensive scaling will further solidify SC-based networks as a practical alternative for edge and mobile devices.