Mathematical Model of Dual-Active-Bridge Converters for Control and Hardware-in-the-Loop Applications

Abstract

This work presents an integrated methodology for modeling, parameter tuning, and experimental emulation of Dual Active Bridge (DAB) converters aimed at detailed simulation, control design, and real-time emulation. This is needed to bridge the gap between theoretical modeling and practical implementation, enabling accurate prediction of converter behavior under realistic operating conditions and facilitating the development of control strategies. The study begins with the derivation of a nonlinear model including parasitic elements and transformer characteristics, enabling accurate representation of the converter’s dynamics across operating conditions. To address deviations caused by component tolerances, the model parameters are calibrated using a multi-algorithm optimization framework based on Particle Swarm Optimization, Grey Wolf Optimizer, Secretary Bird Optimization, and Whale Optimization, where the error between predicted and experimental waveforms is minimized. The comparative analysis allows selecting the most suitable optimization strategy based on statistical analyses. The model is also discretized and implemented on a Hardware-in-the-Loop (HIL) platform based on a high-performance microcontroller, enabling real-time emulation of the converter as a digital twin. Moreover, a control-oriented version of the model is presented and used to design a voltage controller, which is subsequently tested in both the HIL environment and on a real DAB converter prototype. Experimental results report differences between HIL and real prototype below 3.9% for currents and 4.45% for voltages in multiple operation conditions, demonstrating an accurate representation of the real power system. This methodology ensures low errors between theoretical, simulated, and experimental behavior, providing a framework for accurate modeling and controller design of DAB converters.

1. Introduction

The Dual Active Bridge (DAB) converter is one of the most widely adopted isolated bidirectional DC–DC topologies in energy storage systems, electric vehicles, and modern DC networks [1,2]. Such a predilection is based on the DAB converter advantages: high efficiency, high power density, bidirectional power flow capability, galvanic isolation, and soft switching (ZVS). However, precise modeling of the DAB converter remains a challenge due to its strong nonlinear behavior and the interdependence among multiple design parameters, which has driven the evolution of models from idealized approximations to high-fidelity mathematical formulations.

Early model developments relied on simplified representations that neglected losses and parasitics, providing analytical expressions of transferred power as a function of the phase shift between bridges, particularly under single-phase-shift (SPS) modulation. Although applicable for preliminary design, such models show significant limitations in predicting efficiency and control behavior, as they disregard practical effects such as switching and conduction losses or leakage inductances [3].

A significant advance was made by Krismer and Kolar, who developed a detailed model that includes conduction and switching losses in the semiconductors, magnetic core losses, and parasitic resistances, demonstrating that idealized formulations underestimate total system dissipation [4]. For high-power applications, such as automotive converters or bidirectional DC network interfaces, those detailed models are essential for accurately estimating efficiency. More recently, Vardhan et al. analyzed the influence of finite magnetizing inductance, demonstrating that ignoring such an effect alters the resonant behavior and can lead to transformer oversizing [5]. The model proposed in this work integrates both leakage and external inductances, providing more accurate tools for electromagnetic and thermal optimization.

The evolution of average models has led to more generalized and accurate formulations. For example, Liu et al. in [6] introduced the enhanced generalized average model (EGAM), which incorporates additional harmonic components beyond traditional generalized average models (GAMs), thereby improving the prediction of dynamic response. Chakraborty et al. proposed a high-precision GAM that includes high-frequency terms to better capture transient behavior [7]. Veeramraju and Kimball extended this approach to AC-DC converters using a multi-frequency EGAM, capable of modeling the interaction between the grid and switching elements using discrete convolutions in the frequency domain, thus overcoming the limitations of conventional and 2D-GAM models [8].

Dynamic small-signal modeling has also proven essential for the design of classical controllers. Rajender et al. [9] developed a small-signal model for EV chargers based on DAB converters using state-space averaging and Fourier expansion, enabling the design of Proportional–Integral (PI) controllers that ensure stability across multiple charging modes (CC, CV, CCCV). On the other hand, Dubey and Lakshminarasamma focused on the series-resonant DAB (SRDAB) converter, formulating a GAM that includes the resonant capacitor voltages and inductor current, effectively capturing the beat-frequency phenomena and providing a small-signal basis for control design under phase-shift modulation [10].

The DAB converter has been used in a range of applications, from renewable energy systems to electric vehicle charging and energy storage interfaces. One prominent application is photovoltaic generation, where the DAB converter has been identified as a suitable solution due to its high efficiency, galvanic isolation, and wide voltage conversion range. Recent contributions have addressed design-oriented approaches that consider PV generator interaction for maximum power extraction through appropriate selection of transformer turns ratio and leakage inductance [11], control-oriented linearized models that facilitate classical controller design and stability analysis [12], and advanced cascade structures with adaptive regulation for robust maximum power point tracking under varying conditions [13]. These complementary efforts underscore the importance of an integrated approach combining design, modeling, and control. Another common scenario where the DAB model plays a critical role is controller design. The availability of accurate models has enabled more reliable control strategies, with PI and PID controllers remaining predominant when supported by calibrated representations of system gain and phase [14]. Model-based predictive voltage control schemes complemented by disturbance observers have achieved superior speed and robustness compared to conventional methods [15].

Given the wide variety of models used in the literature, the accuracy of DAB converter parameter estimation is a fundamental pillar for the simulation and design of controllers that are not robust (i.e., sensitive to parameter deviations) but offer high performance. While simplified models neglect losses, leakage inductance, or thermal effects, classical controllers based on generalized averaging (or small-signal theory) require precise knowledge of resistances, parasitic capacitances, magnetic inductances, and core losses to ensure realistic phase and gain margins. A poor parameter estimation leads to suboptimal responses or instability.

To mitigate this problem, multiple parameter identification and calibration techniques, offline and online, have been applied to power converters. However, some methodologies can be hybrid in nature, that is, an offline preprocessing technique, like the Taguchi-ANOVA [16], combined with real-time parametric estimation. The methodology can be structured in two sequential phases: first, offline preprocessing (Taguchi), which defines orthogonal arrays to identify the converter’s critical parameters, followed by the percentage quantification of each parameter (ANOVA) based on the system’s responses (efficiency, transient response, frequency response). Then, the selection of parameters with a statistically significant contribution, and finally, the reduced model calculation. The second phase is executed in real-time, and consists of sampling the signals from the converter during operation (voltages, currents, temperature), then applying the dimensionality reduction defined in phase 1 to filter the input variables, next running a lightweight optimization algorithm on the reduced search space to estimate the current parameters, and finally incorporating the estimated parameters into the system.

However, offline optimization techniques have emerged as powerful tools for tuning model parameters based on experimental tests (transient response, frequency response, switched waveforms), as they enable the identification of the combination that minimizes the error between the simulation and the actual measurement. This ensures reliable predictive controllers with gains tuned to actual behavior, improving stability, bandwidth, and robustness, and thus bridging the gap between the theoretical model and the physical converter. This approach surpasses manual or linear identification by capturing nonlinearities and couplings. The selection of the optimization algorithm constitutes the first stage of this work.

The parameter estimation method must include a comparison of multiple optimization algorithms, ranging from gradient descent to metaheuristics such as PSO, GWO, SBOA, or WOA. This will avoid local minima and ensure the best possible representation of the physical converter, so that the model’s accuracy allows accurate simulations and the design of robust controllers in the classical sense, yet insensitive to parameter drifts thanks to a highly accurate base model.

However, research on optimizers for DAB converters has focused on three key areas: converter design optimization, controller design optimization, and parameter estimation optimization. The first area focuses on the converter and its parameters (transformation ratio, inductance, number of turns in the windings, and air gap length), using particle swarm optimization (PSO) algorithms, genetic algorithms, or MATLAB’s Fmincon (R2022a) function [17,18,19,20,21].

The second topic is controller optimization. In general, these studies aim to optimize the modulation variables to improve transient performance and efficiency. To this end, deep reinforcement learning (DRL) and numerical optimization routines are used to find modulation trajectories that minimize, for example, conduction losses [17,22,23,24,25,26,27].

Third, the approach used in the methodology proposed in this paper: optimization for estimating the converter parameters. This optimization process has received small attention in the literature, which has focused on identifying the series/leakage inductance, the capacitance and its equivalent series resistance, and the on-resistance (Ron) to improve controller accuracy and enable condition monitoring. The most commonly used optimizers are based on recursive least squares (RLS), particle swarm optimization (PSO), gradient descent, and genetic algorithms combined with neural networks (GA-BP) [23,24,25,27,28]. Those methods are primarily used for fault diagnosis, controller tuning, and modulation optimization.

The next step is to validate the hypothesis through a step-by-step process that ensures the system’s reliability, efficiency, and safety before its final implementation. This process is structured in four complementary stages: Software-In-the-Loop (SIL), Processor-In-the-Loop (PIL), Hardware-In-the-Loop (HIL), and experimental prototype validation. The SIL stage enables verification of the converter’s mathematical model and control strategy in a purely simulated environment, without interaction with physical hardware. Here, conceptual errors are detected, and parameters are adjusted without operational risks. Subsequently, in the PIL tests, the physical controller (such as a microcontroller or DSP) is introduced into the simulation, validating the real-time implementation of the algorithm and its interaction with the converter model. This stage reveals computational limitations and coding errors.

Next, HIL integrates precise emulation of the converter’s electrical dynamics with real-time controller operation. This allows the system’s behavior to be evaluated under extreme conditions or failures, without exposing expensive components to damage. Finally, experimental validation is performed with the complete prototype in actual operation, confirming performance under real conditions of load, ripple, thermal efficiency, and electromagnetic compatibility. Each stage is essential: SIL reduces initial costs, PIL ensures proper implementation of control software, HIL mitigates risks before physical assembly, and experimental validation verifies compliance with technical specifications. Together, those phases form a robust methodology that minimizes errors, accelerates development, and ensures quality in research on switched power converters.

Previous work in the literature focused on HIL platforms for the development of DAB converters primarily employs high-performance commercial solutions such as Typhoon HIL, OPAL-RT, RTDS, and PLECS RT Box [14,29,30,31,32,33]. Those technologies use real-time processors and FPGAs to achieve high-fidelity simulations, interacting with external controllers based on DSPs or microcontrollers such as the STM32F446RE [14,29,34,35,36].

The models simulated on those platforms are predominantly switched-mode, allowing frequencies of up to 200 kHz through optimization techniques such as “nanostep” or sub-cycle averaging in FPGAs [29,37]. High-fidelity models incorporate leakage inductance, dead times, and conduction losses, as well as thermal models of switches to bridge the gap between simulation and reality [29]. Furthermore, GAMs based on Fourier transforms have been implemented to design control gains [37,38] systematically.

The primary purpose of those platforms is to evaluate advanced control strategies (model predictive control (MPC), robust control, or reinforcement learning), optimize efficiency by reducing reactive power (backflow power), and validate protection systems in critical applications such as ultra-fast electric vehicle charging and microgrids [30,31,32,36,39,40].

A key aspect is the prior validation of those models against actual converters. While some platforms show a high degree of agreement with actual converters [29,31,32], considerable deviations due to unmodeled parasitic elements have also been identified.

In that context, this paper proposes an integrated methodology for the modeling, parameter tuning, and experimental validation of DAB converters models, which is aimed at real-time HIL emulation purposes. The discrete-time model is calibrated through PSO-based optimization to match the converter’s experimental responses. A second modeling approach, for control applications, is derived by truncating high-frequency components from the more accurate representation. That modeling approach is validated by designing a voltage controller, which is tested in both on the real converter and in a HIL platform running on a high-performance microcontroller.

The methodology process followed in this work starts from the detailed modeling of the converter (considering conduction losses) to the experimental validation of the model and control usefulness through real operation and HIL tests. Each stage was designed to ensure consistency among the theoretical model, the simulated behavior, and the experimental response of the system. This methodological approach ensured the accuracy and coherence of the model, as well as the robustness and practical feasibility of the designed control.

The rest of the paper is organized as follows. Section 2 describes the first stage of the methodological process, which includes the derivation of the mathematical model, the parameter identification and the model validation. Section 3 describes the model discretization and HIL implementation, which corresponds to stage 2 of the methodological process. Then, Section 4 presents stages 3 and 4, which derive a control-oriented version of the model to produce a transfer function suitable for control design; the usability of that transfer function is tested with a classical control design. Moreover, that control system is tested using both the developed HIL platform and a real DAB converter. Finally, the conclusions of the work close the paper.

2. Mathematical Model

Figure 1 shows the DAB converter used for the modeling stage. In this diagram, the converter is represented including all conduction losses associated with the power devices and passive components. This detailed representation enables the construction of a model that accurately describes the converter’s dynamic behavior across different operating conditions, serving as the foundation for subsequent stages of fitting, validation, and control design.

Figure 1. DAB converter for photovoltaic and battery charger applications.

In the circuital scheme of Figure 1, the main power source is modeled using a Thevenin equivalent formed by a voltage source $v_L$ and its internal resistance $R_{in}$, which supplies the input current $i_{in}$. To smooth out voltage ripples, an input capacitor filter $C_L$ is connected at the low-side interface. The bidirectional core of the DAB converter comprises low-side ($Bridg{e}_1$) and high-side ($Bridg{e}_2$) full-bridges, each featuring four MOSFET switches driven by complementary gating signals. Interfacing both bridges, the high-frequency transformer assembly is represented by an ideal transformer with a turns ratio of 1:N, a leakage inductance $L_k$, and a magnetizing inductance $L_m$. Additionally, a series external inductance $L_p$ is incorporated into the primary side to adjust the power transfer capability. Finally, the high-voltage output stage considers a filtering capacitance $C_H$ connected in parallel with the load impedance, modeled by $R_o$.

The previous circuital model does not account for switching losses, which can be significant in high-power, high-frequency systems that operate without soft-switching techniques. However, the simulation of this model remains widely applicable for several reasons that are worth highlighting. First, the absence of switching losses does not invalidate the use of the model for the design and validation of closed-loop control strategies. The fundamental dynamic phenomena of the converter, such as phase-angle-controlled power transfer, transient responses to load or voltage changes, and system stability, are governed primarily by the transformer’s electromagnetic parameters and leakage inductance, which are modeled in detail. Therefore, the model remains a valuable tool for evaluating controllers in high-power scenarios, where response times and stability margins are critical. Second, for systems that operate without soft-switching and at high frequencies (typically > 100 kHz), switching losses depend heavily on operating conditions (input voltage, load current, semiconductor temperature). Incorporating them into an averaged or small-signal model requires complex, device-specific empirical characterizations, which are often unavailable in the early stages of design. Therefore, this deliberately simplified approach provides a lower bound on efficiency and, more importantly, serves as a basis for adding experimentally calibrated switching-loss models without losing the model’s fundamental structure. Finally, in the context of parametric estimation via optimization, excluding switching losses reduces the number of parameters to be estimated, facilitates convergence, and allows the algorithms to focus their efforts on the precise identification of the electrical and magnetic parameters. Once this base model has been obtained, it is feasible to incorporate switching-loss blocks as external elements to the converter, e.g., using lookup tables or coupled thermal models, which are fed by the currents and voltages calculated by the model. In this way, the model becomes a core for fast electromagnetic simulation, to which additional layers of fidelity can be added without compromising numerical stability or real-time performance.

Recent studies [1] have proposed hybrid modulation techniques that combine PWM and optimal discrete PDM. This approach enables continuous output regulation, generation of symmetrical pulses, elimination of even subharmonics, and improved system efficiency. However, since one of the objectives of this paper is to demonstrate the benefits of the model-tuning technique, the adopted modulation scheme is shown in Figure 2. This figure illustrates the steady-state switching waveforms of the primary ($u_L$) and secondary ($u_H$) AC voltage profiles generated by $Bridg{e}_1$ and $Bridg{e}_2$, respectively. Both operating signals are unipolar square waves shifting between logic levels 0 and 1 with a fixed 50% duty cycle to maximize power transfer efficiency [41]. The relative phase shift angle between the two bridges, denoted by $\delta$, varies continuously within the range $[-\pi ,\pi ]$ radians, governing both the direction and magnitude of the power throughput.

Figure 2. Switching waveforms of both low-side and high-side bridges.

The time-domain intersections of these switching signals define four distinct operational structures within a single switching period, corresponding to the conduction intervals of the semiconductor devices shown in Figure 3. To capture the comprehensive non-linear losses of the hardware, the equivalent circuit model accounts for all critical parasitic elements. The MOSFET conduction losses are modeled by the lumped series resistances $R_{D_L}$ and $R_{D_H}$ for the low- and high-side bridges, respectively. Transformer losses are accurately represented by the leakage resistance $R_{L_k}$ and magnetizing resistance $R_{L_m}$, while $R_{L_p}$ denotes the internal copper loss of the external series inductor. Lastly, $R_{C_L}$ and $R_{C_H}$ characterize the equivalent series resistances (ESR) of the input and output decoupling capacitors, completing a robust multi-variable non-linear representation.

Figure 3. Switching States of the DAB converter. (a) State 1; (b) State 2; (c) State 3; (d) State 4.

The analysis of the four switching intervals of a single switching period shows that activating the high-side and low-side bridges ($u_H$ and $u_L$) reverses the polarity of specific voltages and currents in the equivalent circuits. These sign inversions arise because each bridge alternately connects the transformer terminals to positive and negative bus voltages, thus modifying the reference direction of certain variables depending on the switching state. To obtain a unified state-space representation that remains valid for all switching intervals, the unipolar logic signals $u_H$ and $u_L$ are replaced by the bipolar variables $s_1$ and $s_2$, taking values of +1 and −1. Figure 2 depicts the relationship between the physical switching signals and their bipolar equivalents, thus describing the mechanism in which the model captures the sign changes induced by the bridge commutations.

By applying Kirchhoff’s voltage and current laws (KVL and KCL) to each of the subcircuits defined by the switching states of Figure 3, the primary-side relations expressed in Equations (1)–(3) are obtained, where $i_{in}$ represents the input current on the low-voltage side, $v_L$ is the input voltage, and $v_{pri}$ denotes the voltage at the primary side of the transformer.

$$\begin{array}{c}{i}_{C_L}=i_{in}-i_{L_p}·s_1\end{array}$$

(1)

$$\begin{array}{c}{i}_{in}=(v_L-v_{C_L}-v_{R_{C_L}})/R_{in}\end{array}$$

(2)

$$\begin{array}{c}\left(v_{pri}+v_{L_p}+v_{R_{L_p}}+2·v_{R_{D_L}}\right)·s_1-v_{C_L}-v_{R_{C_L}}=0\end{array}$$

(3)

Similarly, Equations (4)–(7) describe the voltages and currents on the secondary side, where $v_{Ro}$ corresponds to the terminal voltage across the load resistance, and $v_{sec}$ is the transformer secondary-side voltage associated with the switching function $s_2$.

$$\begin{array}{c}{i}_{C_H}=i_{L_k}·s_2-(v_{R_o}/R_o)\end{array}$$

(4)

$$\begin{array}{c}\left(v_{sec}-v_{L_k}-v_{R_{L_k}}-2·v_{R_{D_H}}\right)·s_2-v_{C_H}-v_{R_{C_H}}=0\end{array}$$

(5)

$$\begin{array}{c}-v_{sec}+v_{L_m}+v_{R_{L_m}}=0\end{array}$$

(6)

$$\begin{array}{c}{v}_{R_o}=v_{C_H}+v_{R_{C_H}}\end{array}$$

(7)

From the analysis of the currents in the primary and secondary windings of the transformer, Equations (8) and (9) are obtained, relating the currents of the primary external inductance ($i_{L_p}$), the magnetizing inductance ($i_{L_m}$), the leakage inductance ($i_{L_k}$), and the secondary side current ($i_s$).

$$\begin{array}{c}{\displaystyle \frac{d{i}_{L_p}}{dt}}=\left({\displaystyle \frac{d{i}_{L_m}}{dt}}+{\displaystyle \frac{d{i}_{L_k}}{dt}}\right)·N\end{array}$$

(8)

$$\begin{array}{c}{i}_s=i_{L_m}+i_{L_k}\end{array}$$

(9)

Using those equations and both the charge and volt-second balances, we obtain the equations for the derivatives of the voltage in the input capacitor $v_{C_L}$ in (10), the voltage in the output capacitor $v_{C_H}$ in (11), the primary-side current $i_{L_p}$ in (12), and the secondary-side current or magnetizing inductance $i_{L_k}$ in (13).

$$\begin{array}{c}{\displaystyle \frac{d{v}_{C_L}}{dt}}=-{\displaystyle \frac{v_{C_L}-v_L+R_{in}·s_1·i_{L_p}}{C_L·(R_{C_L}+R_{in})}}\end{array}$$

(10)

$$\begin{array}{c}{\displaystyle \frac{d{v}_{C_H}}{dt}}=-{\displaystyle \frac{v_{C_H}-R_o·s_2·i_{L_k}}{C_H·(R_{C_H}+R_o)}}\end{array}$$

(11)

$$\begin{array}{c}{\displaystyle \frac{d{i}_{L_p}}{dt}}=s_1·A_{31}·v_{C_L}+s_2·A_{32}·v_{CH}+A_{33}·i_{L_p}+A_{34}·i_{L_k}\end{array}$$

(12)

$$\begin{array}{c}{\displaystyle \frac{d{i}_{L_k}}{dt}}=s_1·A_{41}·v_{C_L}+s_2·A_{42}·v_{C_H}+A_{43}·i_{L_p}+A_{44}·i_{L_k}\end{array}$$

(13)

The coefficients of the previous derivatives are reported in Equations (14)–(21):

$$\begin{array}{c}{A}_{31}={\displaystyle \frac{R_{in}·N^2·(L_k+L_m)}{(R_{C_L}+R_{in})·(L_k·L_m+L_k·L_p·n^2+L_m·L_p·N^2)}}\end{array}$$

(14)

$$\begin{array}{c}{A}_{32}=-{\displaystyle \frac{L_m·R_o·N}{(R_{C_H}+R_o)·(L_k·L_m+L_k·L_p·N^2+L_m·L_p·N^2)}}\end{array}$$

(15)

$$\begin{array}{c}{A}_{33}=-(L_k·(R_{C_L}·R_{L_m}+R_{in}·R_{L_m})+\hfill \\ \hfill {\displaystyle \frac{(L_k+L_m)·N^2·\left(2·R_{C_L}·R_{D_L}+R_{C_L}·R_{in}+2·R_{D_L}·R_{in}+R_{C_L}·R_{L_p}+R_{in}·R_{L_p})\right)}{(R_{C_L}+R_{in})·(L_k·L_m+L_k·L_p·N^2+L_m·L_p·N^2)}}\end{array}$$

(16)

$$\begin{array}{c}{A}_{34}=\left(-n·L_k(-R_{C_H}·R_{L_m}-R_{L_m}·R_o)\right.\hfill \\ {\displaystyle \frac{\left.-n·L_m·(2·R_{C_H}·R_{D_H}+R_{C_H}·R_{L_k}+R_{C_H}·R_o+2·R_{D_H}·R_o+R_{L_k}·R_o)\right)}{(R_{C_H}+R_o)·(L_k·L_m+L_k·L_p·N^2+L_m·L_p·N^2)}}\hfill \end{array}$$

(17)

$$\begin{array}{c}{A}_{41}={\displaystyle \frac{L_m·R_{in}·N}{(R_{C_L}+R_{in})·(L_k·L_m+L_k·L_p·N^2+L_m·L_p·N^2)}}\end{array}$$

(18)

$$\begin{array}{c}{A}_{42}=-{\displaystyle \frac{R_o·(L_p·N^2+L_m)}{(R_{C_H}+R_o)·(L_k·L_m+L_k·L_p·N^2+L_m·L_p·N^2)}}\end{array}$$

(19)

$$\begin{array}{c}{A}_{43}=\left(-N·L_p·(-R_{C_L}·R_{L_m}-L_p·R_{in}·R_{L_m})\right.\hfill \\ {\displaystyle \frac{\left.-N·L_m·(2·R_{C_L}·R_{D_L}+R_{C_L}·R_{in}+2·R_{D_L}·R_{in}+R_{C_L}·R_{L_p}+R_{in}·R_{L_p})\right)}{(R_{C_L}+R_{in})·(L_k·L_m+L_k·L_p·N^2+L_m·L_p·N^2)}}\hfill \end{array}$$

(20)

$$\begin{array}{c}{A}_{44}=\left(-L_m·(2·R_{C_H}·R_{D_H}+R_{C_H}·R_{L_k}+R_{C_H}·R_o+2·R_{D_H}·R_o+R_{L_k}·R_o)\right.\hfill \\ -L_p·N^2·\left(2·R_{C_H}·R_{D_H}+R_{C_H}·R_{L_k}+R_{C_H}·R_{L_m}+\right.\hfill \\ {\displaystyle \frac{\left.\left.R_{C_H}·R_o+2·R_{D_H}·R_o+R_{L_k}·R_o+R_{L_m}·R_o\right)\right)}{(R_{C_H}+R_o)·(L_k·L_m+L_k·L_p·N^2+L_m·L_p·N^2)}}\hfill \end{array}$$

(21)

Finally, Equations (10)–(21) form the switched non-linear model describing the dynamic behavior of the DAB converter.

2.1. Identification of the Model Parameters

Adopting the nominal electrical values provided by component manufacturers introduce significant discrepancies between the predicted average and ripple waveforms and the actual experimental measurements. These deviations are inherently introduced by manufacturing tolerances, environmental factors, and high-frequency parasitic effects not encapsulated by ideal mathematical models, such as stray resistances from the printed circuit board (PCB) tracks and localized contact losses in the soldering process.

This paper presents a systematic parameterization framework to bridge the gap between theoretical modeling and physical hardware behavior. This process relies on a closed-loop optimization scheme that captures raw dynamic data from the physical prototype, executes synchronized time-domain simulations of the DAB converter, and calibrates the vales of the parameter set using population-based metaheuristic algorithms to minimize experimental-to-simulated waveform mismatch.

2.1.1. Experimental Data Generation

Multiple experimental design strategies can be used to characterize the DAB converter. For example, the Taguchi-ANOVA statistical technique [16], which streamlines experimentation and quantifies the influence of parameters on minimizing the converter model’s fitting error, is a powerful preprocessing step to narrow the search space before optimization. However, in this work, statistical preprocessing was omitted to test the performance of several optimization algorithms using the raw experimental data to estimate the 15 model parameters. For a production process, in which the optimization algorithm is already defined, the Taguchi-ANOVA statistical technique will significantly reduce the number of experiments required for the parameterization process.

The first step is to produce reliable experimental data to parameterize the model. This process required the construction of the experimental DAB converter depicted in Figure 4 with a switching frequency $f_{sw}$ = 20 kHz, for which the theoretical electrical parameters were extracted from the manufacturers’ datasheets; Table 1 reports those initial data in the first two columns.

Figure 4. Experimental DAB converter.

Table 1. Nominal values, manufacturing tolerances, and optimization search bounds for the DAB converter parameters.

Parameter	Nominal Value	Tolerance	Lower Bound	Upper Bound
$R_{in}$	0.5 $\Omega$	$\pm 20\%$	0.400 $\Omega$	0.600 $\Omega$
$C_L$	22 $\mathsf{\mu }$F	$\pm 20\%$	17.60 $\mathsf{\mu }$F	26.40 $\mathsf{\mu }$F
$R_{C_L}$	5.4 m$\Omega$	$\pm 20\%$	4.320 m$\Omega$	6.480 m$\Omega$
$R_{D_L}$	25 m$\Omega$	$\pm 20\%$	20.00 m$\Omega$	30.00 m$\Omega$
$L_p$	22 $\mathsf{\mu }$H	−32%/+20%	14.96 $\mathsf{\mu }$H	26.40 $\mathsf{\mu }$H
$R_{L_p}$	2.3 m$\Omega$	$\pm 20\%$	1.840 m$\Omega$	2.760 m$\Omega$
$L_m$	500 $\mathsf{\mu }$H	$\pm 10\%$	450.0 $\mathsf{\mu }$H	550.0 $\mathsf{\mu }$H
$R_{L_m}$	20 m$\Omega$	−20%/+10%	16.00 m$\Omega$	22.00 m$\Omega$
$L_k$	3.5 $\mathsf{\mu }$H	−50%/+100%	1.750 $\mathsf{\mu }$H	7.00 $\mathsf{\mu }$H
$R_{L_k}$	321 m$\Omega$	$\pm 10\%$	288.9 m$\Omega$	353.1 m$\Omega$
$R_{D_H}$	40 m$\Omega$	$\pm 20\%$	32.00 m$\Omega$	48.00 m$\Omega$
$C_H$	22 $\mathsf{\mu }$F	$\pm 20\%$	17.60 $\mathsf{\mu }$F	26.40 $\mathsf{\mu }$F
$R_{C_H}$	5.4 m$\Omega$	$\pm 20\%$	4.320 m$\Omega$	6.480 m$\Omega$
$R_o$	110 $\Omega$	$\pm 20\%$	88.00 $\Omega$	132.0 $\Omega$
n	6.0	$\pm 1\%$	5.940	6.060

For data acquisition, an oscilloscope recorded the primary-side current ($i_{L_P}$), leakage inductor current ($i_{L_k}$), and load voltage ($v_{R_o}$), exporting the waveforms into CSV format. The instrument configuration utilized a horizontal scale of $20\mathsf{\mu }\mathrm{s}/\mathrm{div}$, a sampling interval of $2\mathrm{ns}$, and a record length of ${10}^5$ data points, ensuring a high time resolution for the parameter identification stage. To mitigate high-frequency switching noise in the $v_{R_o}$ waveform, a digital low-pass filter was implemented. Because this filtering operation induced typical transient edge effects at the boundaries of the record, the initial and final segments were corrected by patching them with the raw experimental data. This procedure successfully preserved signal consistency across the entire time window, preventing numerical distortions during the subsequent optimization and model-fitting routines.

Figure 5 illustrates the profiles of the raw measured waveforms alongside their filtered and corrected counterparts. The filtering process successfully removes high-frequency experimental noise while accurately preserving the underlying dynamic trajectories of the primary-side current ($i_{L_p}$) and the transformer leakage current ($i_{L_k}$). Moreover, this procedure extracts the clean switching ripple profile of the output load voltage ($v_{R_o}$), thereby ensuring signal integrity and preventing numerical divergence during the subsequent optimization and model-fitting routines.

Figure 5. Experimental and filtered data.

2.1.2. Parameter Optimization Using Optimization Algorithms

The identification of the DAB converter model parameters was performed using a population-based optimization framework to test multiple metaheuristic algorithms. In this work, four optimization techniques were considered: Particle Swarm Optimization (PSO), Grey Wolf Optimizer (GWO), Secretary Bird Optimization Algorithm (SBOA), and Whale Optimization Algorithm (WOA); Appendix A describes the specific update strategies for each metaheuristic algorithm. The use of multiple algorithms enables a comprehensive evaluation of the multidimensional solution space and provides a robust benchmark in terms of convergence accuracy, computational speed, and parametric stability.

All algorithms were used to solve the same parameter estimation problem under identical operational conditions. Each method operates over a population of candidate solutions, which are iteratively updated according to their respective mathematical search mechanisms to minimize a predefined objective function.

The optimization vector comprises a set of scaling factors, defined as $\mathbf{Par}$ = $[Pa{r}_1,Pa{r}_2,\dots$, $Pa{r}_{15}]$, which scale the nominal theoretical parameters of the physical elements listed in Table 1 (provided by the manufacturers). These 15 dimensionless coefficients are tolerance tuning weights, strictly constrained within predefined lower and upper boundaries (provided by the manufacturer) to preserve the physical consistency of the identified model.

The objective function, formulated in (22), minimizes the normalized root mean square error (NRMSE) between the experimental and simulated trajectories of the leakage inductor current ($i_{L_k}$), the primary-side current ($i_{L_p}$), and the output load voltage ($v_{R_o}$). Within this formulation, $M=3$ represents the total number of evaluated physical signals, while $N_s$ denotes the record length (in samples) for each waveform. The terms $y_{m,k}^{\exp }$ and $y_{m,k}^{\mathrm{sim}}$ define the experimental and simulated samples, respectively, for the m-th monitored variable ($m=1,2,3$) at the k-th sampling instant. Additionally, the normalization factor $(y_m^{max}-y_m^{min})$ accounts for the full dynamic range of each measured signal, balancing the optimization weight regardless of the signal’s physical units.

$$\mathbf{J}={\displaystyle \frac{1}{M}}{\displaystyle \sum _{m=1}^M}{\displaystyle \frac{\sqrt{\frac{1}{N_s}{\sum }_{k=1}^{N_s}{\left(y_{m,k}^{\exp }-y_{m,k}^{\mathrm{sim}}\right)}^2}}{y_m^{max}-y_m^{min}}}·100$$

(22)

Each algorithm iteratively minimizes this objective function by updating its population of candidate solutions. A unified stopping criterion was adopted for all methods, defined either by reaching a maximum number of iterations $k_{\max }$ or by satisfying a convergence condition based on the statistical dispersion of the objective function values within the population (23). In that stopping criterion $\mathbf{J}=[J_1,J_2,\dots ,J_{N_p}]$ represents the vector of objective function values for the entire population of size $N_p$ at the current iteration, and $\sigma \left(·\right)$ denotes the standard deviation operator. This criterion automatically halts the optimization when the population reaches a state of stagnation, indicating that the swarm or pack has converged around a single solution.

$$\sigma \left(\mathbf{J}\right)<\mathrm{tol}$$

(23)

The specific configurations for each algorithm are detailed in Table 2. The PSO uses dynamic coefficients, with the inertia weight w decreasing linearly from $0.9$ to $0.4$. Moreover, the cognitive ($c_1$) and social ($c_2$) parameters are dynamically adjusted to enhance exploration during the initial iterations, favoring exploitation in the later stages. Similarly, both the GWO and the WOA incorporate an exploration-exploitation control parameter a, which linearly decreases from $2.0$ to $0.0$. The GWO updates positions based on a hierarchy determined by the leadership variables $\alpha$, $\beta$, and $\delta$, in conjunction with a proportional soft-rebound factor of $0.5$. In contrast, the WOA differentiates between a bubble-net attack and a spiral path based on a selection probability threshold of $p=0.5$, while implementing strict boundary clamping. Lastly, the SBOA is structured around a time-segmented exploration phase (Phase P1) that evolves from randomized differential interactions to Gaussian random matrices, then using a polynomial-damped Lévy flight distribution as the iteration progresses. Finally, Phase P2 (exploitation strategy) relies on a fixed probability threshold of $0.5$ and incorporates strict boundary-saturation handling. It should be noted that the WOA, SOBA, and GWO algorithms have predefined parameters, whereas the PSO algorithm has the adjustable parameters $c_1$ and $c_2$. In this study, the commonly used PSO parameters across various configurations, presented in [42,43], are adopted.

Table 2. Internal Hyperparameter Configurations and Boundary Operational Strategies for the Evaluated Metaheuristic Algorithms.

Algorithm	Hyperparameter Description	Value/Operational Strategy
PSO	Inertia weight (w)	Linear decrease from $0.9$ to $0.4$
	Cognitive coefficient ($c_1$)	Linear decrease from $2.5$ to $0.5$
	Social coefficient ($c_2$)	Linear increase from $0.5$ to $2.5$
	Velocity clamping ($V_{max},V_{min}$)	Bounded at $\pm 20\%$ of the search space range
	Boundary handling	Soft-rebound with velocity scaling factor of $-0.5$
GWO	Exploration/Exploitation control (a)	Linear decrease from $2.0$ to $0.0$
	Coefficient vectors ($A_1,A_2,A_3$)	Randomly computed within $[-a,a]$
	Coefficient vectors ($C_1,C_2,C_3$)	Randomly computed within $[0,2]$
	Leadership hierarchy	Position updates driven by $\alpha$, $\beta$, and $\delta$ wolves
	Boundary handling	Proportional soft-rebound with scaling factor of $0.5$
SBOA	Phase P1 exploration ($t<t_{max}/3$)	Randomized multi-individual differential interaction
	Phase P1 exploration ($t<2t_{max}/3$)	Gaussian random matrix scaled by $exp\left({(t/t_{max})}^4\right)$
	Phase P1 exploration ($t\ge 2t_{max}/3$)	Lévy flight distribution with polynomial damping
	Phase P2 exploitation parameter ($r_i$)	Constant probability threshold fixed at $0.5$
	Phase P2 exploitation strategy	Swaps between Gaussian best-guided walks and K-scaled steps
	Boundary handling	Strict boundary saturation handling (clamping)
WOA	Exploration/Exploitation control (a)	Linear decrease from $2.0$ to $0.0$
	Spiral shape constant (b)	Fixed constant equal to $1.0$
	Spiral path parameter (l)	Uniformly distributed random value within $[-1,1]$
	Selection probability (p)	Threshold at $0.5$ for spiral path or bubble-net choice
	Search mechanisms	Encircling prey ($\left|A\right|<1$) and random whale exploration ($\left|A\right|\ge 1$)
	Boundary handling	Strict boundary saturation handling (clamping)

2.2. Hyperparameter Sensitivity Analysis and Optimization Scenarios

Beyond their internal updating operators, metaheuristic algorithms are highly sensitive to macroscopic search configurations, such as population size and execution limits. To achieve a rigorous, unbiased assessment of their robustness, speed, and precision when identifying the DAB converter parameters, it was established a comprehensive experimental matrix consisting of nine distinct tuning scenarios (denoted as ${\mathrm{P}}_1$ through ${\mathrm{P}}_9$).

As detailed in Table 3, these scenarios were designed by cross-varying three critical execution hyperparameters: the population size ($N_p$), the maximum allowable iterations ($k_{max}$), and the stagnation convergence tolerance (tol). This parametric sweep enables to validate each algorithm’s behavior across different search spaces.

Table 3. Experimental Matrix Definition for Hyperparameter Sensitivity Sweep.

Scenario	Population Size (${\mathit{N}}_{\mathit{p}}$)	Maximum Iterations (${\mathit{k}}_{max}$)	Convergence Tolerance (tol)
${\mathrm{P}}_1$	20	200	$1.0\times {10}^{-3}$
${\mathrm{P}}_2$	20	400	$1.0\times {10}^{-3}$
${\mathrm{P}}_3$	20	600	$1.0\times {10}^{-3}$
${\mathrm{P}}_4$	30	200	$1.0\times {10}^{-4}$
${\mathrm{P}}_5$	30	400	$1.0\times {10}^{-4}$
${\mathrm{P}}_6$	30	600	$1.0\times {10}^{-4}$
${\mathrm{P}}_7$	40	200	$1.0\times {10}^{-5}$
${\mathrm{P}}_8$	40	400	$1.0\times {10}^{-5}$
${\mathrm{P}}_9$	40	600	$1.0\times {10}^{-5}$

Figure 6 presents the final $\mathrm{NRMSE}$ values achieved across the nine experimental scenarios for the four evaluated algorithms. It is observed that the optimization errors for most trials are constrained between $2.7\%$ and $3.2\%$. However, the WOA algorithm exhibits a distinctive performance in Scenario ${\mathrm{P}}_2$, reaching a maximum error peak of $3.95\%$.

Figure 6. Comparative analysis of the final Normalized Root Mean Square Error ($\mathrm{NRMSE}$) across the nine evaluation scenarios (${\mathrm{P}}_1$ to ${\mathrm{P}}_9$) for each metaheuristic algorithm.

In addition, Figure 7 displays the computational clusters by plotting execution times (in hours) against the final fitting error for each trial. Notably, the SBOA algorithm consistently demands the highest execution time. This behavior is mathematically justified by its internal search mechanism, which performs a double evaluation of the objective function per iteration, thereby increasing the computational time. Nevertheless, in terms of model accuracy, this extended exploration enables SBOA to achieve some of the lowest $\mathrm{NRMSE}$ values, which are competitively with the PSO algorithm.

Figure 7. Computational trade-off analysis mapping the execution time against the model fitting accuracy ($\mathrm{NRMSE}$) for all optimization trials.

Figure 8 illustrates the step-by-step NRMSE convergence history for scenarios ${\mathrm{P}}_3$, ${\mathrm{P}}_6$, and ${\mathrm{P}}_9$, capturing the core trade-offs of the maximum iteration budget ($k_{max}=600$) under varying population sizes ($N_p$) and tolerances. The profiles reveal that smaller populations ($N_p=20$, ${\mathrm{P}}_3$) drop sharply the NRMSE during opening iterations, they stagnate early; in contrast, larger populations ($N_p=40$, ${\mathrm{P}}_9$) trade off initial optimization speed for an enhanced exploration of the 15-dimensional search space, successfully preventing premature convergence to local minima. Furthermore, the algorithmic comparison (from Appendix A) shows that GWO and WOA require a larger number of iterations to stabilize their final cost function values; however, PSO and SBOA demonstrate a superior global search capability, locating the minimum error within half of the iteration budget and maintaining stability for the remainder of the process.

Figure 8. Comparison of tuning convergence curves across metaheuristic optimization algorithms under different hyperparameter scenarios. (a) GWO Convergence; (b) PSO Convergence; (c) SBOA Convergence; (d) WOA Convergence.

Figure 9 illustrates the trajectory profiles of the population standard deviation ($\sigma \left(\mathbf{J}\right)$) across scenarios ${\mathrm{P}}_3$ and ${\mathrm{P}}_9$, emphasizing the distinct search dynamics exhibited by the four metaheuristic approaches. The PSO and SBOA frameworks effectively trigger the early-stopping condition, surpassing the horizontal convergence thresholds ($\mathrm{tol}={10}^{-3}$ and $\mathrm{tol}={10}^{-5}$) before reaching the execution limit. In contrast, the GWO and WOA profiles remain consistently flat and above these thresholds, leading to termination strictly due to the maximum iteration limit ($k_{max}=600$). Those results show that both PSO and SBOA efficiently guide their entire population toward a highly concentrated and localized search area for fine-tuning. On the other hand, the elevated and non-convergent standard deviation of GWO and WOA indicates that their candidate solutions remain dispersed throughout the 15-dimensional search space during the final stages of the optimization process.

Figure 9. Evolution of the standard deviation $\sigma \left(\mathbf{J}\right)$ against the early-stopping thresholds for different optimization scenarios. (a) Population standard deviation under strict convergence tolerance ($\mathrm{tol}={10}^{-3}$, scenario ${\mathrm{P}}_3$). (b) Population standard deviation under relaxed convergence tolerance ($\mathrm{tol}={10}^{-5}$, scenario ${\mathrm{P}}_9$).

To identify the optimal operational configuration for each metaheuristic framework, a formal multi-objective decision-making procedure was adopted based on the weighted-sum method. Relying exclusively on the lowest $\mathrm{NRMSE}$ for selecting a tuning scenario frequently introduces significant computational overhead, while emphasizing speed can lead to substantial accuracy loss. To address this problem, a composite selection score ($S_i$) was developed to establish the best trade-off between those competing factors. First, the raw objective function error (J) and the execution time (T) vectors across all nine scenarios were normalized to a range between 0 and 1 using a min–max scaling technique. This approach ensured numerical comparability across different physical scales. Subsequently, a composite penalization function was computed as follows:

$$S_i=w_{\mathrm{rmse}}·J_{\mathrm{norm},i}+w_{\mathrm{time}}·T_{\mathrm{norm},i}$$

(24)

In this context, $w_{\mathrm{rmse}}=0.6$ and $w_{\mathrm{time}}=0.4$ indicate the specific weights assigned to model precision and computational cost, respectively. This approach aims to achieve a balanced calibration for the physical DAB converter, while still emphasizing accuracy. The scenario that resulted in the lowest composite score $S_i$ was systematically identified as the optimal tuning compromise for each algorithm.

Figure 10 presents a final comparison of the performance in the selected scenarios across the four metaheuristic algorithms, reporting the definitive $\mathrm{NRMSE}$ on the left vertical axis and the execution time on the right vertical axis. The profiles demonstrate that the PSO and SBOA algorithms achieve the most accurate parameter estimation, both converging to a similar minimum error $\mathrm{NRMSE}\approx 2.7\%$. However, their computational requirements are significantly different. The SBOA framework requires approximately 23.3 h of runtime. In contrast, the PSO algorithm effectively balances performance and cost, achieving the same level of accuracy in just 5.9 h. While the GWO and WOA frameworks converge in short times, they struggle to identify the global optimal parameters, resulting in higher final error margins of 2.78% and 2.85%, respectively. These results provide clear mathematical evidence that the PSO framework, when optimized for the selected scenario, offers the most balanced, robust, and computationally efficient solution for the digital twin identification of the DAB converter.

Figure 10. Performance Comparison of the Best Tuning Scenario for the DAB converter.

To provide an additional comprehensive understanding of the methods trade-offs, Figure 11 presents a multi-criteria radar chart that evaluates five standardized performance dimensions for each optimal configuration [44,45]. The polygon shapes in the chart illustrate the operational effectiveness of each technique, which is defined and quantified as follows:

Figure 11. Multi-criteria radar assessment evaluating the qualitative footprints (Accuracy, Speed, Consistency, Exploration, and Stability) for the best sintonization scenario of each algorithm.

• Accuracy: measures the absolute proximity of the estimated parameters to the global minimum, quantified as the inverse of the minimum achieved $\mathrm{NRMSE}$ to evaluate the reduction of steady-state mismatch.
• Consistency: evaluates the numerical robustness and repeatability of the solver, computed as the inverse of the standard deviation ($\sigma$) of the final objective function values across the independent scenarios.
• Exploration: reflects the global search coverage and population diversity during early stages, quantified by tracking the average spatial dispersion among the candidate agents during the initial iterations.
• Speed: represents the computational efficiency of the metaheuristic routine, calculated as the inverse of the average convergence time required to satisfy the execution termination criteria.
• Exploitation: measures the local refining capability for fine-tuning the solution vector, evaluated through the rate of improvement of the best fitness score during the final convergence phase.

The SBOA algorithm maximizes the areas corresponding to Accuracy, Consistency, and Exploration, demonstrating its exceptional ability to find and refine the global minimum, yet its footprint shrinks significantly along the Speed axis. In contrast, the GWO and WOA frameworks show a strong tendency towards the Speed dimension but drop significantly into the Poor and Fair categories for stability and precision. The PSO framework, on the other hand, demonstrates the most balanced polygon geometry. It receives an ’Excellent’ rating for both ’Accuracy’ and ’Stability,’ while also maintaining an ’Acceptable’ level of computational speed. Consequently, both the mathematical and qualitative results confirm that the PSO framework offers the most balanced, robust, and computationally efficient configuration for identifying the DAB converter parameters.

Figure 12 illustrates the percentage deviation of the identified parameters from their nominal theoretical baselines, emphasizing the sensitivity of each metaheuristic framework. For most passive core components ($L_m$, $L_p$, $R_o$, and n) all four algorithms converge within ±5%, demonstrating the structural robustness of the underlying nonlinear model. In contrast, a significant and general positive deviation is observed for the leakage inductance ($L_k$) and the output filtering capacitance ($C_H$). This deviation is attributed to a combination of manufacturing tolerances, unmodeled board parasitics, and limitations in the algorithms’ convergence.

Figure 12. Parametric tolerance heatmap illustrating the directional average deviation ($\Delta \%$) from nominal manufacturer values across all experimental scenarios for each optimization algorithm.

Finally, Figure 13 provides a detailed view of the distribution of the identified physical parameters. PSO demonstrates a good balance between low dispersion and proximity to the nominal values, indicating consistent parameter estimation. In contrast, SBOA and WOA exhibit wider distributions in several parameters, especially in those with higher sensitivity such as $L_k$ and $R_{D_H}$. This increased variability suggests reduced reliability in capturing the physical behavior of the system.

Figure 13. Identified Physical Parameter Distributions. Dotted lines represent the nominal values present in Table 1, red crosses represent outliers, and the solid horizontal lines within the boxes indicate the median values.

Table 4 shows the cross-validation performance of the model, evaluated using the optimal parameter set identified at $\delta ={70}^{\circ }$ across multiple operational phase shift angles. Those results show that although the model retains a high level of accuracy close to the parameterization point, with an overall NRMSE of $22.45\%$ at $\delta ={60}^{\circ }$, the discrepancy in estimation rises at the edges of operation. Specifically, at $\delta ={120}^{\circ }$, the output voltage ($V_o$) NRMSE rises to $106.66\%,$ resulting in a deviation between the experimental $RMS$ values and the simulation data. These results show that a single global parametric configuration is insufficient to account for the non-linear/high-frequency variations across its entire operating range, thereby stressing the limitations of static global identification.

Table 4. Cross-Validation Performance and Multi-Variable Error Footprint Metrics Across Different Phase Shift Angles ($\delta$).

Metric/Variable		${45}^{\circ }$	${60}^{\circ }$	${70}^{\circ }$	${120}^{\circ }$	${135}^{\circ }$
General Metrics	NRMSE $I_{LP}$ (%)	3.48	4.20	1.27	2.77	3.75
	NRMSE $I_{LK}$ (%)	3.09	2.55	1.16	18.92	16.28
	NRMSE $V_o$ (%)	62.03	37.55	4.45	106.66	53.41
	Total NRMSE (%)	32.15	22.45	2.29	42.78	24.48
$I_{LP}$	RMS Experimental (A)	2.66	3.24	4.46	4.96	4.93
	RMS Simulated (A)	2.70	3.35	4.45	5.22	5.23
$I_{LK}$	RMS Experimental (A)	0.70	0.95	1.32	1.35	1.26
	RMS Simulated (A)	0.94	1.22	1.32	1.56	1.45
$V_o$	Mean Experimental (V)	41.90	47.96	51.11	42.90	34.96
	Mean Simulated (V)	41.59	47.71	51.11	41.91	35.45

Therefore, the parameters were identified for each operation point. Table 5 reports the identified real physical parameters of the DAB converter across the evaluated phase shift angles ($\delta$), providing a direct mapping of the hardware state and demonstrating that key structural parameters, such as the transformer turns ratio ($n\approx 6.0$), the primary DC-link filter capacitance ($C_H=26.40\mathsf{\mu }\mathrm{F}$), and the input resistance ($R_{\mathrm{in}}$), exhibit remarkable numerical stability throughout the entire operational range. This constant convergence demonstrates that the PSO algorithm effectively tracks the actual physical constants without suffering from numerical overfitting. In contrast, a highly dynamic, operating-point-dependent variation is observed in the high-frequency parasitic resistances and the coupled leakage inductance ($L_k$), which fluctuates between $3.81\mathsf{\mu }\mathrm{H}$ ($\delta ={70}^{\circ }$) and $6.99\mathsf{\mu }\mathrm{H}$ ($\delta ={60}^{\circ }$).

Table 5. Identified Real Physical Parameters for the DAB Converter via Vertical Parameter-by-Parameter Matrix Mapping.

Physical Parameter	Operational Phase Shift Angle $\mathit{\delta }$
	${\mathbf{45}}^{\circ }$	${\mathbf{60}}^{\circ }$	${\mathbf{70}}^{\circ }$	${\mathbf{120}}^{\circ }$	${\mathbf{135}}^{\circ }$
$R_{\mathrm{in}}(\Omega )$	0.44	0.52	0.46	0.60	0.47
$C_L\left(\mathsf{\mu }\mathrm{F}\right)$	17.60	17.60	21.88	17.70	17.60
$R_{C_L}(\mathrm{m}\Omega )$	4.35	6.00	6.01	5.58	5.41
$R_{D_L}(\mathrm{m}\Omega )$	30.00	29.43	26.08	30.00	29.21
$L_p\left(\mathsf{\mu }\mathrm{H}\right)$	23.06	21.98	22.77	26.40	23.91
$R_{L_p}(\mathrm{m}\Omega )$	2.75	1.98	2.65	2.75	2.28
$L_m\left(\mathsf{\mu }\mathrm{H}\right)$	487.40	490.10	515.15	550.00	450.60
$R_{L_m}(\mathrm{m}\Omega )$	21.98	22.00	18.90	21.96	21.98
$L_k\left(\mathsf{\mu }\mathrm{H}\right)$	6.27	6.99	3.81	5.54	5.76
$R_{L_k}(\mathrm{m}\Omega )$	353.10	353.10	323.18	353.07	353.07
$R_{D_H}(\mathrm{m}\Omega )$	48.00	48.00	41.13	47.99	48.00
$C_H\left(\mathsf{\mu }\mathrm{F}\right)$	26.40	26.40	26.40	26.40	26.40
$R_{C_H}(\mathrm{m}\Omega )$	6.47	6.47	4.80	6.47	5.01
$R_o(\Omega )$	108.39	106.66	106.22	129.01	112.35
n	6.02	6.06	5.98	6.03	5.96

Table 6 presents the tracking performance metrics for each phase-shift angle ($\delta$). This new process provides a significant reduction in tracking errors compared to the previous cross-validation analyses, specifically, at $\delta ={120}^{\circ }$, this localized calibration effectively decreases the output voltage ($V_o$) NRMSE from $106.66\%$ to $8.42\%$, where the total collective error is reduced to $5\%$. The targeted local optimization ensures consistently low error rates across the entire operating range by eliminating operating-point-dependent non-linearities, semiconductor switching delays, and magnetic variations in the physical DAB converter.

Table 6. Performance and Multi-Variable Error Metrics Obtained via Independent Local Parameter Optimization for Each Phase Shift Angle ($\delta$).

Metric/Variable		${45}^{\circ }$	${60}^{\circ }$	${70}^{\circ }$	${120}^{\circ }$	${135}^{\circ }$
General Metrics	NRMSE $I_{LP}$ (%)	2.81	3.90	1.27	3.78	2.51
	NRMSE $I_{LK}$ (%)	2.84	2.60	1.16	2.81	2.02
	NRMSE $V_o$ (%)	3.94	4.35	4.45	4.21	2.92
	Total NRMSE (%)	3.20	3.62	2.29	3.60	2.48
$I_{LP}$	RMS Experimental (A)	2.66	3.24	4.46	4.96	4.93
	RMSE Simulated (A)	2.68	3.42	4.45	4.50	4.96
$I_{LK}$	RMS Experimental (A)	0.70	0.95	1.32	1.35	1.26
	RMSE Simulated (A)	0.72	1.03	1.32	1.36	1.34
$V_o$	Mean Experimental (V)	41.90	47.96	51.11	42.90	34.96
	Mean Simulated (V)	41.90	47.96	51.11	42.90	35.45

The model accuracy is validated using a parametric analysis performed to the tracking errors across all core variables, which is summarized in Table 7. The primary-side current $i_{L_p}$, the leakage inductor current $i_{L_k}$, and the output capacitor voltage $v_{C_H}$ exhibit sample means of $2.85\%$, $2.29\%$, and $7.50\%$, respectively, with low standard deviations. Under a two-tailed t-Student distribution with four degrees of freedom and a $95\%$ confidence level ($\alpha =0.05$), the operational boundaries restrict the expected error variance within narrow margins, such as $[1.53\%,4.18\%]$ for the primary current and $[3.2\%,4.74\%]$ for the Output Voltage. A one-sample t-test was performed with a conservative tolerance threshold of $H_0$:${\mu }_0\ge 5.0\%$, which establishes the baseline for high-fidelity real-time emulation; hence, reporting a rejection of $H_0$ across all indicators, with strong statistical significance. The p-values were $0.0117$ for $i_{L_p}$, $0.0005$ for $i_{L_k}$, and an overall system significance of $0.0010$ for the average total metric. This statistical validation demonstrates that the low error achieved through the optimization process accurately reflects the converter’s true physical dynamics, thereby ensuring the model’s robustness.

Table 7. Confidence Intervals and Statistical Significance Parameters ($n=5$, $\alpha =0.05$).

Statistical Metric	Primary Current ${\mathit{i}}_{{\mathit{L}}_{\mathit{p}}}$	Leakage Current ${\mathit{i}}_{{\mathit{L}}_{\mathit{k}}}$	Output Voltage ${\mathit{v}}_{{\mathit{C}}_{\mathit{H}}}$	Total Averaged NRMSE
Sample Mean ($\overline{x}$)	$2.85\%$	$2.29\%$	$7.50\%$	$4.21\%$
Standard Deviation (s)	$1.07\%$	$0.71\%$	$1.21\%$	$0.92\%$
Standard Error (SEM)	$0.48\%$	$0.32\%$	$0.54\%$	$0.41\%$
Computed t-Statistic	$-4.48$	$-8.54$	$-3.71$	$-7.07$
95% Confidence Interval	$[1.53\%,4.18\%]$	$[1.40\%,3.17\%]$	$[3.20\%,4.74\%]$	$[2.27\%,3.81\%]$
Null Hypothesis ($H_0$)	${\mu }_0\ge 5.0\%$	${\mu }_0\ge 5.0\%$	${\mu }_0\ge 5.0\%$	${\mu }_0\ge 5.0\%$
Significance (p-value)	$0.0117$	$0.0005$	$0.0103$	$0.0010$

2.3. Model Validation

The validation of the identified parameters is performed by evaluating the model equations in both time and frequency domains under the nominal operating point of $\delta ={70}^{\circ }$. First, Figure 14 illustrates the time-domain comparison between the experimental waveforms and the simulated trajectories using the optimal parameter set from Table 5. The tracking metrics demonstrate a satisfactory agreement, yielding a $\mathrm{NRMSE}$ of $1.27\%$ for the primary-side external inductor current ($i_{L_P}$), $1.16\%$ for the leakage inductor current ($i_{L_k}$), and $6.67\%$ for the filtered output voltage ($V_o$). These low error values confirm that the localized parameter identification successfully captures the high-frequency switching ripple and the steady-state behavior of the DAB converter.

Figure 14. Waveform comparison between experimental data and the optimized model at the nominal operating point ($\delta ={70}^{\circ }$), plotted against the data sample index (10,000 samples).

To execute these dynamic validation tests, the experimental platform use a TMS320F28335 microcontroller to modulate the phase shift $\delta$ between the two bridges. The microcontroller Analog-to-Digital Converter (ADC) operates at a sampling rate of 12.5 MSPS, and the digital phase command ${\delta }_{dig}$ is computed through the linear transformation defined in (25), where the slope $m=0.153$ and intercept $b=415.653$ are selected to achieve a phase variation of $\pm 5\%$. This phase value is updated synchronously via an interruption routine at the end of each PWM cycle, commanding two complementary 50% duty cycle gating signals at a fixed switching frequency of $f_{sw}=20\mathrm{kHz}$.

$${\delta }_{dig}=m·\mathit{ADC}+b$$

(25)

For the frequency-domain characterization, small-signal sinusoidal perturbations are injected into the phase shift around the nominal ${70}^{\circ }$ baseline using a Venable Frequency Response Analyzer (FRA) Model 6320 [46], as illustrated in Figure 15. The FRA output incorporates a DC offset of $V_{DC}=1.5\mathrm{V}$ to comply with the unipolar input range of the microcontroller ADC, along with a peak AC perturbation amplitude of $V_{AC,peak}=0.5\mathrm{V}$. To protect signal integrity against switching noise, the FRA performs a logarithmic frequency sweep from $f_{start}=100\mathrm{Hz}$ to $f_{stop}=2\mathrm{kHz}$, which corresponds to a decade below $f_{sw}$, utilizing $N_{steps}=20$ points per decade and integrating the responses over $N_{cycles}=5$ cycles. The final experimental Bode diagram is computed from the output-to-input ratio, applying a correction factor of $G_{corr}=0.1$ to compensate for the attenuation of the voltage sensing circuitry.

Figure 15. Experimental setup for the small-signal frequency domain validation test.

To evaluate the model performance, the frequency response of the optimized model is generated by implementing the system differential equations within a specialized C-block environment. The simulation reproduces the experimental frequency analysis using an AC Sweep block configured with an excitation amplitude of $A_{exc}=0.5$ over 51 points from $100\mathrm{Hz}$ to $2\mathrm{kHz}$. For mathematical consistency with the physical setup, the linear scaling of (25) is mapped into the simulation environment with parameters $m=0.045$ and $b=0.15$.

Figure 16 reports the comparison between the experimental frequency response and the model simulation. The results demonstrate a strong agreement across the entire validated band, achieving an average magnitude error of 1.03% and a phase deviation of 6.31%. This precise correlation across both time and frequency domains confirms that the optimized model accurately characterizes both the high-frequency switching ripples in the time domain and the small-signal dynamic behavior under perturbation, establishing a reliable foundation for control systems design.

Figure 16. Frequency-domain comparison between the experimental FRA response and the optimized model.

3. Digital Twin for Hardware-in-the-Loop Tests

A real-time digital twin of the DAB converter is developed using an optimized parameter set that serves as the mathematical foundation for HIL emulation. To accurately capture the converter’s high-frequency switching dynamics, the digital twin operates at the absolute limits of the embedded microcontroller’s integration period $T_s$, which is not a constant; instead, it is affected by the computational complexity of the chosen integration algorithm. To minimize this time, it is essential to have an execution window to avoid aliasing-induced subharmonic oscillations, which often occur on HIL platforms when the input sampling time approaches the converter’s switching period. Therefore, it is required a high oversampling ratio, or the implementation of complex sub-step integration techniques to accurately resolve discrete switching events and reconstruct a representative binary input for the model without modifying the plant structure [47]. Within this execution framework, each integration method requires a particular minimum execution time to suppress sub-harmonic components before step-overruns occur.

To determine the optimal trade-off between micro-architectural execution complexity and transient tracking accuracy, this digital twin framework evaluates four explicit numerical integration schemes: Forward Euler, Trapezoidal (Tustin), 2nd-order Runge–Kutta (RK2), and 4th-order Runge–Kutta (RK4). While multi-stage implicit methods offer superior numerical stability under larger step sizes, real-time power electronics emulation require explicit formulations to guarantee deterministic execution boundaries within the microcontroller clock cycles. The discrete-time recursive equations for the Trapezoidal, RK2, and RK4 frameworks are detailed in Appendix B.

The state-space discretization process yields a compact mathematical structure that updates at each sampling instant. The state vector is defined as $\mathbf{x}\left(n\right)={\left[x_1\left(n\right)x_2\left(n\right)x_3\left(n\right)x_4\left(n\right)\right]}^T$, where the variables correspond to the physical elements of the DAB converter, including the low-voltage filter capacitor voltage $v_{C_L}$, the high-voltage capacitor voltage $v_{C_H}$, the primary-side external inductor current $i_{L_p}$, and the transformer leakage inductor current $i_{L_k}$. The input vector is denoted as $\mathbf{u}\left(n\right)=\left[u_1\left(n\right)\right]$, representing the input DC-link voltage. Taking the Forward Euler approximation as the computational baseline, the discrete-time state-space system is formulated as follows:

$$\mathbf{x}\left(n\right)=\left[\mathbf{I}+T_s\mathbf{A}(s_1,s_2)\right]\mathbf{x}(n-1)+T_s\mathbf{B}(s_1,s_2)\mathbf{u}(n-1)$$

(26)

where $\mathbf{I}$ is the identity matrix, while $\mathbf{A}(s_1,s_2)$ and $\mathbf{B}(s_1,s_2)$ denote the continuous-time state and input matrices, respectively, which are dynamically updated according to the discrete switching functions $s_1$ and $s_2$.

3.1. Model-Based Architectural Design and System Requirements

The HIL platform was designed using the Model-based development (MBD) philosophy. MBD is an engineering paradigm that shifts the focus of activity from “coding from documentation” to “modeling from formal specification”. Instead of using static textual or schematic descriptions, MBD promotes the construction of executable models that act as a single source of truth throughout the entire life cycle: requirements analysis, architectural design, simulation, automatic code generation, integration testing, and maintenance. This approach reduces semantic ambiguity, facilitates early verification of functional and non-functional properties, and enables bidirectional traceability between customer requirements and software/hardware artifacts [48,49].

The systematic adoption of architectural models in HIL platforms has been shown to reduce integration time between 2 and 3 times [50,51]. The ability to run “virtual simulations” of the HIL bench before soldering the first component enables detection of dynamic-range incompatibilities, ADC saturation, or latency violations at a cost several orders of magnitude lower than in the physical prototype. Architectural modeling is the fundament of model-based development, providing a common, formal, and executable language. In the field of power electronics, where microseconds of delay or millivolts of noise determine the success of a product, having a well-defined architecture from the initial stages is not an option; it is a necessary condition for the HIL bench to be a true reflection of reality rather than a source of misleading conclusions.

3.1.1. System Architecture

The system architecture is modeled with three components (see Figure 17). The central element of the converter’s real-time simulation architecture is the HILPlatform component. This component is responsible for materializing the electromagnetic dynamics of the DAB converter, including losses, through real-time numerical resolution of its switched model. The component is reusable and can accommodate different converter parameterizations without modifying its physical architecture, limited only to updating its internal coefficients via the defined input interface (ElectricalParameters). The input matrix (ElectricalParameters) constitutes the complete configuration vector that parameterizes the mathematical model of the DAB converter. Its structure is organized into four matrices with the values described in Table 5: inductances (3 × 1 matrix); capacitances (2 × 1 matrix); loss resistances (8 × 1 matrix); and load (1 × 1 matrix).

Figure 17. HIL platform architecture based on a component diagram.

The PWMSignals port, a 2 × 1 Boolean signal matrix, serves as the control interface for the emulated converter, receiving trigger signals for the semiconductors of both active bridges in the DAB converter. Its purpose is to capture the switching state imposed by the external controller, determining the instantaneous topological configuration of the circuit and, consequently, the direction and magnitude of the power flow. The first element of the matrix, PWMSignals(1,1), represents the conduction state of the MOSFETs in the low-side bridge (the primary side of the transformer). The second element, PWMSignals(2,1), represents the conduction state of the high-side bridge MOSFETs (transformer secondary side). The combination of those two binary states defines the four topological configurations of the converter shown in Figure 3.

The state vector SV is the output interface, and it contains the four independent dynamic variables that fully describe the energy configuration of the DAB converter at any given moment in time. Its evolution over time, governed by the discretized state equations, constitutes the primary output of the simulation: primary inductor and magnetizing inductor currents (2 × 1 matrix); input capacitor and output capacitor voltages (2 × 1 matrix).

The mathematical model constitutes a fourth-order state representation derived from the continuous-time differential equations governing the converter’s four state variables, including the voltages across the input and output filter capacitors, the current flowing through the power transfer inductor, and the current in the equivalent magnetizing inductance of the isolation transformer. To evaluate the micro-architectural trade-offs of the real-time emulation, this continuous framework is mapped into four distinct discrete-time execution structures. Taking the Forward Euler discretization as the computational baseline, the state increment is updated at each sampling instant according to $\mathbf{x}\left(n\right)=\left[\mathbf{I}+T_s\mathbf{A}(s_1,s_2)\right]\mathbf{x}(n-1)+T_s\mathbf{B}(s_1,s_2)\mathbf{u}(n-1)$, where $T_s$ represents the integration period governed by the algorithm complexity, and $\mathbf{u}(n-1)$ encapsulates the discrete states of the external PWM control signals. This baseline formulation is systematically compared against the Trapezoidal, RK2, and RK4 recursive structures to determine the optimal balance between tracking precision and computational burden.

The Digital-to-Analog Converter (DAC) component is configured as the essential translator between the discrete computational domain of the simulation model and the continuous analog domain for control and observation. Its status as a signal conditioning node reflects its specific function: transforming digital numerical representations into electrical voltage signals that can be processed by external ADCs.

The RSV port is the interface for receiving data from the digital simulation domain, specifically from the HILPlatform component. Its purpose is to capture a reduced projection of the complete state vector of the DAB converter model, adapted by selection and quantification to the capabilities of the analog conversion hardware. The RSV matrix is derived from the SV state vector (4 × 1 matrix) generated by the HILPlatform through an adaptation process, which selects two specific variables (2 × 1 matrix, using the Adapter element) and represents them in 8-bit integer format, optimizing the bandwidth of the physical interface and the DAC conversion speed.

The High-sideCapacitorVoltage port of the Adapter implements the analog reconstruction of the first element in the RSV vector, i.e., the voltage of the high-side capacitor in the DAB converter, scaled to the operating range of the ControllerHardware’s analog-to-digital converter. Its purpose is to close the physical control loop: to provide a continuous electrical representation of the controlled variable that the controller can sample, quantify, and use to compute its regulation action. Scaling to the 0–3.3 V range establishes electrical compatibility with the typical analog-to-digital converters found in modern industrial and automotive microcontrollers. This signal is the only critical analog link in the control loop; its integrity directly determines the quality of the emulated converter’s output-voltage regulation. This port architecture allows the DAC to operate as a transparent boundary between domains: it preserves essential information about the state of the emulated converter (output voltage) in a format that the controller can process, while keeping a second variable available for diagnostic observation, thus enabling experimental validation of the model without compromising the determinism of the control loop.

The ControllerHardware component is the core of the HIL control loop, implementing the DAB converter’s voltage regulation strategy using a PI compensator with a classic structure. The hardware/software condition reflects its dual nature: a physical computational infrastructure (processor, peripherals such as ADC and PWM) that houses a software artifact consisting of the difference equations of the PI controller. This controller iteratively computes the proportional control action (instantaneous response to the error) and the integral control action (accumulation of historical error), adding both to obtain the phase-shift value. This calculated phase shift is implemented in digital trigger signals for the semiconductors of both DAB bridges, generating the modulation required by the converter emulated in the HILPlatform to transfer the required power and maintain the output voltage at its reference value.

The High-sideCapacitorVoltage port serves as the feedback interface for the control loop, receiving the scaled analog representation of the voltage across the output capacitor of the emulated DAB converter. Its purpose is to provide the controller with the status information necessary to compute the regulation error: the difference between the voltage reference value (set point) and the measured value (feedback). The analog signal in the 0–3.3 V range is digitized by the ControllerHardware ADC, yielding a discrete numerical representation that the control algorithm processes. The correspondence between the analog voltage level and the physical voltage value in the DAB converter is established by a known scaling factor, which the controller software applies to recover the physical magnitude before calculating the error.

The PWMSignals port constitutes the control loop’s actuation interface, emitting trigger signals to the semiconductors of both active bridges in the DAB converter. Its purpose is to implement the control action calculated by the PI compensator, translating the phase shift into precise temporal transitions of the digital signals that govern the switching of the emulated converter. The phase shift between PWMSignals(1,1) and PWMSignals(2,1) determines the magnitude and direction of the power transferred through the DAB converter. A zero shift implies zero power transferred; a positive shift (high-side signal delayed relative to low-side) implies power transfer from primary to secondary; and a negative shift implies reverse transfer. The PI compensator dynamically adjusts this value to maintain the output voltage at its reference value, compensating for load disturbances.

The two ports on the ControllerHardware establish a closed-loop control system that regulates the operation of the emulated DAB converter. This architecture allows the component to operate as an autonomous regulator: it receives measurements of the controlled variable (High-sideCapacitorVoltage), executes the control algorithm, and emits actuation signals (PWMSignals) that modify the behavior of the emulated plant, thereby closing the voltage regulation loop of the DAB converter. This explicit definition of interfaces, using component-based system architecture modeling, establishes a formal framework that facilitates integration with computer-aided design tools, automatic code-generation platforms, and systematic testing environments, aligning its structure with the best practices for designing critical complex systems. Finally, a summary of the system architecture components is provided in Table 8.

Table 8. Architectural components and their characteristics.

Component	Type	Architectural Category	Level of Abstraction
HILPlatform	Hard./soft.	Physical plant simulation—computational node	Execution platform of the discretized mathematical model
DAC	Hard.	Signal conditioning node, mixed-signal border interface	Digital-to-analog conversion—hardware component
ControllerHardware	Hard./soft.	Computing node for real-time control	Execution platform of the discretized control algorithm

3.1.2. Definition of System Requirements

The specification of requirements is the first step in any development cycle that aims to combine reliability, cost, and deployment time. In the field of hardware/software systems, this stage is even more important than in purely software projects, since errors detected once the PCB has been made or the firmware has been implemented in ROM not only make the product more expensive, but can also compromise the safety of people and equipment. Therefore, a clear and quantifiable definition of functionality, performance, interfaces, and restrictions, is essential for successful hardware products.

In the particular case of HIL platforms dedicated to power management, converters like the DAB operate with dynamics of tens of kilohertz, with voltage transitions of hundreds of volts in tens of nanoseconds, and with control loops whose phase margin can be lost due to simple microsecond delays. Any poorly dimensioned requirement (model update frequency, DAC resolution, PWM chattering, CPU latency) introduces distortions that translate into apparent gains in the compensator, non-existent resonances, or unstable behavior when control is migrated to the actual prototype. Therefore, rigorous specification bridges the gap between the mathematical model and observable behavior. Figure 17 shows the requirements that each architecture component implements, which are described below.

Properties of the DAB converter model: this requirement imposes that the model must be switched, since, unlike averaged models, it accounts for the actual behavior of the semiconductor switches, allowing the observation of current and voltage ripple, as well as the effects of phase shift in each switching cycle. In addition, representation in a discrete state space using the Forward Euler method has the advantage of lower computational cost, since it is an explicit method that allows a constant and very small step size.

HIL platform hardware features: Defines the essential aspects to characterize a computational node for model simulation. In this case, a processor was selected, and the requirements for computing power (CPU), memory, and peripherals were defined.

The discrete state space model given in (26) corresponds to a time-varying switched system, in which $u_1\left(n\right)\in {\Re }^1$, $x\left(n\right)$ and $T_s·B_d(s_1,s_2)\in {\Re }^{4\times 1}$, and $I+T_s·A_d(s_1,s_2)\in {\Re }^{4\times 4}$. Solving this system requires approximately 36 floating point operations (FLOPs) for calculation and 42 integer operations (IOPs) for data management and flow control. Due to its proven performance and market availability, an ARM Cortex-M7 processor is selected. This CPU must have a floating-point unit (FPU) with VFPv5 capability (support for fused multiply-accumulate operations) and an IPC (instructions per cycle) of 2 for 50% of the time. In this case, the total number of instructions per simulation step is approximately 64 (22 FLOPs due to the FPU’s fused multiply-add and 42 IOPs). Considering a maximum switching frequency of 100 kHz and an average IPC of 1.5, the processor clock frequency must be approximately 427 MHz, so 450 MHz is established as the minimum CPU frequency requirement. Moreover, DMA (direct memory access) channels are used to transfer system states to memory without CPU intervention.

Memory requirements are defined to enable the platform to emulate higher-order converters, such as interleaved converters, and to align with the market that offers RAM and Flash memory in embedded systems based on the selected processor.

To define the requirements for the computational node peripherals, the inputs and outputs of the converter to be emulated must be considered: two PWM signals up to 100 kHz and two parallel 8-bit outputs (representing the two states to be monitored). For the TIM (Timer Module), a resolution of 1% of the phase shift at the operating point is required, i.e., ${0.7}^{\circ }$. For a converter switching at 20 kHz, the time resolution is around 100 ns, so the minimum frequency of the TIM must be around 20 MHz. A 16-bit register is sufficient, along with capture inputs for the PWM control signals. The parallel output must have 16 pins, 8 for each state variable, updated at the DAB converter model’s calculation speed.

Properties of DAC: The DAC is the connection between the digital and analog frameworks, whose function is to convert 32-bit floating-point digital data into an analog signal in the range of 0 to 3.3 V. The DAC used is an R-2R type with an 8-bit parallel interface, and since the model generates new data every 100 ns, a settling time of at least 50 ns is required, so that high-frequency transitions are not filtered. In order to achieve a 3.3 V excursion in less than 50 ns, a minimum slew rate of 100 V/$\mathsf{\mu }$s is required. In addition, to keep the DNL (Differential Non-Linearity) and INL (Integral Non-Linearity) within tolerable ranges, the tolerance of the resistors must be 0.1%.

Controller features for testing the DAB converter model: The requirements for the controller to be used in the model validation are those of a classic PI voltage controller, for which overshoot and transient response settling time are defined. The controller must be designed based on a control-oriented DAB converter model, which is a first-order small-signal model with an 8th-order harmonic approximation of the PWM signals that control the converter bridges.

Controller hardware characteristics: the controller hardware must guarantee determinism and minimal latency. To do this, it must execute the PI algorithm at a sampling frequency at least equal to the converter’s switching frequency, in the most extreme case, 100 kHz. A 32-bit FPU is essential, as the controller constants are large and working with fixed point will cause severe truncation errors in the integral accumulator. A CPU operating at a frequency higher than 100 MHz ensures that the PI controller’s calculation time is negligible compared to 10 $\mathsf{\mu }$s, the minimum switching period. For this simple controller, 16 kB of RAM and 64 kB of Flash are sufficient. In terms of peripherals, an ADC with 12-bit resolution and a sampling frequency of 1 MSPS is required, with synchronization to sample at the midpoint of the PWM signal to avoid switching noise. Two PWM channels with ${0.7}^{\circ }$ phase resolution and updating cycle according to the changes calculated by the PI controller.

The previous requirements are summarized in Table 9.

Table 9. Summary of validation and testing platform requirements.

Requirement	Features	Implemented by
Properties of the DAB converter model	Model type @ switched; discretization method @ fordward Euler	HILPlatform
HIL platform hardware feature	CPU spec.: ARM-Cortex-M7 @ ≥450 MHz; IPC 2@50%; FPU-VFPv5; DMA @ 4 stream	HILPlatform
	Memory spec.: RAM @ ≥ 320 kB; Flash @ ≥ 1 MB	HILPlatform
	Peripheral spec.: TIM @ 16-bit, resolution @ ≤ 20 ns, channels 2 @ IC; 16-channels GPIO @ ≥ 10 MHz	HILPlatform
Properties of DAC	@ R-2R; interface @ parallel; resolution @ 8-bit; settling-time @ < 50 ns; out voltage range @ 0–3.3 V; INL/DNL @ < ±0.5/±0.25 LSB; slew-rate @ > 100 V/µs	DAC
Controller features for testing the DAB converter model	Model version @ control-oriented; controller type @ classical voltage PI; max. overshoot @ 10%; settling-time @ ≤ 20 ms	ControllerHardware
Controller hardware features	CPU spec.: CPU @ 32-bit; frequency @ 150 MHz; FPU @ IEEE-754 SP; DMA @ 2-channels	ControllerHardware
	Memory spec.: RAM @ ≥ 64 kB; Flash @ ≥ 256 kB	ControllerHardware
	Peripheral spec.: ADC resolution @ ≥ 12-bit; ADC-channels @ ≥ 2; PWM type @ high-resolution; PWM channels @ ≥ 2	ControllerHardware

3.2. Real-Time HIL Experimental Implementation and Verification

For the physical validation of the real-time emulation, the digital twin is deployed on a Teensy 4.1 microcontroller operating at a stable overclocked frequency of $1\mathrm{GHz}$ to maximize computational throughput. The emulation bench receives two external, phase-shifted PWM signals generated by the TMS320F28335 microcontroller, reproducing the nominal operating point of $\delta ={70}^{\circ }$ with a switching frequency of $f_{sw}=20\mathrm{kHz}$ ($T_{sw}=50\mathsf{\mu }\mathrm{s}$). This angular displacement corresponds to a strict time delay of $9.7\mathsf{\mu }\mathrm{s}$ between the bridge activation waveforms. Because the mathematical model operates with binary switching commands (1 or $-1$), the digital input signals captured by the hardware pins are mapped using the discrete transformation $s_x=2u_x-1$ prior to resolving the state-space equations under an input DC-link voltage set to $v_L=12\mathrm{V}$.

To enable real-time visualization and external data acquisition, two independent 8-bit R–2R resistor network DACs [52] are interfaced with the Teensy 4.1 platform using 18 dedicated digital GPIO pins. This mixed-signal link reconstructs the discrete state variables into proportional analog voltage signals. Figure 18 illustrates the complete experimental setup developed for the HIL validation, detailing the signal generation and real-time emulation hardware nodes.

Figure 18. Experimental test bench setup for the real-time HIL platform validation.

To reconstruct these analog representations with precision, a rigorous scaling and quantization procedure is implemented within the microcontroller firmware prior to digital-to-analog conversion. For the current waveforms, a digital offset equivalent to $10\mathrm{A}$ is added to the numerical values of $i_{L_P}$ and $i_{L_k}$ to shift the bipolar AC signals into the strictly unipolar input range of the parallel R–2R DACs. These offset-corrected variables are subsequently normalized against their maximum expected operating peaks and quantized into 8-bit integer streams, yielding static hardware scaling factors of $G_{i_{L_k}}=0.078\mathrm{V}/\mathrm{A}$ and $G_{i_{L_p}}=0.0667\mathrm{V}/\mathrm{A}$.

Figure 19 displays the experimental oscilloscope waveforms captured from this configuration, showcasing the primary-side external inductor current ($i_{L_P}$) and the transformer leakage inductor current ($i_{L_k}$). The reconstructed analog current waveforms exhibit amplitudes of $\pm 160\mathrm{mV}$ for the leakage current representation and $\pm 400\mathrm{mV}$ for the primary-side inductor current. Demodulating the signal by applying the calculated scaling factor for $i_{L_k}$ translates to $\pm 160\mathrm{mV}/G_{i_{L_k}}=\pm 2.05\mathrm{A}$, which maps the experimental current amplitude of the physical DAB converter previously reported in Figure 14 with a minimal relative error of only $20\mathrm{mA}$ ($1\%$). Similarly, decoding the primary current waveform yields $\pm 400\mathrm{mV}/G_{i_{L_p}}=\pm 6.0\mathrm{A}$, effectively reproducing the physical converter baseline with a bounded deviation of $100\mathrm{mA}$ ($1.7\%$).

Figure 19. Experimental HIL time-domain waveforms capturing the primary and leakage currents under nominal phase shift.

To validate the high-voltage dynamic response, the HIL system is reconfigured to export the output filtering capacitor voltage ($v_{C_H}$) to the primary DAC channel under an analog scaling gain of $G_{v_{C_H}}=1.4\mathrm{V}/\mathrm{V}$. The resulting experimental waveform, reported in Figure 20 along with the input PWM gating signals, reveals a steady-state switching ripple amplitude equal to $700\mathrm{mV}$. Demodulating this signal through its scaling matrix results in $700\mathrm{mV}/G_{v_{C_H}}=500\mathrm{mV}$ of physical high-frequency ripple. This valuation closely matches the experimental $490\mathrm{mV}$ ripple recorded on the actual hardware prototype in Figure 14, operating with a restricted tracking error of $10\mathrm{mV}$ ($2\%$).

Figure 20. Experimental HIL time-domain waveforms capturing the high-side capacitor voltage switching ripple.

The precise correlation between these experimental hardware-in-the-loop tests and the physical bench measurements validates the dynamic consistency of the discrete state-space model. Crucially, the phase relationships and cross-coupling dynamics among $i_{L_p}$, $i_{L_k}$, and $v_{C_H}$ are preserved across both platforms, confirming that the optimized parametric digital twin successfully tracks the continuous high-frequency switching trajectories without clipping or numerical divergence, making it fully suitable for real-time closed-loop control stage evaluation.

3.3. Numerical Integration Profile and Accuracy Benchmark

To validate the computational feasibility of the digital twin, the discrete execution profiles were thoroughly benchmarked on the Teensy 4.1 platform running at a stable frequency of $1\mathrm{GHz}$. To measure the physical calculation step ($T_s$) required by each solver, a high-speed digital output pin-toggling technique was used, and the timing was measured with an external oscilloscope. Through this hardware profiling, the baseline Forward Euler scheme exhibited the lowest latency, requiring an execution window of $T_s=172\mathrm{ns}$. Due to the matrix inversion requirements of the implicit Trapezoidal framework, its processing interval scaled up to $T_s=290\mathrm{ns}$. For the multi-stage explicit routines, the two-stage evaluation of the RK2 scheme yielded a step of $T_s=320\mathrm{ns}$, while the comprehensive four-stage calculation of the RK4 algorithm demanded an execution window of $T_s=620\mathrm{ns}$.

To evaluate accuracy under these varying execution rates, the real-time embedded trajectories were benchmarked against a high-fidelity continuous circuit simulation operating at a fixed step size of $10\mathrm{ns}$ using the optimal parameter set of Table 5. A linear interpolation routine was executed to ensure point-to-point temporal alignment before computing the final $\mathrm{NRMSE}$. Table 10 reports the resulting tracking errors for the critical state variables.

Table 10. Real-Time Performance and NRMSE Accuracy Benchmark of the Digital Twin Across Different Integration Schemes.

State	Numerical Integration Scheme and Execution Time (${\mathit{T}}_{\mathit{s}}$)
Variable	Forward Euler	Trapezoidal	Runge–Kutta 2	Runge–Kutta 4
Error	$({\mathit{T}}_{\mathit{s}}=\mathbf{172}\mathrm{ns})$	$({\mathit{T}}_{\mathit{s}}=\mathbf{290}\mathrm{ns})$	$({\mathit{T}}_{\mathit{s}}=\mathbf{320}\mathrm{ns})$	$({\mathit{T}}_{\mathit{s}}=\mathbf{620}\mathrm{ns})$
$i_{L_k}$ (%)	2.33	3.19	4.12	6.47
$i_{L_p}$ (%)	3.12	3.33	4.67	5.97
$v_{C_H}$ (%)	5.08	5.20	5.79	5.84

The numerical metrics show an inverse trade-off between the theoretical mathematical order of the integration scheme and its real-time embedded accuracy. For example, despite the theoretical higher precision provided by multi-stage configurations like RK4, their high computational complexity requires a longer real-time execution times ($620\mathrm{ns}$). This longer calculation time degrades the temporal resolution for sampling the external controller gating signals, introducing aliasing-related duty-cycle quantization errors. Consequently, the explicit Forward Euler baseline achieves the highest tracking precision across all states (Euler calculates almost four points for each RK4 point), including an $i_{L_k}$ error of $2.33\%$ and a $v_{C_H}$ error of $5.08\%$, proving that maximizing the oversampling ratio through ultra-low execution latency is more critical for high-frequency switched HIL emulations than upgrading the polynomial order of the solver.

Table 11 details the micro-architectural memory footprint required by each integration scheme. Within the tightly coupled memory (TCM RAM1), the static variable allocation remains constant at 5408 Bytes. At the same time, the RAM-resident code segment shows only an 8.8% increase, scaling from 7992 Bytes for Forward Euler to 8696 Bytes for RK4. A similar small increment (less than 1 kB) is observed in the FLASH code section. Memory utilization is not a physical constraint for the selected hardware platform, indicating that the selection of the real-time numerical solver must be exclusively defined by tracking accuracy, stability margins, and computational latency.

Table 11. Embedded Memory Footprint Consumption Across the Evaluated Numerical Integration Schemes on the Teensy 4.1 Platform.

Numerical	FLASH Memory (Bytes)			TCM RAM1 Memory (Bytes)
Scheme	Code	Headers	Total FLASH	Variables	Code (RAM)
Forward Euler	10,516	8992	23,548	5408	7992
Trapezoidal	10,788	8720	23,548	5408	8264
Runge–Kutta 2	10,756	8752	23,548	5408	8232
Runge–Kutta 4	11,220	8288	23,548	5408	8696

Commercial low-cost microcontrollers, such as the Teensy 4.1, have advanced to the point where they can effectively execute switched algorithms with high fidelity at a typical DAC switching frequency of 20 kHz. However, as operating conditions shift towards higher frequencies, the computational window narrows, making the multi-stage execution delay of the RK4 method difficult to manage. Additionally, the numerical stability of the Forward Euler method is reduced by accumulated truncation errors generated by the increment of the sampling period ($T_s$). To address those demands in high-frequency converters, the HIL platform can be implemented using multi-core microprocessors with higher clock frequencies, or adopt specialized Field-Programmable Gate Array (FPGA) architectures.

4. Model Simplification for Control-Oriented Applications

The main inputs of the proposed model are the binary activation signals of the MOSFETs, which are required to reproduce the high-frequency switching behavior and ripple dynamics of the converter. However, to design a linear regulation strategy based on the variations of the phase-shift angle ($\delta$) between the two bridges, a control-oriented continuous representation must be derived to explicitly incorporate $\delta$ into the system equations. This mathematical simplification is required to design control strategies with continuous output variables, like classical PI compensators. To transform the switched system into a continuous analytical structure, the discrete switching signals $s_1$ and $s_2$ are expressed as the infinite Fourier series reported in (27) and (28), where n represents the specific harmonic order to be truncated and construct the control-oriented model.

$$\begin{array}{c}\hfill s_1={\displaystyle \frac{4}{\pi }}{\displaystyle \sum _{n=0}^{\infty }}{\displaystyle \frac{1}{[2n+1]}}sin\left([2n+1]{\omega }_{s}t\right)\end{array}$$

(27)

$$\begin{array}{c}\hfill s_2={\displaystyle \frac{4}{\pi }}{\displaystyle \sum _{n=0}^{\infty }}{\displaystyle \frac{1}{[2n+1]}}sin\left([2n+1]({\omega }_{s}t-\delta )\right)\end{array}$$

(28)

Those expressions are substituted into the model Equations (12) and (13), and later transformed into the phasor domain by applying ${\displaystyle \frac{d{i}_L\left(t\right)}{dt}}\to j\omega I_{L_{(2n+1)}}$, which enables the derivation of the time-domain expression for the current $i_{L_k}\left(t\right)$. Such $i_{L_k}\left(t\right)$ equation, and expression (28), are both substituted into Equation (11) to obtain the dynamic expression of the load voltage $v_{C_H}$ reported in Equation (29); the parameters of such an equation are described in (30)–(36).

$$\begin{array}{cc}\hfill {\displaystyle \frac{d{v}_{C_H}}{dt}}=& {\displaystyle \frac{-v_{C_H}}{(C_H·(R_{C_H}+R_o)}}+{\displaystyle \frac{\left(R_o\right)}{(C_H·(R_{C_H}+R_o)}}·\hfill \\ & \left[{\displaystyle \frac{4}{\pi }}{\displaystyle \sum _{m=0}^{\infty }}{\displaystyle \frac{1}{[2m+1]}}sin\left([2m+1]({\omega }_{s}t-\delta )\right)\right]·\\ & \left[{\displaystyle \frac{4}{\pi }}{\displaystyle \sum _{n=0}^{\infty }}{\displaystyle \frac{1}{[2n+1]}}\left[{\displaystyle \frac{(v_{C_L}·k_1+v_L·k_2)}{\left|Z\right[n\left]\right|}}sin([2n+1]{\omega }_{s}t-{\Phi }_z\left[n\right])-\right.\right.\hfill \\ & \hfill \left.\left.{\displaystyle \frac{v_{C_H}·k_3}{\left|Z\right[n\left]\right|}}sin([2n+1]({\omega }_{s}t-\delta )-{\Phi }_z\left[n\right])\right]\right]\end{array}$$

(29)

where

$$\begin{array}{cc}\hfill Z\left[n\right]& =\sqrt{k_4^2+{\left((2n+1){\omega }_s{k}_5\right)}^2}\hfill \end{array}$$

(30)

$$\begin{array}{cc}\hfill {\Phi }_z\left[n\right]& ={tan}^{-1}\left({\displaystyle \frac{(2n+1){\omega }_s{k}_5}{k_3}}\right)\hfill \end{array}$$

(31)

$$\begin{array}{cc}\hfill k_1& =N(R_{C_H}+R_o)(2L_m{R}_{D_L}+L_m{R}_{in}+L_m{R}_{L_p}-L_p{R}_{L_m})\hfill \end{array}$$

(32)

$$\begin{array}{cc}\hfill k_2& =-N(R_{C_H}+R_o)(2L_m{R}_{D_L}+L_m{R}_{L_p}-L_p{R}_{L_m})\hfill \end{array}$$

(33)

$$\begin{array}{cc}\hfill k_3& =-R_{in}{R}_o(L_p{N}^2+L_m)\hfill \end{array}$$

(34)

$$\begin{array}{cc}\hfill k_4=-& R_{in}(2L_m{R}_{C_H}{R}_{D_H}+L_m{R}_{C_H}{R}_{L_k}+L_m{R}_{C_H}{R}_o\hfill \\ & +2L_m{R}_{D_H}{R}_o+L_m{R}_{L_k}{R}_o\hfill \\ & +2L_p{R}_{C_H}{R}_{D_H}{N}^2+L_p{R}_{C_H}{R}_{L_k}{N}^2\hfill \\ & +L_p{R}_{C_H}{R}_{L_m}{N}^2+L_p{R}_{C_H}{R}_o{N}^2\hfill \\ & +2L_p{R}_{D_H}{R}_o{N}^2+L_p{R}_{L_k}{R}_o{N}^2\hfill \\ & +L_p{R}_{L_m}{R}_o{N}^2)\hfill \end{array}$$

(35)

$$\begin{array}{cc}\hfill k_5& =R_{in}(R_{C_H}+R_o)(L_k{L}_m+L_k{L}_p{N}^2+L_m{L}_p{N}^2)\hfill \end{array}$$

(36)

The high complexity of expression (29) makes it impractical for control design. Therefore, applying the methodology described in [53,54], such an expression is simplified as given in (37). Such a simplification consists in neglecting all the sinusoidal terms explicitly dependent on ${\omega }_s·t$ that appear after the Fourier substitution, which represent high–frequency components associated with the switching ripple. Those terms have zero average value over a switching period, thus they do not contribute to the slow dynamics of the output capacitor voltage. By retaining only the difference components that yield slow-dynamic terms, the model is reduced to an expression that captures the low–frequency evolution of $v_{C_H}$ with respect to the phase shift $\delta$, while preserving the nonlinear dependence on the operating point. This non-linear model can be used to design non-linear control systems such as MPC, sliding-mode control, among others.

$$\begin{array}{c}{\displaystyle \frac{d{v}_{C_H}}{dt}}=-{\displaystyle \frac{v_{C_H}}{\left(C_H·(R_{C_H}+R_o)\right)}}+{\displaystyle \frac{2}{\pi }}{\displaystyle \sum _{n=0}^{\infty }}{\displaystyle \frac{1}{{[2n+1]}^2·\left|Z\left[n\right]\right|}}·\hfill \\ \left[{\displaystyle \frac{R_o·(v_{C_L}·k_1+v_L·k_2)}{\left(C_H·(R_{C_H}+R_o)\right)}}·cos\left(-[2n+1]\delta -{\Phi }_z\left[n\right]\right)+{\displaystyle \frac{R_o·\left(v_{C_H}·k_3\right)}{\left(C_H·(R_{C_H}+R_o)\right)}}·cos\left(-{\Phi }_z\left[n\right]\right)\right]\hfill \end{array}$$

(37)

Finally, the previous expression for the capacitor voltage derivative is linearized to obtain the following small-signal transfer function (38), expressed in terms of the phase-shift, which can be used to design classical control systems after being evaluated at a particular operating point.

$${\displaystyle \frac{\Delta v_{C_H}}{\Delta \delta }}={\displaystyle \frac{\left(\left(\frac{2·v_{C_{L_0}}·R_o·k_1}{\left(\pi ·C_H·(R_{C_H}+R_o)\right)}+\frac{2·v_{L_0}{R}_o·k_2}{\left(\pi ·C_H·(R_{C_H}+R_o)\right)}\right)·{\sum }_{n=0}^{\infty }\frac{1}{[2n+1]·\left|Z\right[n\left]\right|}·\left[sin\left(-[2n+1]{\delta }_0-{\Phi }_z\left[n\right]\right)\right]\right)}{\left(s+\frac{1}{\left(C_H·(R_{C_H}+R_o)\right)}-\frac{2·R_o·k_3}{\left(\pi ·C_H·(R_{C_H}+R_o)\right)}{\sum }_{n=0}^{\infty }\frac{1}{{[2n+1]}^2·\left|Z\left[n\right]\right|}·cos\left(-{\Phi }_z\left[n\right]\right)\right)}}$$

(38)

In (38), the variables with subscript “0” represent the linearization operating point. Therefore, $v_{C_{L_0}}$, $v_{L_0}$, and ${\delta }_0$ correspond to the steady-state input capacitor voltage, input source voltage, and phase-shift operating point, respectively, while $\Delta v_{C_H}$ and $\Delta \delta$ denote small-signal perturbations around those equilibrium conditions.

4.1. Transfer Function and Harmonic Order Analysis

The transfer function (38) depends on the converter’s parameters and the variable n, which represents the number of harmonics used to construct the model. To find the minimum number of harmonics providing an accurate representation of the converter’s dynamic behavior, a comparison of the time response with different harmonic values is performed. This analysis considers a unitary step exciting the transfer function, and the resulting time-domain responses are evaluated. Such a process is performed for the following number of harmonics: $n=[0,1,2,3,4,5,6,7,8,9,10,20,40,60,80,100]$.

To derive those small-signal transfer functions, the continuous non-linear model was linearized around the specific nominal operating point defined by an input voltage $v_{C_{L_0}}=12\mathrm{V}$, a regulated output voltage $v_{C_{H_0}}=36\mathrm{V}$, and a steady-state phase-shift angle ${\delta }_0={39}^{\circ }$. Figure 21 illustrates the transfer function responses for the different values of n, where the results converge as n increases. In fact, at higher harmonic orders the responses are superimposed, thus indicating that the model becomes nearly invariant to n at high orders.

Figure 21. Impact of the number of harmonics n into the transfer function.

Figure 22 illustrates the model convergence by comparing the time-domain responses for different values of n with respect to the response obtained with the maximum number of harmonics, i.e., $n_{ref}=100$, which is considered as reference. The comparison is based on the average mean squared difference between the time-domain responses, denoted as $\left|E\left(n,n_{ref}\right)\right|$. The results show that increasing n reduces exponentially the difference with respect to $n_{ref}=100$. From $n\ge 8$, the differences are lower than ${10}^{-2}$ V, and for $n\ge 20$ the errors fall below ${10}^{-5}$ V, indicating that the dynamic behavior of the model remains practically unchanged for higher harmonic orders. Therefore, this work adopts $n=8$, since the model achieves a sufficiently accurate approximation and remains stable and representative of the system’s behavior. Higher n values will increase the computational time without sensible difference reduction.

Figure 22. Model convergence vs. number of harmonics (n).

Evaluating the transfer function (38) with the adjusted parameters of Table 5, and considering a harmonics order $n=8$, results in the following numerical transfer function for the DAB converter, which can be used to design traditional controllers.

$${\displaystyle \frac{\Delta v_{C_H}\left(s\right)}{\Delta \delta \left(s\right)}}={\displaystyle \frac{12.3429}{5.0277·s+1}}$$

(39)

To validate the small-signal dynamics and evaluate the impact of harmonic truncation, five steady-state operating points were selected within the optimal operational region of the DAB converter ($0^{\circ }\le \delta \le {90}^{\circ }$). The experimental characterization was carried out under a constant input voltage of $V_{\mathrm{in}}=12\mathrm{V}$ and a fixed calibration load resistance of $R_o=106.22\Omega$. As summarized in Table 12, the selected test profile spans from a light-load condition at Operating Point 1 ($\delta ={25}^{\circ }$, $P_o=7.38\mathrm{W}$) up to a near-peak nominal load condition at Operating Point 5 ($\delta ={85}^{\circ }$, $P_o=27.15\mathrm{W}$), causing the output voltage to scale non-linearly from $28.00\mathrm{V}$ to $53.70\mathrm{V}$.

Table 12. Steady-State Operating Points of the DAB Converter.

Operating Point	Phase Shift Angle $\mathit{\delta }$ (deg)	Output Voltage (V)	Output Power (W)
1	${25}^{\circ }$	28.00	7.38
2	${40}^{\circ }$	38.62	14.04
3	${55}^{\circ }$	46.50	20.35
4	${70}^{\circ }$	51.00	24.49
5	${85}^{\circ }$	53.70	27.15

During this mathematical validation process, each operating point selected was subjected to six progressive step perturbations defined by $\Delta \delta =[{0.5}^{\circ },1^{\circ },2^{\circ },3^{\circ },4^{\circ },5^{\circ }]$. For each scenario, the transient response of the simplified transfer function was compared point-to-point with the full non-linear model that preserves the time-dependent switching components. This multi-point analysis allows precise quantification of the tracking mismatch induced by the mathematical simplification using the $\mathrm{NRMSE}$, evaluating the accuracy of the small-signal representation under different perturbations in the operation point.

Figure 23 illustrates the tracking performance metrics obtained across the six perturbations for the five selected steady-state operating points (${\delta }_0$). The evaluation of the numerical trends reveals a robust behavior, as the calculated $\mathrm{NRMSE}$ remains limited between $0.21\%$ and $0.43\%$ across the entire perturbation spectrum. The tracking mismatch does not exhibit a proportional degradation as the step amplitude scales from a strict small-signal perturbation ($\Delta \delta ={0.5}^{\circ }$) up to a large dynamic variation ($\Delta \delta ={5.0}^{\circ }$). This uniform error distribution confirms that the simplified transfer functions preserve high predictive accuracy and numerical consistency even under transient conditions that breach typical small-signal assumptions. This test validates the model’s accuracy with harmonic truncation, demonstrating that the simplified model provides a reliable and mathematically stable representation for the design of classical control system across the entire operating range.

Figure 23. Tracking performance across six perturbation sizes ($\Delta \delta$) for five steady-state operating points (${\delta }_0$).

4.2. Example of a Control Design Using the Proposed Linearized Model

This section illustrates the usefulness of the control-oriented version of the model in the design of control systems, hence this procedure is performed considering a classical proportional–integral controller $PI=K_p+K_i/s$.

This example uses the voltage transfer function previously obtained in (39), which has the first-order structure given in Equation (40) with $K=12.3429$ and $\tau =5.0277$.

$$G_{fo\left(s\right)}={\displaystyle \frac{K}{\tau ·s+1}}$$

(40)

Considering a classical closed-loop structure [55], the general closed-loop transfer function is given by $G_{v\delta ,cl}\left(s\right)=\left(G_{fo\left(s\right)}·PI\right)/\left(1+G_{fo\left(s\right)}·PI\right)$, and replacing both $G_{fo\left(s\right)}$ and $PI$ transfer functions results in the following practical $G_{C_L\left(s\right)}$ expression:

$$G_{v\delta ,cl}\left(s\right)={\displaystyle \frac{(K·K_p·s+K·K_i)/\tau }{s^2+((K·K_p+1)/\tau )·s+\left(K·K_i\right)/\tau }}$$

(41)

Based on the canonical form of a second-order system and following the method reported in [56], the proportional and integral gains ($K_p$ and $K_i$) of the $PI$ controller are analytically calculated from the desired performance specifications, namely the maximum overshoot ($OS$, in percentage) and the settling time ($t_s$, in seconds) for a 2% band. The resulting expressions for $K_p$ and $K_i$ are given in Equations (42) and (43), respectively.

$$\begin{array}{c}\hfill K_p={\displaystyle \frac{(2·\pi ·\tau -t_s)}{\left(K·t_s\right)}};t_s\le 2·\pi ·\tau \end{array}$$

(42)

$$\begin{array}{c}\hfill K_i={\displaystyle \frac{\tau ·{\pi }^2·(log{(OS/100)}^2+9.8696)}{K·t_s^2·log{(OS/100)}^2}}\end{array}$$

(43)

Evaluating Expressions (42) and (43) using the values of K and $\tau$ reported in (39), and considering design specifications equal to $OS\le 10\%$ and $t_s\le 20\mathrm{ms}$, results in the $PI$ controller parameters $K_p=63.565$ and $K_i=5.2481\times {10}^3$. This example shows the usability of the control-oriented version of the model to design classical control systems acting on the phase-shift between the two bridges of the DAB converter. The following two subsections evaluate the controller performance using both HIL and real platforms, which is necessary to validate the applicability of the control-oriented version of the model in real operation scenarios.

4.3. Control Evaluation Using HIL Tests

The validation of the control-oriented version of the model requires to verify the performance of the controller designed in the previous subsection. The first validation is carried out using HIL tests with the digital twin previously developed in Section 3.

This test uses the experimental HIL configuration shown in Figure 18, where the Teensy 4.1 microcontroller emulates the DAB converter using the proposed discrete-time model, and the TMS320F28335 microcontroller executes the designed voltage controller (HIL part of the experiment). The test structure is depicted in Figure 24, where the Teensy 4.1 microcontroller exports the emulated load voltage $v_{C_H}$ to the DAC R2R in real-time, producing an analog signal that could be introduced into the control device. Moreover, the Teensy 4.1 microcontroller can export other signals to the other DAC R2R to inspect them using a real oscilloscope. The control device to be tested is the TMS320F28335 microcontroller, which acquires the load voltage $v_{C_H}$ using an ADC, scales it to the appropriate magnitude, computes the PI controller designed in the previous subsection, and produces the two phase-shifted PWM signals based on the PI command $\delta$. Those real PWM signals are sent back to the Teensy 4.1 microcontroller to update the difference equations of the optimized model. This bidirectional communication closes the HIL loop, reproducing the real-time interaction between the control algorithm and the converter.

Figure 24. HIL platform of the DAB converter for testing practical control systems.

This HIL tests also considers load variations, which are programmed in the Teensy 4.1 microcontroller, thus emulating step changes in the output current $i_o$. Those perturbations are used to evaluate the controller’s ability to regulate the output voltage $v_{C_H}$ at the reference $v_{ref}$ under different operating conditions. This process validates the control strategy in a fully embedded HIL environment.

The perturbations emulated on the load current are: the load current starts at 400.0 mA and follows a predefined stepped profile in which its value is updated every 100 ms according to the sequence: 400.0 mA, 306.1 mA, 257.1 mA, 306.1 mA, 315.8 mA, and finally 400.0 mA. Each current level is set for a duration of 100 ms before switching to the next value, generating a piecewise consumption profile used to evaluate the dynamic response of the system. Figure 25 shows the experimental results of the HIL test. Those analog signals must be scaled to represent the real converter behavior; this is needed due to the voltage range limitation of the DACs. Table 13 summarizes the scaling factors that must be applied to the waveforms reported in Figure 25.

Figure 25. Experimental HIL testing of the controller for $v_{ref}=36V$.

Table 13. Scaling factors and equivalent real values for the emulated voltage and current in Figure 25.

Variable	Measured Range (HIL)	Scaling Factor	Equivalent Real Range
Voltage $v_{C_H}$	1.252 V–1.428 V	37.20 mV/V	33.66 V–38.38 V
Current $i_{L_p}$	0.894 V–1.111 V	135.45 mV/A	6.6 A–8.2 A

The lower part of Figure 25 shows the waveform of the current $i_{L_p}$ (red trace), where three steady-state conditions are observed, those corresponding to the different load levels considered in the test. The measured amplitudes of the emulated current are 894 mV, 1.002 V, and 1.111 V, which correspond to the real converter currents when considering the scaling factor of the HIL system. Table 13 reports the equivalent real range of $i_{L_p}$ after applying the scaling factor. The upper part of the figure shows the emulated output voltage $v_{C_H}$ (blue trace), which follows the reference $v_{ref}=1.34\mathrm{V}$ corresponding to a real reference of 36 V; this value is calculated using the scaling factor reported in Table 13. The $v_{C_H}$ waveform shows two transient events: the first with an undershoot ($OS$) of 6.5% and a settling time ($t_s$) of 13.2 ms, and the second one with an overshoot of 6.5% and a settling time of 8.7 ms, thus imposing a $v_{C_H}$ between 1.252 V and 1.428 V, which corresponds to a real voltage range between 33.66 V and 38.38 V as reported in Table 13.

To evaluate the model performance under a different operating condition, an additional closed-loop test was conducted at an output voltage reference of $24\mathrm{V}$, which lies within the physical operational boundaries established for the converter components. Following the same tuning procedure implemented for the $36\mathrm{V}$ baseline, the new linearized model was obtained at the operating point defined by $v_{C_{H_0}}=24\mathrm{V}$, $v_{L_0}=12\mathrm{V}$, and ${\delta }_0={21}^{\circ }$. Then, the proportional and integral gains for the PI controller were calculated as $K_p=1$ and $K_i=20$, respectively.

Figure 26 presents the dynamic HIL trajectories observed during the $24\mathrm{V}$ closed-loop test. Under the sequential charging steps, the current in the primary inductor $i_{L_P}$ shows fewer transitions than in the 36 V test. The output voltage $v_{C_H}$ successfully tracks its reference without any steady-state error, demonstrating a maximum transient overshoot of $3.1\%$ and achieving an average settling time of $t_s=16\mathrm{ms}$. Table 14 reports the scaling factors and equivalent real values for this test.

Figure 26. Experimental HIL testing of the controller for $v_{ref}=24V$.

Table 14. Scaling factors and equivalent real values for the emulated voltage and current in Figure 26.

Variable	Measured Range (HIL)	Scaling Factor	Equivalent Real Range
Voltage $v_{C_H}$	0.862 V–0.897 V	37.20 mV/V	23.17 V–24.11 V
Current $i_{L_p}$	0.58 V–0.60 V	135.454 mV/A	4.28 A–4.43 A

The effectiveness of the linearized model in decoupling the dynamics of the DAB converter is demonstrated through closed-loop regulation across a broad range of voltage variations. The parametric accuracy and precise transient replication achieved by this linear version of the model was successfully used to design a classical PI controller.

In conclusion, this HIL test confirms that the PI controller designed with the control-oriented version of the model (Section 4.2) fulfills the desired performance criteria: maximum overshoot $OS\le 10\%$ and settling-time $t_s\le 20\mathrm{ms}$. Therefore, it will be possible to use the linearized model in the design of more complex strategies that depend on an accurate representation of the system to ensure stability, such as MPC and Robust Sliding-Mode Control (SMC).

4.4. Control Evaluation Using a Real DAB Converter

A second validation is performed using the real DAB converter. This experiment fulfills two objectives:

• Validate the performance of the digital twin for HIL tests by contrasting both emulated and real converter currents and voltages.
• Validate the performance of the PI controller designed with the control-oriented version of the model, thus also validating the usability of the proposed model.

The experimental platform based on the real DAB converter is described in Figure 27. The controller to be tested is implemented on the TMS320F28335 microcontroller using the same code developed for the HIL test, which produces the two PWM signals needed by the converter, modulating the phase shift between the bridges according to the controller command. Similar to the HIL test, this experiment also considers load disturbances in the form of current steps, which are applied to evaluate the regulation and dynamic response of the system.

Figure 27. Circuital scheme of the experimental platform of the DAB converter.

The experimental platform of Figure 27 is based on the real DAB converter previously described in Section 2.1 and Figure 4. Moreover, two DC power supplies feed the converter: one DC power source provides the input voltage $v_L=12V$, and the another supplies the instrumentation. In order to provide signal isolation for the MOSFETs’ drivers, HCPL optocouplers are used to interface the TMS320F28335 microcontroller and the drivers integrated circuits. Finally, the load current profile is imposed by a KEPCO four-quadrant electronic load operating in current mode. Figure 28 shows all the physical components of the experimental setup, where the measurements are obtained with a Tektronix scopometer, current and voltage probes, and dedicated probe power supply, which enables simultaneous observations of both voltage and current waveforms during operation.

Figure 28. Experimental setup for the DAB prototype.

The perturbations emulated on the load current follow a predefined stepped profile. The current starts at 400.0 mA and is updated every 100 ms according to the sequence: 400.0 mA, 306.1 mA, 257.1 mA, 306.1 mA, 315.8 mA and 400.0 mA. Each current level is set for a duration of 100 ms before switching to the next value, generating a piecewise load perturbation to the real DAB converter. Figure 29 reports the experimental results of this voltage control test. The lower trace displays the main inductor current $i_{L_k}$ (red), where the amplitude changes according to the applied load perturbation. The amplitude starts at 16.4 A for a load current of 400.0 mA; at 24 ms it decreases to 7.4 A due to the load current change to 306.1 mA; at 124 ms it further decreases to 6.6 A when the load current reaches 257.1 mA. Subsequently, the profile returns to 306.1 mA, causing the inductor current amplitude to rise again to 7.4 A, and finally, at 424 ms, the amplitude returns to 8.2 A as the load current changes back to 400.0 mA. These experimental results are contrasted with the HIL experiment previously reported in Figure 25 (Section 4.3), which scaled with the factors of Table 13, results in errors below 1.5% for the HIL predictions with respect to the real DAB converter behavior. This confirms the accurate predictions of both the model and digital twin proposed in this paper.

Figure 29. Experimental response of the voltage controller on the real DAB converter.

This experiment considers a voltage reference $v_{ref}$ = 36 V, which is lower than the reference considered for the HIL experiment (46 V) due to constraints of the electrical components in the real DAB converter. The upper trace of Figure 29 reports the output capacitor voltage $v_{C_H}$ (blue), which is controlled by the designed PI controller running in the TMS320F28335 microcontroller. The controller successfully mitigates the five disturbances introduced in the load current, where two transient events are particularly notable: the first one at 124 ms exhibits an 8.8% undershoot (minimum voltage of 32.8 V) with a stabilization time of 13 ms; the second one occurs at 224 ms, exhibiting a 10% overshoot (maximum voltage of 39.6 V) and stabilizes within 19 ms. Therefore, the system shows fast and well-damped responses, fulfilling the desired performance criteria imposed in Section 4.2, i.e., maximum overshoot $OS\le 10\%$ and settling-time $t_s\le 20\mathrm{ms}$. This confirms suitability of the optimized model for control design.

In conclusion, the experimental transient behavior of both voltage and current obtained in the real converter closely matches the characteristics exhibited by the HIL emulation, keeping the overshoot and stabilization time within the expected performance range. These results confirm that the optimized model accurately reproduces the converter’s dynamic response, and validates the control-oriented version of the model. The results also validate the proposed platform as an effective tool for designing and testing controllers before implementation on the actual converter, thereby ensuring successful control deployment and minimizing implementation errors.

5. Conclusions

This work proposed a comprehensive methodology for mathematical modeling, validation, emulation, and control of DAB converters to ensure consistency across all design stages. The first step consisted in developing a detailed nonlinear model of the DAB converter that accounts for conduction losses, parasitic elements, and transformer characteristics to accurately capture its dynamic behavior. The model parameters were then calibrated through a multi-algorithm optimization framework, using PSO, GWO, SBOA, and WOA to minimize the error between simulated waveforms and experimental measurements. The comparative analysis demonstrated that PSO provides the best compromise between accuracy and robustness, achieving the lowest error values along with a consistent parameter convergence, while the remaining algorithms either exhibited higher variability or limited exploration capabilities.

To establish a clear methodological distinction within the modeling stage, it is crucial to categorize the two independent mathematical frameworks developed in this study according to their core purposes. On the one hand, the real-time emulation branch represents the main contribution of this work, consisting of a high-fidelity, non-linear model that incorporates all identified parasitic resistances and inductances. This model is discretized and deployed on the Teensy 4.1 platform at an overclocked frequency of $1\mathrm{GHz}$, successfully operating as a HIL digital twin baseline. On the other hand, the linearized small-signal control branch follows established literature practices by expanding the dynamic variables of the DAB converter through a Generalized State-Space Averaging approach. This method incorporates the phase shift angle ($\delta$) via the harmonic representation of the switching waveforms. Then, a practical small-signal transfer function, suitable for classical controller design, is derived by truncating the high-frequency time-dependent switching components, which represent the steady-state switching ripple, leaving only the averaged dynamic envelope behavior.

The validation was performed using both time-domain and frequency-domain experimental analyses, where the optimized model exhibited close agreement with reality, demonstrating the correct reproduction of the converter dynamics. Specifically, the parameter identification routine achieved low baseline error metrics, while the average frequency-domain tracking yielded a mismatch of only $1.03\%$ in magnitude and $6.31\%$ in phase. These low error metrics confirm the high fidelity of the proposed model and the effectiveness of the parameter identification process.

Following validation, the real-time emulation framework was deployed to evaluate the digital twin on its dedicated embedded architecture. The embedded profiling of the integration algorithms revealed a critical micro-architectural trade-off between mathematical order and execution latency ($T_s$). Although higher-order methods like RK4 offer superior truncation properties under matched steps, their elevated computational time forces a wider real-time execution window ($T_s=620\mathrm{ns}$). This longer execution time degrades the temporal resolution available to sample external gating signals, introducing aliasing-related duty cycle quantization errors. Consequently, the explicit Forward Euler baseline achieves the highest tracking precision by completing its execution loop in just $172\mathrm{ns}$, demonstrating that maximizing the physical oversampling ratio through low computational latency is more critical for high-frequency switched HIL emulations than upgrading the polynomial order of the solver.

Subsequently, the linearized control-oriented branch led to a simplified transfer function between the phase shift and the output voltage, which was initially linearized around the nominal $36\mathrm{V}$ operating point. The usability of this representation was evaluated by designing a classical PI controller, which was experimentally tested in both the HIL system and the real DAB converter. The experimental results confirmed that the control system fulfills the required performance objectives, achieving overshoots below $10\%$ and settling times under $20\mathrm{ms}$ for multiple load disturbances. Furthermore, the dynamic robustness of the identification and control frameworks was successfully validated through a cross-validation campaign under a degraded voltage reference of $24\mathrm{V}$, which heavily altered the converter operating gains. Despite being operated away from the original $36\mathrm{V}$ linearization baseline, the model preserved its high tracking accuracy and zero steady-state error under these wide voltage variations, confirming that the linearized model represents a suitable tool for control purposes. These results validate the accuracy of the proposed model and HIL framework, ensuring strong consistency between theoretical, simulated, and real-world behavior.

This paper introduces a highly accurate approach for identifying parameters and designing controllers in DAB converters. This physically consistent, linear baseline simplifies practical engineering deployment and supports advanced non-linear controls like MPC or Robust SMC, which demand precise plant models for stability. To account for thermal effects and component aging over the lifespan, which were not modeled in this work, periodic recalibration cycles can integrated into the optimization loop. A future improvement of this work will be focused on integrating these non-linear control architectures on the HIL platform, also incorporating temperature dependencies and frequency-dependent switching losses into the converter’s dynamic model.

In conclusion, this work proposes a methodology whose originality lies in the seamless transition between experimental testing and high-fidelity hardware emulation for DAB converters. Unlike traditional, purely theoretical modeling approaches, this method captures complex parasitic dynamics and real-world physical imperfections, such as solder resistances and PCB manufacturing tolerances, by parametrically identifying the converter model via optimization algorithms coupled with an experimental error metric. Furthermore, the ability to re-parameterize the system after prolonged periods of operation introduces a critical innovation: the quantification and tracking of the effects of component aging and thermal variations. Finally, integrating this optimized and calibrated model into a HIL platform ensures a precise, safe, and realistic environment for validating advanced control strategies.

It is important to note that the methodology presented in this paper constitutes an initial phase of exploration and conceptual validation of the optimization-based approach for the parametric estimation of the DAB converter. At this stage, it was decided not applying search space reduction techniques, such as the Taguchi-ANOVA statistical method, to evaluate the raw performance of the four selected optimization algorithms on the full problem with 15 parameters. This decision allowed for the characterization of the convergence capacity and robustness of each optimizer without biases arising from simplifications or preconditioning, thereby establishing a rigorous baseline for future comparisons.

Although the methodological foundation presented in this work provides a robust framework for accurate parameter estimation and control design, it is also clear the potential of AI-based techniques such as neural networks, reinforcement learning, and surrogate models, as well as hybrid approaches that combine data-driven methods with physics-based models. Therefore, another future research direction is to integrate these advanced strategies to accelerate convergence, reduce computational load, and enhance accuracy in real-time-constrained environments, while preserving the fidelity of the converter model as a central design priority. Specifically, it is expected to develop surrogate-assisted optimization frameworks and learning-based adaptive controllers that dynamically adjust to parameter variations and operating-point changes. These extensions will be systematically addressed in subsequent work, once the core methodology presented in this paper has been fully consolidated.

An additional future project is the real-time implementation of a parametric estimation scheme for power converters that incorporates data preprocessing using the Taguchi-ANOVA methodology, which will reduce dimensionality and filter variables before applying optimization algorithms. This strategy will transform experimental data (transient response, steady-state efficiency, and harmonic content) into a reduced set of critical parameters, significantly reducing the computational load and convergence time of the optimizers. The implementation will be carried out on high-performance hardware platforms, such as FPGAs or DSP microcontrollers, which will execute the closed-loop optimization algorithm to update the converter’s parameters in real time. This approach is expected to improve estimation accuracy, reduce stress on components, and enable continuous adaptation to changes in load conditions or system aging.

A third future development is to overcome the limitations of traditional modulation techniques used in DAB converters, such as SPS, to improve the quality of the transferred power and the system’s overall efficiency. In this context, accurately simulated hardware-based converters will be a useful tool for this purpose, enabling the rapid validation of advanced modulation strategies, such as hybrid strategies that integrate PWM and discrete optimal PDM [1].

Appendix A.1. Particle Swarm Optimization (PSO)

PSO updates the velocity and position of each particle i at iteration t using a combination of inertia, cognitive, and social components, formulated as:

$${\mathbf{v}}_i^{t+1}=w{\mathbf{v}}_i^t+c_1{\mathbf{r}}_1\odot ({\mathbf{p}}_i-{\mathbf{x}}_i^t)+c_2{\mathbf{r}}_2\odot (\mathbf{g}-{\mathbf{x}}_i^t)$$

(A2)

$${\mathbf{x}}_i^{t+1}={\mathbf{x}}_i^t+{\mathbf{v}}_i^{t+1}$$

(A3)

where ${\mathbf{p}}_i$ is the historical personal best position of particle i, $\mathbf{g}$ is the global best position found by the entire swarm, and ${\mathbf{r}}_1,{\mathbf{r}}_2$ are uniformly distributed random vectors within $[0,1]$. An adaptive strategy dynamically updates the parameters at each time step according to:

$$w=w_{max}-(w_{max}-w_{min})\left({\displaystyle \frac{t}{t_{max}}}\right)$$

(A4)

$$c_1=c_{1,max}-(c_{1,max}-c_{1,min})\left({\displaystyle \frac{t}{t_{max}}}\right)$$

(A5)

$$c_2=c_{2,max}+(c_{2,min}-c_{2,max})\left({\displaystyle \frac{t}{t_{max}}}\right)$$

(A6)

The optimization execution incorporates velocity clamping ($V_{max},V_{min}$) and a soft-rebound boundary handling mechanism that scales the velocity vector by a factor of $-0.5$ upon boundary infringement.

Appendix A.2. Grey Wolf Optimizer (GWO)

GWO mimics the social hierarchy and hunting mechanisms of grey wolves. The population is guided by the three best candidate positions, denoted as $\alpha$, $\beta$, and $\delta$. The position update of each wolf at iteration t is calculated by averaging the encircling trajectories relative to the leaders:

$${\mathbf{D}}_{\alpha }=\left|{\mathbf{C}}_1\odot {\mathbf{X}}_{\alpha }-{\mathbf{X}}^t\right|,{\mathbf{D}}_{\beta }=\left|{\mathbf{C}}_2\odot {\mathbf{X}}_{\beta }-{\mathbf{X}}^t\right|,{\mathbf{D}}_{\delta }=\left|{\mathbf{C}}_3\odot {\mathbf{X}}_{\delta }-{\mathbf{X}}^t\right|$$

(A7)

$${\mathbf{X}}_1={\mathbf{X}}_{\alpha }-{\mathbf{A}}_1\odot {\mathbf{D}}_{\alpha },{\mathbf{X}}_2={\mathbf{X}}_{\beta }-{\mathbf{A}}_2\odot {\mathbf{D}}_{\beta },{\mathbf{X}}_3={\mathbf{X}}_{\delta }-{\mathbf{A}}_3\odot {\mathbf{D}}_{\delta }$$

(A8)

$${\mathbf{X}}^{t+1}={\displaystyle \frac{1}{3}}\left({\mathbf{X}}_1+{\mathbf{X}}_2+{\mathbf{X}}_3\right)$$

(A9)

The coefficient vectors ${\mathbf{A}}_m$ and ${\mathbf{C}}_m$ ($m=1,2,3$) are defined as:

$${\mathbf{A}}_m=2a{\mathbf{r}}_1-a,{\mathbf{C}}_m=2{\mathbf{r}}_2$$

(A10)

where ${\mathbf{r}}_1,{\mathbf{r}}_2$ are random vectors uniformly distributed in $[0,1]$. The exploration-exploitation transition parameter a decays linearly as:

$$a=2-2\left({\displaystyle \frac{t}{t_{max}}}\right)$$

(A11)

Appendix A.3. Secretary Bird Optimization Algorithm (SBOA)

SBOA applies a two-phase sequential update scheme comprising an exploration phase (P1) and an exploitation phase (P2) driven by a greedy selection mechanism. The exploration phase (P1) alters its mathematical structure across three distinct iteration segments:

$${\mathbf{X}}_{i,\mathrm{new}}^{\mathrm{P}1}=\left\{\begin{array}{cc}{\mathbf{X}}_i^t+({\mathbf{X}}_{r1}-{\mathbf{X}}_{r2})\odot {\mathbf{R}}_1,\hfill & \mathrm{if}t<{\displaystyle \frac{t_{max}}{3}}\hfill \\ {\mathbf{X}}_{\mathrm{best}}+e^{{(t/t_{max})}^4}({\mathbf{R}}_B-0.5)\odot ({\mathbf{X}}_{\mathrm{best}}-{\mathbf{X}}_i^t),\hfill & \mathrm{if}{\displaystyle \frac{t_{max}}{3}}\le t<{\displaystyle \frac{2t_{max}}{3}}\hfill \\ {\mathbf{X}}_{\mathrm{best}}+{\left(1-{\displaystyle \frac{t}{t_{max}}}\right)}^{{\displaystyle \frac{2t}{t_{max}}}}{\mathbf{X}}_i^t\odot {\mathbf{R}}_L,\hfill & \mathrm{if}t\ge {\displaystyle \frac{2t_{max}}{3}}\hfill \end{array}\right.$$

(A12)

where ${\mathbf{X}}_{r1},{\mathbf{X}}_{r2}$ are randomly selected individuals, ${\mathbf{R}}_1$ is a uniform random matrix, ${\mathbf{R}}_B$ is a normal Gaussian random matrix, and ${\mathbf{R}}_L$ follows a Lévy flight distribution.

In the exploitation phase (P2), candidate solutions choose between two localized tracking mechanisms governed by the constant internal threshold probability $r_i=0.5$:

$${\mathbf{X}}_{i,\mathrm{new}}^{\mathrm{P}2}=\left\{\begin{array}{cc}{\mathbf{X}}_{\mathrm{best}}+(2{\mathbf{R}}_B-1){\left(1-{\displaystyle \frac{t}{t_{max}}}\right)}^2\odot {\mathbf{X}}_i^t,\hfill & \mathrm{if}rand<r_i\hfill \\ {\mathbf{X}}_i^t+{\mathbf{R}}_2\odot ({\mathbf{X}}_r-K{\mathbf{X}}_i^t),\hfill & \mathrm{otherwise}\hfill \end{array}\right.$$

(A13)

where ${\mathbf{X}}_r$ represents a random candidate, ${\mathbf{R}}_2$ is a uniform random matrix, and K is a discrete random scaling integer computed as $K=\mathrm{round}(1+rand)$.

Appendix A.4. Whale Optimization Algorithm (WOA)

WOA models the bubble-net hunting behavior of humpback whales by choosing between encircling mechanisms and spiral path updates based on a random threshold probability p. For $p<0.5$, the algorithm switches between exploitation and exploration depending on the magnitude of the coefficient vector $\mathbf{A}$:

$${\mathbf{X}}^{t+1}=\left\{\begin{array}{cc}{\mathbf{X}}_{\mathrm{best}}-\mathbf{A}\odot \mathbf{D},\hfill & \mathrm{if}p<0.5\mathrm{and}\left|\mathbf{A}\right|<1\hfill \\ {\mathbf{X}}_{\mathrm{rand}}-\mathbf{A}\odot {\mathbf{D}}_{\mathrm{rand}},\hfill & \mathrm{if}p<0.5\mathrm{and}\left|\mathbf{A}\right|\ge 1\hfill \\ {\mathbf{D}}^{\prime }\odot e^{bl}cos\left(2\pi l\right)+{\mathbf{X}}_{\mathrm{best}},\hfill & \mathrm{if}p\ge 0.5\hfill \end{array}\right.$$

(A14)

The vector variables and distance matrices are mathematically defined as:

$$\mathbf{D}=\left|\mathbf{C}\odot {\mathbf{X}}_{\mathrm{best}}-{\mathbf{X}}^t\right|,{\mathbf{D}}_{\mathrm{rand}}=\left|\mathbf{C}\odot {\mathbf{X}}_{\mathrm{rand}}-{\mathbf{X}}^t\right|,{\mathbf{D}}^{\prime }=\left|{\mathbf{X}}_{\mathrm{best}}-{\mathbf{X}}^t\right|$$

(A15)

The internal parameters follow the structures $\mathbf{A}=2a{\mathbf{r}}_1-a$ and $\mathbf{C}=2{\mathbf{r}}_2$, where the exploration variable a decays linearly from 2 to 0 over the iterations. The spiral path is governed by the constant shape factor $b=1.0$, while l is a uniformly distributed random value within the interval $[-1,1]$.

Appendix B.1. Implicit Trapezoidal (Tustin) Scheme

The implicit Trapezoidal method achieves a second-order algebraic approximation by averaging the state derivatives at the current and previous sampling instants. By isolating the state vector $\mathbf{x}\left(n\right)$, the execution structure is expressed as:

$$\mathbf{x}\left(n\right)={\left[\mathbf{I}-{\displaystyle \frac{T_s}{2}}{\mathbf{A}}_d(s_1,s_2)\right]}^{-1}\left[\left(\mathbf{I}+{\displaystyle \frac{T_s}{2}}{\mathbf{A}}_d(s_1,s_2)\right)\mathbf{x}(n-1)+{\displaystyle \frac{T_s}{2}}{\mathbf{B}}_d(s_1,s_2)\left(u_1\left(n\right)+u_1(n-1)\right)\right]$$

(A16)

Appendix B.2. Explicit Second-Order Runge–Kutta (RK2) Scheme

The RK2 framework, or Heun’s method, introduces an explicit multi-stage evaluation. It predicts an intermediate state using a standard Euler step and subsequently refines the trajectory slope, yielding the following recurrence profile:

$$\begin{array}{ccc}\hfill {\mathbf{k}}_1& =& {\mathbf{A}}_d(s_1,s_2)\mathbf{x}(n-1)+{\mathbf{B}}_d(s_1,s_2)u_1(n-1)\hfill \end{array}$$

(A17)

$$\begin{array}{ccc}\hfill {\mathbf{k}}_2& =& {\mathbf{A}}_d(s_1,s_2)\left(\mathbf{x}(n-1)+T_s{\mathbf{k}}_1\right)+{\mathbf{B}}_d(s_1,s_2)u_1\left(n\right)\hfill \end{array}$$

(A18)

$$\begin{array}{ccc}\hfill \mathbf{x}\left(n\right)& =& \mathbf{x}(n-1)+{\displaystyle \frac{T_s}{2}}\left({\mathbf{k}}_1+{\mathbf{k}}_2\right)\hfill \end{array}$$

(A19)

Appendix B.3. Explicit Fourth-Order Runge–Kutta (RK4) Scheme

The classical RK4 algorithm computes four distinct derivative approximations (${\mathbf{k}}_1$ through ${\mathbf{k}}_4$) per integration window to capture the non-linear/high-frequency switching transitions with maximum precision. Its real-time sub-stage execution is governed by:

$$\begin{array}{ccc}\hfill {\mathbf{k}}_1& =& {\mathbf{A}}_d(s_1,s_2)\mathbf{x}(n-1)+{\mathbf{B}}_d(s_1,s_2)u_1(n-1)\hfill \end{array}$$

(A20)

$$\begin{array}{ccc}\hfill {\mathbf{k}}_2& =& {\mathbf{A}}_d(s_1,s_2)\left(\mathbf{x}(n-1)+{\displaystyle \frac{T_s}{2}}{\mathbf{k}}_1\right)+{\mathbf{B}}_d(s_1,s_2)u_1\left(n-{\displaystyle \frac{1}{2}}\right)\hfill \end{array}$$

(A21)

$$\begin{array}{ccc}\hfill {\mathbf{k}}_3& =& {\mathbf{A}}_d(s_1,s_2)\left(\mathbf{x}(n-1)+{\displaystyle \frac{T_s}{2}}{\mathbf{k}}_2\right)+{\mathbf{B}}_d(s_1,s_2)u_1\left(n-{\displaystyle \frac{1}{2}}\right)\hfill \end{array}$$

(A22)

$$\begin{array}{ccc}\hfill {\mathbf{k}}_4& =& {\mathbf{A}}_d(s_1,s_2)\left(\mathbf{x}(n-1)+T_s{\mathbf{k}}_3\right)+{\mathbf{B}}_d(s_1,s_2)u_1\left(n\right)\hfill \end{array}$$

(A23)

$$\begin{array}{ccc}\hfill \mathbf{x}\left(n\right)& =& \mathbf{x}(n-1)+{\displaystyle \frac{T_s}{6}}\left({\mathbf{k}}_1+2{\mathbf{k}}_2+2{\mathbf{k}}_3+{\mathbf{k}}_4\right)\hfill \end{array}$$

(A24)

where $u_1(n-1/2)$ represents the mid-point input voltage value during the current discrete integration interval.