Design of a Fast and Scalable FPGA-Based Bitmap for RDMA Networks

Remote direct memory access (RDMA) is widely used within and across data centers due to its low latency, high throughput, and low CPU overhead. To further enhance the transmission performance of RDMA, techniques such as multi-path RDMA have been proposed. However, while these techniques increase throughput, they also introduce significant out-of-order (OoO) packet issues that standard RDMA network interface cards (RNICs) struggle to handle effectively. To address the OoO challenges in RDMA network and ensure the integrity of data, we propose an FPGA-based bitmap which is capable of maintaining high throughput and low latency under OoO conditions. Our design segments the bitmap and maintains status information, achieving the low-latency processing of OoO packets with excellent scalability, thus making it suitable for various network environments. We implement this design on Xilinx AU200 FPGA and test it in a simulated 100 Gbps data center network. The results show that the performance under OoO transmission conditions is comparable to that under in-order conditions, demonstrating the solution’s effectiveness in handling RDMA OoO packets efficiently and ensuring high-performance data transfer in RDMA networks.