Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design

Garbaya, Amel; Kotti, Mouna; Fakhfakh, Mourad; Tlelo-Cuautle, Esteban

doi:10.3390/jlpea10020020

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Article

16 June 2020

16 Pages

Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design

and

Department of Electronics, ENET’com, University of Sfax, Sfax 3018, Tunisia

Department of Electronics, Electrotechnics and Control, ISSIG, University of Gabes, Gabes 6032, Tunisia

INAOE, Tonantzintla, Puebla 72840, Mexico

Author to whom correspondence should be addressed.

J. Low Power Electron. Appl.2020, 10(2), 20;https://doi.org/10.3390/jlpea10020020

This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters

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Abstract

Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used within a metaheuristic-based optimization kernel in order to maximize the circuits’ sizing. The JAYA algorithm was used for this purpose. Three topologies of CMOS current conveyors (CCII) were considered to showcase the proposed approach. The achieved performances were compared to those obtained using conventional LVLP circuit sizing techniques, and we show that our approach offers interesting results.

Keywords:

LVLP; CCII; surrogate modeling; kriging models; JAYA; PSO; Wilcoxon Signed-Rank Test

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