Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design

: Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used within a metaheuristic-based optimization kernel in order to maximize the circuits’ sizing. The JAYA algorithm was used for this purpose. Three topologies of CMOS current conveyors (CCII) were considered to showcase the proposed approach. The achieved performances were compared to those obtained using conventional LVLP circuit sizing techniques, and we show that our approach o ﬀ ers interesting results.


Introduction
Low-power low-voltage (LVLP) circuits are of paramount importance in analog, mixed-signal and radiofrequency (AMS/RF) systems. Decreasing voltage supply and reducing power consumption is a real challenge for AMS/RF applications [1][2][3][4][5][6][7][8]. As examples, we can mention the fact that such circuits can overcome some classical circuit limitations, such as the gain-bandwidth (GBW) product limitation [1], and they are also very necessary due to ceaseless technology scaling. However, such circuit design is complex, tedious and very time consuming.
MOSFETs operating in weak inversion mode have been largely considered to implement low power circuits [9]. LVLP current conveyors have been used in many electronic applications [10], such as sensor interfaces [10], inductance simulation [11], oscillators [12] and filters [3,13], among others. However, and as aforementioned, the complexity of such designs and the impact of technology variations in analog integrated circuits operating in weak inversion have pushed (and continue to push) engineers, designers and researchers to develop computer-aided design (CAD) tools for automating this process as much as possible [9,14]. Two main approaches have been used so far: (i) the so-called knowledge-based technique [9], which is very time consuming and mainly depends on the experience of the skilled designer; (ii) the optimization-based design, which consists of using an optimization algorithm for optimally sizing the considered circuit/system [9]. Two evaluation approaches can be used. The first considers the symbolic equations of the circuit/system performances/constraints [15][16][17]. This approach is known to be rapid but lacks accuracy. The second approach is the in-loop based approach, also called the simulation-based technique [18][19][20][21]. It consists of making the appeal to use an electric simulator as an evaluator. In this way, accurate results can be obtained; however, the approach is time consuming due to the number of calls to the simulator. results can be obtained; however, the approach is time consuming due to the number of calls to the simulator.
A few years ago, a new modeling technique, (i.e., surrogate modeling) was proposed in the mathematical literature. The technique is also called "metamodeling". In short, the approach consists of generating accurate performance models that can be rapidly evaluated. In other words, this new technique offers advantages of both conventional approaches: accuracy and rapid evaluation. Different variants of metamodeling approaches are nowadays available in the literature, such as the regression method [22], the Kriging model [23], and the radial basis function (RBF) [24]. Surrogate modeling has already been adopted in the electronic domain (see, for instance, [25][26][27]). In a previous work [21], the authors used the RBF model combined with particle swarm optimization (PSO) to optimize the performances of CMOS analog circuits.
In this work, the Kriging model was applied to the accurate modeling of the main parasitic error source (the X-port input resistance (Rx)) of second-generation current conveyors (CCIIs) operating in weak inversion under different biases. Constructed models were used within a metaheuristic-based optimization kernel for minimizing the aforementioned parasitic source. The newly proposed Jaya algorithm was considered [28,29].
The rest of this paper is organized into four sections. In section 2, an overview on the metamodeling techniques is offered. The considered metaheuristic-based algorithms are detailed in section 3. Section 4 presents the considered applications and highlights the achieved results. Finally, conclusions are offered in Section 5.

Metamodeling Technique: An Overview
Surrogate modeling is a newly conceived interpolation technique for the efficient approximation of linear and non-linear functions [25]. Many variants have been considered and introduced in the specialized literature, such as the regression method [22], the Kriging method [23] and the RBF method [24]. The main objective of this technique is to approximate complex non-linear functions with an accurate and simple model [25][26][27]. This technique has already been used in a broad range of engineering applications, such as in geostatistics [26], electronic circuits [27,30,31], and electromagnetic devices [25,[32][33][34].
The construction of surrogate models requires three main steps: design sampling, function evaluation, and model construction, as shown in Figure 1. In this work, we consider the Kriging technique which uses the interpolation function Y(x), represented as follows [25][26][27]: where N is the number of sample points, fj(x) represents the j th regression function model, βj is the corresponding weighting coefficient, and Z(x) is a stochastic process. The latter has a mean value equal to zero, and the covariance between two sampling points, xi and xj, is expressed as in [25][26][27]: In this work, we consider the Kriging technique which uses the interpolation function Y(x), represented as follows [25][26][27]: where N is the number of sample points, f j (x) represents the j th regression function model, β j is the corresponding weighting coefficient, and Z(x) is a stochastic process. The latter has a mean value equal to zero, and the covariance between two sampling points, x i and x j , is expressed as in [25][26][27]: where σ 2 is the variance coefficient of Z(x) and R(θ,x i ,x j ) is the correlation function. The exponential correlation function, based on the Kriging technique, is considered in this work.

The Optimization Kernel
It has already been shown that analog circuit sizing/optimization can be considered as a hard problem to overcome [35][36][37]. Metaheuristics bid interesting solutions to solve such problems that can be formulated as presented in Equation (3). A plethora of metaheuristics have already been used for sizing AMS/RF circuits and systems, such as Genetic Algorithms (GA) [38], Ant Colony Optimization (ACO) [39], Bacterial Foraging Optimization (BFO) [40], Firefly Optimization (FFO) [41] and Simulated Annealing (SA) [42], to name a few. Among these metaheuristics, PSO [43] has been widely used due to the fact that it is robust, rapid and easy to be implemented. However, similar to most other metaheuristics, weighting coefficients (constriction and inertia) have to be fixed by the user for the metaheuristic tradeoff between exploration and intensification. This highly depends on the experience of the designer and the handled problem itself. Recently, a new metaheuristic has been proposed in the specialized literature which does not need any a prior coefficients to be fixed, it is called the JAYA algorithm [29], and it is applied herein as the optimization algorithm. A comparison with PSO will be performed to argue this choice. In the subsections below, we respectively present a brief overview of PSO and the details regarding the JAYA algorithm.
where x = (x 1 , . . . , x n )∈ X, X ⊂ n is the decision space for the variables, f (x i ): n -→ , is the objective function and h k (x) ≤ 0, k = 1 . . . m is a set of constraints that limit the values of the variables.

The Particle Swarm Optimization Algorithm
The Particle Swarm Optimization (PSO) algorithm is widely used in the literature, since it is a simple, robust and rapid metaheuristic. It is inspired by the social behavior of animals, namely fishes and birds [16,43,44]. Its mechanism works on updating each particle velocity and position at each iteration, according to the following equations: With x Pbest is the best position, x Gbest is the global best position, w is the inertia weight of the particle, and c 1 and c 2 are the construction parameters. Figure 2 shows a flowchart of the PSO algorithm [43].

The JAYA Algorithm
Evolutionary algorithms (EA), such as GA and swarm intelligence (SI) based algorithms, such as PSO, need specific parameters to be fixed, such as mutation probability and crossover probability for GA, inertia weight and cognitive social parameters for PSO. In this context and in order to avoid such a rule-of-thumb-based approach for fixing values of such weighting parameters, a new metaheuristic, inspired from the teaching-learning-based optimization (TLBO), was proposed, as detailed in [29,[45][46][47][48]. TLBO works according to two phases (teacher phase and learner phase) [48]. On the other hand, the JAYA algorithm encompasses only a unique phase [29]. Both algorithms require only common control parameters (population size and iteration number). It is comparatively much simpler to apply than conventional metaheuristics [29,44,45].
The JAYA algorithm mechanism works on updating each solution at each iteration, according to the following equations: where i is the number of iterations, K = 1,2,…n, n is the number of candidate solutions, J = 1,2,…m, m is the number of design variables, Xj,best,i is the value of the variable j for the best candidate and Xj, worst,i is the value of the variable j for the worst candidate. Xʹj,k,i is the update value of Xj,k,I and [r1,j,i, r2,j,i ] are the random numbers for the j th variable during the i th iteration and varies between [0, 1]. Term 1 in

The JAYA Algorithm
Evolutionary algorithms (EA), such as GA and swarm intelligence (SI) based algorithms, such as PSO, need specific parameters to be fixed, such as mutation probability and crossover probability for GA, inertia weight and cognitive social parameters for PSO. In this context and in order to avoid such a rule-of-thumb-based approach for fixing values of such weighting parameters, a new metaheuristic, inspired from the teaching-learning-based optimization (TLBO), was proposed, as detailed in [29,[45][46][47][48]. TLBO works according to two phases (teacher phase and learner phase) [48]. On the other hand, the JAYA algorithm encompasses only a unique phase [29]. Both algorithms require only common control parameters (population size and iteration number). It is comparatively much simpler to apply than conventional metaheuristics [29,44,45].
The JAYA algorithm mechanism works on updating each solution at each iteration, according to the following equations: where i is the number of iterations, K = 1,2, . . . n, n is the number of candidate solutions, J = 1,2, . . . m, m is the number of design variables, X j,best,i is the value of the variable j for the best candidate and X j, worst,i is the value of the variable j for the worst candidate. X j,k,i is the update value of X j,k,I and [r 1,j,i , r 2,j,i ] are the random numbers for the j th variable during the i th iteration and varies between [0, 1]. Term 1 in Equation (6) specifies the trend of the solution to move closer to the best solution, whereas Term 2 specifies the trend of the solution to avoid the worst solution. X' j,k,i is accepted if it gives a better function value. At the end of the iteration, all the accepted function values have been used as inputs to the next iteration. Figure 3 shows the flowchart of the JAYA algorithm [29].
J. Low Power Electron. Appl. 2020, 10, x FOR PEER REVIEW 5 of 16 Equation (6) specifies the trend of the solution to move closer to the best solution, whereas Term 2 specifies the trend of the solution to avoid the worst solution. X'j,k,i is accepted if it gives a better function value. At the end of the iteration, all the accepted function values have been used as inputs to the next iteration. Figure 3 shows the flowchart of the JAYA algorithm [29].

The Proposed Approach and Application Examples
Current conveyors are used as basic building blocks for the synthesis of analog circuits and systems. Due to their flexibility, the CCIIs operating in weak inversion are utilized in different applications [11], especially in high frequency circuits, sensor interfaces, filters and mobile communication applications [11]. A CCII is composed of two input ports (X and Y) and one output port (Z). The behavior of an ideal CCII can be summarized as follows [9][10][11][12], where positive (CCII+) and negative (CCII-) current conveyors are obtained for a = 1 and a = −1 [12], respectively: Parasitic input resistance (Rx) at port X can greatly affect the performances of the current conveyor and has to be minimized [49].
In the following section, we deal with modeling and then minimizing the aforementioned performances (i.e., Rx) of CMOS current conveyors operating in the weak inversion mode. For the sake of comparison, three different topologies are considered, namely, a class AB CCII+, a

The Proposed Approach and Application Examples
Current conveyors are used as basic building blocks for the synthesis of analog circuits and systems. Due to their flexibility, the CCIIs operating in weak inversion are utilized in different applications [11], especially in high frequency circuits, sensor interfaces, filters and mobile communication applications [11]. A CCII is composed of two input ports (X and Y) and one output port (Z). The behavior of an ideal CCII can be summarized as follows [9][10][11][12], where positive (CCII+) and negative (CCII-) current conveyors are obtained for a = 1 and a = −1 [12], respectively: Parasitic input resistance (Rx) at port X can greatly affect the performances of the current conveyor and has to be minimized [49].
In the following section, we deal with modeling and then minimizing the aforementioned performances (i.e., Rx) of CMOS current conveyors operating in the weak inversion mode. For the sake of comparison, three different topologies are considered, namely, a class AB CCII+, a differential-based Class AB CCII and an OTA-based CCII+. These circuits have already been considered in [9] and [49] and have been sized/optimized for operating in the weak inversion mode.

The Proposed Approach
The proposed approach consisted of generating a model of the Rx performance of each of the three topologies of CMOS CCIIs operating in weak inversion using the Kriging technique, then, using the JAYA algorithm, minimizing the corresponding value.
Initially, a database was generated using the Latin hypercube sampling (LHS) technique [50]. Four variables were considered (i.e., the channel widths and the channel lengths of the MOS transistors). For comparison with [9] and [49], we considered that all NMOS transistors' channels have the same widths (Wn) and the same lengths (Ln). Ditto for PMOS transistors. This database was used as an input for the Kriging modeling technique. This database consisted of the geometric variables of the considered circuits. In total, 1200 samples were considered. The HSPICE simulator was used to evaluate these samples. The simulations were performed using Level 49 standard CMOS technology of 0.35 µm, where transistors operate in the weak inversion mode. The model was constructed using the Kriging technique with the exponential correlation function. A second database, consisting of 100 test samples and their performance evaluated by the Hspice simulator, was used to validate the model. The relative error metric was considered to check the accuracy of the constructed models and its equation is given by (8), where yi and Yi are the simulated and the estimated (modeled) performance values, respectively. N is the number of sample points.

Application 1: A Class AB CMOS CCII+
The considered circuit [49] is shown in Figure 4. The objective was to model the parasitic X-port resistance for different bias current (I bias ) values: 15 µA, 20 µA, 26 µA, 30 µA and 45 µA. The voltage power supply was V dd /V ss = ± 1 V. Five models were constructed and validated. Table 1 gives the relative error of the model created for the different bias currents of the class AB CMOS CCII+, where the accuracy of the constructed models can be easily interpreted.
differential-based Class AB CCII and an OTA-based CCII+. These circuits have already been considered in [9] and [49] and have been sized/optimized for operating in the weak inversion mode.

The Proposed Approach
The proposed approach consisted of generating a model of the Rx performance of each of the three topologies of CMOS CCIIs operating in weak inversion using the Kriging technique, then, using the JAYA algorithm, minimizing the corresponding value.
Initially, a database was generated using the Latin hypercube sampling (LHS) technique [50]. Four variables were considered (i.e., the channel widths and the channel lengths of the MOS transistors). For comparison with [9] and [49], we considered that all NMOS transistors' channels have the same widths (Wn) and the same lengths (Ln). Ditto for PMOS transistors. This database was used as an input for the Kriging modeling technique. This database consisted of the geometric variables of the considered circuits. In total, 1200 samples were considered. The HSPICE simulator was used to evaluate these samples. The simulations were performed using Level 49 standard CMOS technology of 0.35 µm, where transistors operate in the weak inversion mode. The model was constructed using the Kriging technique with the exponential correlation function. A second database, consisting of 100 test samples and their performance evaluated by the Hspice simulator, was used to validate the model. The relative error metric was considered to check the accuracy of the constructed models and its equation is given by (8), where yi and Yi are the simulated and the estimated (modeled) performance values, respectively. N is the number of sample points.

Application 1: A class AB CMOS CCII+
The considered circuit [49] is shown in Figure 4. The objective was to model the parasitic X-port resistance for different bias current (Ibias) values: 15 µA, 20 µA, 26 µA, 30 µA and 45 µA. The voltage power supply was Vdd/Vss = ± 1 V. Five models were constructed and validated. Table 1 gives the relative error of the model created for the different bias currents of the class AB CMOS CCII+, where the accuracy of the constructed models can be easily interpreted.
Subsequently, the constructed models were used within a metaheuristic-based optimization routine. The JAYA algorithm was used, as aforementioned. The obtained results were compared to those of [9,49], where the in-loop optimization technique is used. Further, and in order to highlight the JAYA algorithm performances, optimization using the PSO technique was also carried out for comparison regarding accuracy, rapidity and robustness.   Subsequently, the constructed models were used within a metaheuristic-based optimization routine. The JAYA algorithm was used, as aforementioned. The obtained results were compared to those of [9,49], where the in-loop optimization technique is used. Further, and in order to highlight the JAYA algorithm performances, optimization using the PSO technique was also carried out for comparison regarding accuracy, rapidity and robustness. Table 2 presents the optimization results obtained using the constructed Kriging-based models as performance evaluators within the JAYA and PSO-based optimization kernel (denoted as Kriging-PSO and Kriging-JAYA, respectively). Hspice simulations were performed for evaluating the relative error.    Table 2 presents the optimization results obtained using the constructed Kriging-based models as performance evaluators within the JAYA and PSO-based optimization kernel (denoted as Kriging-PSO and Kriging-JAYA, respectively). Hspice simulations were performed for evaluating the relative error.  Figure 5 shows a comparison between the Hspice simulations of Rx performances obtained via Kriging-PSO and Kriging-Jaya for Ibias = 26 µA. (In order to not overload the paper, a unique case is presented.) Figure 6 gives a whisker boxplot relative to 50 executions of the Kriging-PSO and Kriging-Jaya of Rx performances.

Application 2: A differential-based Class AB CMOS CCII
The schematic of the considered differential-based class AB CMOS CCII [49] is shown in Figure  7. Similar to Application 1, the objective was to model and then minimize the parasitic X-port resistance in different bias current (Ibias) values: 100 nA, 250 nA, 1 µA and 10 µA. To this end, four models were constructed and validated. The same sizes for both databases were considered. The voltage power supply was Vdd/Vss = ± 0.6 V.

Application 2: A Differential-Based Class AB CMOS CCII
The schematic of the considered differential-based class AB CMOS CCII [49] is shown in Figure 7. Similar to Application 1, the objective was to model and then minimize the parasitic X-port resistance in different bias current (I bias ) values: 100 nA, 250 nA, 1 µA and 10 µA. To this end, four models were constructed and validated. The same sizes for both databases were considered. The voltage power supply was V dd /V ss = ± 0.6 V. Table 3 shows the relative errors of the models constructed for different bias currents, and Table 4 summarizes the Kriging-PSO, the Kriging-Jaya and the Hspice simulation results for the four cases of the bias current.  Table 3 shows the relative errors of the models constructed for different bias currents, and Table  4 summarizes the Kriging-PSO, the Kriging-Jaya and the Hspice simulation results for the four cases of the bias current. Table 3. Relative Error of the differential-based Class AB CMOS CCII.

Ibiais (µA) Relative Error (%)
0.10 0.829 0.25 0.386 1 0.092 10 0.007 Table 4. Obtained results for the Rx performance of the differential-based class AB CMOS CCII.  Figure 8 shows a comparison between the Hspice simulations of Rx obtained via the Kriging-PSO and Kriging-Jaya techniques, and Figure 9 gives a boxplot relative to 50 executions of the Kriging-PSO and Kriging-Jaya approaches.  Table 3. Relative Error of the differential-based Class AB CMOS CCII.

Application 3: An CMOS OTA-based CCII+
A CMOS OTA-based CCII+ [49] is shown is Figure 10. In this application, the objective was to model and minimize the parasitic X-port resistance for different bias current (Ibias2) values: 500 nA, 1 µA, 10 µA and 30 µA, where Ibias1 = 3 µA. Four models were constructed and validated, as shown in Table 5. The voltage power supply was Vdd/Vss = ±1V. The obtained optimization results corresponding to the application of the Kriging model as an evaluator within the Jaya/PSO sizing kernel are given in Table 6. A comparison with the results given in [9,49] is also provided.

Application 3: An CMOS OTA-Based CCII+
A CMOS OTA-based CCII+ [49] is shown is Figure 10. In this application, the objective was to model and minimize the parasitic X-port resistance for different bias current (I bias2 ) values: 500 nA, 1 µA, 10 µA and 30 µA, where I bias1 = 3 µA. Four models were constructed and validated, as shown in Table 5. The voltage power supply was V dd /V ss = ±1V. The obtained optimization results corresponding to the application of the Kriging model as an evaluator within the Jaya/PSO sizing kernel are given in Table 6. A comparison with the results given in [9,49] is also provided.    Figure 11 shows the Rx Hspice simulations corresponding to the sizing obtained by the application of the Kriging-PSO and Kriging-JAYA approaches for Ibias2 = 10 µA. Figure 12 gives boxplots relative to 50 applications of the Kriging-PSO and Kriging-Jaya approaches.  Figure 11 shows the Rx Hspice simulations corresponding to the sizing obtained by the application of the Kriging-PSO and Kriging-JAYA approaches for I bias2 = 10 µA. Figure 12 gives boxplots relative to 50 applications of the Kriging-PSO and Kriging-Jaya approaches.

Comparisons and Discussion
Tables 1, 3 and 5 show the viability of the proposed modeling technique. For comparison, the same circuits, as well as the same simulation conditions and the same operating mode adopted in [9] and [49], were considered. The same technology in [9], and the same bias conditions in [9] and [49] were adopted. Table 7 summarizes the results obtained using the constructed models within a PSO and a JAYA-based optimization kernel. The proposed approach allows for the same performances as when adopting the conventional in-loop technique but within a much-reduced computing time, as shown in see Table 7. It is to be mentioned that model generation and training takes approximately ten minutes. However, this is performed only once. Then, the model is used as it is within sizing/optimization loops, where its evaluation takes a couple of

Comparisons and Discussion
Tables 1, 3 and 5 show the viability of the proposed modeling technique. For comparison, the same circuits, as well as the same simulation conditions and the same operating mode adopted in [9] and [49], were considered. The same technology in [9], and the same bias conditions in [9] and [49] were adopted. Table 7 summarizes the results obtained using the constructed models within a PSO and a JAYA-based optimization kernel. The proposed approach allows for the same performances as when adopting the conventional in-loop technique but within a much-reduced computing time, as shown in see Table 7. It is to be mentioned that model generation and training takes approximately ten minutes. However, this is performed only once. Then, the model is used as it is within sizing/optimization loops, where its evaluation takes a couple of seconds. On the contrary, when using a simulator-based technique, each time the corresponding approach restarts from scratch. It is worth mentioning that the proposed Kriging-based optimization technique is more suitable for integration within a CAD tool, since it allows the computation time to be reduced approximately 100-fold.
Tables 2, 4 and 6 show that the JAYA algorithm performs results as accurate as those obtained using the well-known PSO metaheuristic. On the other hand, the robustness tests shown in Figures 6, 9 and 12, which were performed due to the intrinsic stochastic aspect of the metaheuristics, prove that JAYA is more robust than PSO. In order to further compare both metaheuristics, the Wilcoxon Signed-Rank Test [51] was preformed, with the statistical significance value a = 0.05, for 50 runs. Table 8 summarizes the obtained results where it is clear that, for the three cases, the JAYA algorithm's statistical performances outperform those of PSO. It is to be mentioned that the null hypothesis is considered for the Wilcoxon Signed-Rank test. For comparing both of the metaheuristics' performances, the alternative hypothesis was valid, and the ranks' sizes provided by the Wilcoxon test (i.e., T + and T-as defined in [51]) were examined.

Conclusions
It has been shown that Kriging-assisted JAYA-based LVLP circuit design offers an interesting approach that can be integrated within a CAD tool. This has been showcased via three CMOS current conveyors operating in the weak inversion mode. It has been shown that the proposed approach accurately models the performances of such circuits. Comparisons with Hspice simulations were performed for evaluating the accuracy of the established models. These models were then used as performance evaluators within an optimization kernel. The newly proposed JAYA algorithm was used for computing optimal parameters' values (mainly transistors' sizes). It has been shown that the JAYA algorithm, which does not need any predefined parameters, is much more robust than the PSO metaheuristic, while providing similar accurate performances.
The performances of the proposed approach have been compared to those proposed in the literature where the in-loop sizing technique is adopted. Comparable results have been obtained within a much-reduced computing time; an approximate 100-fold reduction.