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Low-Power CMOS Analog and Digital Circuits and Filters
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Low-Power CMOS Analog and Digital Circuits and Filters

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 October 2020) | Viewed by 25066

Special Issue Editor

Dr. Marcello De Matteis

E-Mail Website
Guest Editor
Department of Physics, University of Milano Bicocca, 1–20126 Milan, Italy
Interests: microelectronics; analog circuits; amplifiers; filters; A-to-D

Special Issue Information

Dear Colleagues,

CMOS technologies has always represented a key opportunity for smart and efficient mixed-signal systems design, covering several application fields (biomedical, physics and astrophysics experiments, sensors, telecommunication, Internet-of-Thing) having strong interest in fully-integrated solutions.

Integration of analog and digital circuits in the same die area is then sustained by the technological scaling-down, since lower power consumption can be achieved in mostly-digital systems due to the lower supply voltage.

Analog

The first interface of the mixed-signal systems with the external world is intrinsically analog. As a consequence, in order to achieve efficient and reliable circuits in deeply scaled and/or nm-range CMOS technologies, analog designers have to be able to manage the poor analog performance of the MOS transistors and at the same time to take advantage of the opportunities given by the increasing technological scaling-down. The scaling-down of the physical (length, size, etc.) and electrical (supply voltage) parameters leads to a significant improvement for digital circuits in terms of speed and power. This trend is not so automatic for analog circuits, since they experience severe drawbacks, like VDD/VTH decreasing (supply voltage and threshold voltage, respectively), higher sensitivity to Process-VoltageTemperature (PVT) variations, transistor intrinsic gain decreasing and in general higher power consumption.

Digital

Thanks to the increasing transition frequency of most recent CMOS technological process nodes, digital hardware is replacing several analog functions, representing an evident opportunity for high-data rate digital signal processing systems implementation. Digital designers must be able to operate in such stimulating scenario, where wide bandwidth digital signals have to be processed at higher speed and saving power.

Dr. Marcello De Matteis
Guest Editor

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • CMOS Integrated Circuits
  • Analog Filters
  • Analog Amplifiers
  • to-D/D-to-A Converters
  • Digital Filters
  • Low Power
  • Low Voltage

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Published Papers (7 papers)

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Research

11 pages, 1026 KiB  
Article
Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference
by Orazio Aiello
J. Low Power Electron. Appl. 2021, 11(1), 6; https://doi.org/10.3390/jlpea11010006 - 20 Jan 2021
Cited by 1 | Viewed by 3016
Abstract
The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution [...] Read more.
The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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11 pages, 877 KiB  
Article
Energy Efficiency in Slew-Rate Enhanced Single-Stage OTAs for Switched-Capacitor Applications
by Alessandro Catania, Mattia Cicalini, Massimo Piotto, Paolo Bruschi and Michele Dei
J. Low Power Electron. Appl. 2021, 11(1), 1; https://doi.org/10.3390/jlpea11010001 - 24 Dec 2020
Cited by 5 | Viewed by 3020
Abstract
Slew-rate enhancement (SRE) techniques assist the charge transfer process in OTA-based switched-capacitor circuits. Parallel-type slew-rate enhancement circuits, i.e., circuits that provide a feed-forward path external to the main OTA, are attractive solutions, since they introduce a further degree of freedom in the speed/power [...] Read more.
Slew-rate enhancement (SRE) techniques assist the charge transfer process in OTA-based switched-capacitor circuits. Parallel-type slew-rate enhancement circuits, i.e., circuits that provide a feed-forward path external to the main OTA, are attractive solutions, since they introduce a further degree of freedom in the speed/power consumption design space without affecting other specifications regarding the main OTA. This technique lends itself to be employed jointly with advanced OTA topologies in order to compose a highly energy efficient OTA/SRE system. However, insights in design choices such as power optimization are still missing for such systems. Here we discuss system level choices with the help of a simple model. Using precise electrical simulations, we demonstrate energy savings greater than 30% for different OTA/SRE systems implemented in a standard 180-nm CMOS technology. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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11 pages, 4160 KiB  
Article
A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments
by Federico Fary and Andrea Baschirotto
J. Low Power Electron. Appl. 2020, 10(4), 35; https://doi.org/10.3390/jlpea10040035 - 28 Oct 2020
Viewed by 2448
Abstract
This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), [...] Read more.
This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 µW. The total area occupancy is 1702 µm2 for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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10 pages, 3970 KiB  
Article
High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS
by Andrea Ballo, Alfio Dario Grasso, Salvatore Pennisi and Chiara Venezia
J. Low Power Electron. Appl. 2020, 10(3), 27; https://doi.org/10.3390/jlpea10030027 - 3 Sep 2020
Cited by 9 | Viewed by 3633
Abstract
Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order [...] Read more.
Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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12 pages, 4531 KiB  
Article
Evaluation of In Vivo Spike Detection Algorithms for Implantable MTA Brain—Silicon Interfaces
by Mattia Tambaro, Elia Arturo Vallicelli, Gerardo Saggese, Antonio Strollo, Andrea Baschirotto and Stefano Vassanelli
J. Low Power Electron. Appl. 2020, 10(3), 26; https://doi.org/10.3390/jlpea10030026 - 2 Sep 2020
Cited by 7 | Viewed by 4027
Abstract
This work presents a comparison between different neural spike algorithms to find the optimum for in vivo implanted EOSFET (electrolyte–oxide-semiconductor field effect transistor) sensors. EOSFET arrays are planar sensors capable of sensing the electrical activity of nearby neuron populations in both in vitro [...] Read more.
This work presents a comparison between different neural spike algorithms to find the optimum for in vivo implanted EOSFET (electrolyte–oxide-semiconductor field effect transistor) sensors. EOSFET arrays are planar sensors capable of sensing the electrical activity of nearby neuron populations in both in vitro cultures and in vivo experiments. They are characterized by a high cell-like resolution and low invasiveness compared to probes with passive electrodes, but exhibit a higher noise power that requires ad hoc spike detection algorithms to detect relevant biological activity. Algorithms for implanted devices require good detection accuracy performance and low power consumption due to the limited power budget of implanted devices. A figure of merit (FoM) based on accuracy and resource consumption is presented and used to compare different algorithms present in the literature, such as the smoothed nonlinear energy operator and correlation-based algorithms. A multi transistor array (MTA) sensor of 7 honeycomb pixels of a 30 μm2 area is simulated, generating a signal with Neurocube. This signal is then used to validate the algorithms’ performances. The results allow us to numerically determine which is the most efficient algorithm in the case of power constraint in implantable devices and to characterize its performance in terms of accuracy and resource usage. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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16 pages, 3082 KiB  
Article
Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design
by Amel Garbaya, Mouna Kotti, Mourad Fakhfakh and Esteban Tlelo-Cuautle
J. Low Power Electron. Appl. 2020, 10(2), 20; https://doi.org/10.3390/jlpea10020020 - 16 Jun 2020
Cited by 8 | Viewed by 3754
Abstract
Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used [...] Read more.
Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used within a metaheuristic-based optimization kernel in order to maximize the circuits’ sizing. The JAYA algorithm was used for this purpose. Three topologies of CMOS current conveyors (CCII) were considered to showcase the proposed approach. The achieved performances were compared to those obtained using conventional LVLP circuit sizing techniques, and we show that our approach offers interesting results. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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15 pages, 6149 KiB  
Article
Implementation of a Fractional-Order Electronically Reconfigurable Lung Impedance Emulator of the Human Respiratory Tree
by Elpida Kaskouta, Stavroula Kapoulea, Costas Psychalinos and Ahmed S. Elwakil
J. Low Power Electron. Appl. 2020, 10(2), 18; https://doi.org/10.3390/jlpea10020018 - 16 May 2020
Cited by 7 | Viewed by 4234
Abstract
The fractional-order lung impedance model of the human respiratory tree is implemented in this paper, using Operational Transconductance Amplifiers. The employment of such active element offers electronic adjustment of the impedance characteristics in terms of both elements values and orders. As the MOS [...] Read more.
The fractional-order lung impedance model of the human respiratory tree is implemented in this paper, using Operational Transconductance Amplifiers. The employment of such active element offers electronic adjustment of the impedance characteristics in terms of both elements values and orders. As the MOS transistors in OTAs are biased in the weak inversion region, the power dissipation and the dc bias voltage of operation are also minimized. In addition, the partial fraction expansion tool has been utilized, in order to achieve reduction of the spread of the required time-constants and scaling factors. The performance of the proposed scheme has been evaluated, at post-layout level, using MOS transistors models provided by the 0.35 μ m Austria Mikro Systeme technology CMOS process, and the Cadence IC design suite. Full article
(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)
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