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28 June 2026

23 Pages

A Scoping Review of Composite Evaluation Approaches for Software Architectures on Resource-Constrained Hardware

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Posgrado en Ingeniería para la Innovación Tecnológica, Unidad Académica de Ingeniería Eléctrica, Universidad Autónoma de Zacatecas “Francisco García Salinas”, Campus Siglo XXI, Carretera Zacatecas-Guadalajara Km 6, Zacatecas 98160, Zacatecas, Mexico
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Centro Universitario del Sur, Universidad de Guadalajara, Ciudad Guzmán 49000, Jalisco, Mexico
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Authors to whom correspondence should be addressed.
Appl. Sci.2026, 16(13), 6436;https://doi.org/10.3390/app16136436
This article belongs to the Section Computing and Artificial Intelligence
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Abstract

Background: Hardware-software co-design for resource-constrained systems requires evaluation methods that integrate multiple quality attributes rather than isolated performance indicators. Objectives: This scoping review maps composite evaluation approaches used to assess architecture-relevant software or system artifacts, including software architectures where applicable, on resource-constrained hardware, while distinguishing explicitly aggregated quantitative composite metrics from qualitative and user-centric forms of evaluation. Methods: Using a PRISMA-ScR-informed reporting structure, the review analyzes a curated corpus of publications to identify foundational quality attributes, evaluation mechanisms, target hardware platforms, and architectural trade-off methods. Title and abstract screening, full-text eligibility assessment, and data charting were conducted by two investigators, with a third investigator available to resolve discrepancies when necessary. Results: Within the reviewed corpus, a descriptive shift is observed from single-attribute optimization toward broader multi-attribute evaluation, including explicit objective functions, benchmark-guided system-level modeling, structured qualitative trade-off assessment, and Quality-of-Experience (QoE)-oriented evaluation. These mechanisms are reported across FPGA-based accelerators, ARM-based edge devices, low-end IoT frameworks, heterogeneous intelligent devices, and XR platforms. However, explicitly aggregated architectural-level composite metrics remain rare, and representative studies such as FLASH, HW-FlowQ, Monarch, and ILLIXR illustrate related but distinct evaluation forms, rather than a single unified metric family. Conclusions: The reviewed corpus indicates that composite evaluation approaches support architecture-relevant reasoning under hardware constraints, although further work is needed to improve reproducibility, operational consistency, and cross-domain validation.

1. Introduction

The decline of conventional CMOS scaling has fundamentally altered the landscape of computing, driving a pronounced shift towards specialized, heterogeneous systems-on-chip (SoCs) [1,2,3,4]. This era of domain-specific computing is particularly evident in resource-constrained edge devices deployed in fields like Extended Reality (XR), the Internet of Things (IoT), and autonomous systems. For these platforms, where power, latency, and area are critically constrained, this complexity necessitates composite evaluation frameworks that integrate multiple trade-offs, such as those implemented in Monarch [5] for hyperscale telemetry, and in ILLIXR [4] for immersive XR platforms. The traditional, siloed evaluation of software performance is no longer sufficient. Achieving desired system-level outcomes requires a deeply integrated approach to system design.
This paradigm shift has elevated hardware-software (HW/SW) co-design from a niche discipline to a critical, mainstream methodology [6,7,8,9,10,11]. In a co-design context, the software architecture and the underlying hardware are designed and optimized in tandem, forcing developers to manage complex trade-offs between often conflicting system goals. For example, an architectural choice that improves raw performance might lead to unacceptable energy consumption, while a design optimized for maintainability could introduce prohibitive latency. Evaluating these trade-offs requires metrics that can capture a holistic view of system quality.
In this manuscript, the term resource-constrained hardware is used as the main umbrella term for embedded, edge, and specialized platforms operating under explicit limits on power, latency, area, memory, or computing capacity. This includes not only classical embedded and IoT devices, but also ARM-based edge platforms, batteryless or energy-harvesting devices, FPGA/eFPGA accelerators, heterogeneous edge nodes, and domain-specific platforms whose evaluation is governed by tight resource or real-time constraints.
Accordingly, the primary objective of this scoping review is to map the landscape of composite evaluation approaches used for the holistic evaluation of architecture-relevant software or system artifacts designed for resource-constrained hardware, including software architectures where the primary studies report them explicitly. Within this broader family, the term composite metrics is reserved for explicitly aggregated quantitative formulations that combine multiple attributes through a defined operational expression, whereas qualitative trade-off frameworks and user-centric QoE-oriented evaluations are treated as related but distinct evaluation approaches. These approaches move beyond measuring individual characteristics like throughput or coupling and instead provide a structured basis for reasoning about the overall fitness of an architectural solution in its target hardware environment.
This report is structured as follows. Section 2 details the scoping review methodology employed to gather and analyze the findings. Section 3 presents the results, starting with foundational single-dimension quality attributes and progressing to the various forms of composite evaluation approaches identified in the reviewed corpus. Section 4 provides a discussion of the strategic implications of these findings, including their impact on development practices and the concept of architectural technical debt. Finally, Section 5 offers a conclusion and outlines promising directions for future work in this domain.

2. Materials and Methods

This review was designed as a scoping review and structured using the reporting categories of the PRISMA extension for Scoping Reviews (PRISMA-ScR). A scoping review approach was selected because the objective was to map how composite metrics and related composite evaluation approaches are defined, combined, and applied across heterogeneous hardware-software co-design contexts, rather than to estimate the effect of a single intervention. Title and abstract screening, full-text eligibility assessment, and data charting were conducted by two investigators, with a third investigator available to resolve discrepancies when necessary. The review should therefore be interpreted as a structured scoping synthesis with acknowledged methodological limitations, but not as a purely single-reviewer workflow.

2.1. Research Questions

The review was guided by a set of core research questions designed to investigate the landscape of architectural evaluation for resource-constrained systems. These questions are as follows:
  • RQ1: Which foundational quality attributes and individual metrics are used to evaluate software architecture in the context of resource-constrained hardware?
  • RQ2: How are these individual metrics combined or synthesized into explicit composite metrics, qualitative trade-off frameworks, or user-centric evaluation approaches to support trade-off analysis?
  • RQ3: What architecture-relevant software or system artifact classes and hardware platforms are most prominently discussed in recent HW/SW co-design literature?

2.2. Protocol and Registration

A protocol for this scoping review was registered in OSF Registries (DOI: https://doi.org/10.17605/OSF.IO/U85BV) and is available at https://osf.io/u85bv/ (accessed on 14 June 2026). The review questions, eligibility criteria, screening procedure, and data-charting categories were defined before full-text analysis and refined iteratively as the terminology used in the literature was mapped.

2.3. Information Sources and Search Strategy

The evidence base consisted of a curated corpus of peer-reviewed publications and research papers addressing software architecture evaluation, quality attributes, performance metrics, hardware-software co-design, edge computing, embedded systems, and specialized hardware platforms. The primary information sources used to identify candidate records were Web of Science, Scopus, and Google Scholar. Searches were conducted from December 2025 to January 2026, prior to submission of the present manuscript version in May 2026. Because the literature uses heterogeneous terminology, the corpus was screened using both metric-centered and broader trade-off concepts represented in the review questions: composite metrics, software architecture, quality attributes, hardware-software co-design, resource-constrained hardware, embedded systems, specialized accelerators, edge devices, latency, energy, performance, maintainability, and quality of experience.
The search logic used to identify and verify topical relevance can be represented as follows: (“software architecture” OR “software architectures”) AND (“composite metric” OR “composite metrics” OR “quality attribute” OR “quality attributes” OR “multi-objective” OR “trade-off”) AND (“hardware-software co-design” OR “embedded system” OR “edge computing” OR “resource-constrained” OR “specialized hardware” OR accelerator) AND (performance OR latency OR energy OR maintainability OR reliability OR portability OR “quality of experience”). This conceptual strategy was adapted to the syntax and filtering options available in each information source.
The records were organized and screened according to PRISMA-ScR principles. The initial identification stage yielded 512 records. After removing 120 duplicate entries, 392 unique records remained for title and abstract screening. A total of 188 records were excluded during screening because they did not explicitly address hardware constraints, software architecture evaluation, or multi-attribute evaluation approaches. The remaining 204 articles were assessed through full-text analysis. Finally, 38 articles were excluded because they did not meet the inclusion criteria related to trade-off analysis or metric formalization, resulting in 166 primary studies included in the final synthesis. The source-selection process is summarized in Figure 1.
Figure 1. PRISMA-ScR flow diagram illustrating the source selection process, including identification, screening, eligibility, and inclusion phases.

2.4. Eligibility Criteria

Sources were considered eligible when they described metrics, quality attributes, evaluation frameworks, or trade-off methods relevant to software architectures operating on resource-constrained hardware platforms. This included studies that either directly evaluated software architectures or presented hardware-aware optimization, co-design, or benchmark-driven analyses that materially informed architecture-level trade-off reasoning under hardware constraints. The review focused on sources published between 2015 and 2025 with sufficient English-language metadata and methodological detail for data charting. Studies were excluded when they focused only on software quality without hardware or deployment constraints, lacked a concrete metric or evaluation method, or did not support analysis of trade-offs among multiple system characteristics.
The inclusion and exclusion criteria are summarized in Table 1.
Table 1. Eligibility criteria used for source selection.

2.5. Selection of Sources of Evidence

Titles and abstracts were screened first to remove records outside the scope of the review. Full texts were then assessed against the eligibility criteria. The selection process prioritized evidence that explicitly connected software architecture decisions, or architecture-relevant system design choices, with hardware constraints and multi-attribute evaluation. Reasons for exclusion were recorded at the screening and full-text eligibility stages and summarized in the PRISMA-ScR flow diagram. Screening and eligibility assessment were conducted by two investigators, and any discrepancies were resolved through consultation with a third investigator. This procedure improves the robustness of study selection relative to a purely single-reviewer workflow, although it does not eliminate all sources of selection bias.

2.6. Data Charting and Data Items

The selected source documents were charted using a structured form derived from the research questions and eligibility criteria. The charting categories were refined iteratively during full-text assessment to maintain consistency in terminology across heterogeneous sources. Data charting was conducted by two investigators, and discrepancies were resolved through consultation with a third investigator when required. For each source, the extraction process identified the quality attributes discussed, any explicit composite metrics proposed, the target hardware platform, software architecture context, evaluation method, trade-off dimensions, the reported strengths and limitations, and the relationship between the study and hardware-software co-design. The charted data were synthesized narratively and organized into thematic categories: foundational quality attributes, quantitative composite metrics, qualitative trade-off frameworks, user-centric evaluation, practical deployment profiles, and methodological trends. The complete 166-study corpus-mapping matrix is provided as Supplementary Table S1, whereas the main text integrates representative and grouped evidence selected to illustrate the principal methodological categories and their contribution to the research questions.

2.7. Critical Appraisal and Synthesis

Because the purpose of this scoping review was to map the breadth and characteristics of the evidence rather than to produce a pooled effect estimate, a formal risk-of-bias assessment was not performed. Instead, each included source was examined for its relevance to the review questions, clarity of metric definition, explicitness of hardware constraints, and usefulness for trade-off analysis. Results were synthesized through descriptive tables, conceptual grouping, and narrative comparison across methodologies, hardware platforms, and quality attributes.

2.8. Methodological Limitations

The present review has methodological limitations despite the use of two-investigator screening, eligibility assessment, and data charting with third-investigator discrepancy resolution. In particular, the manuscript does not report formal inter-rater agreement statistics or an externally audited verification procedure across all review stages. As a result, the synthesis may still be affected by residual selection and extraction bias and should be interpreted as a structured descriptive mapping of the reviewed corpus rather than as an exhaustive error-free inventory. Future updates of this review would benefit from formal agreement reporting, externally auditable decision logs, and continued multi-reviewer consensus protocols across all review stages.

3. Results

This section presents the synthesized findings of the scoping review. Within the reviewed corpus, the results indicate a progression in evaluation methodologies, moving from a foundational vocabulary of individual quality attributes to broader multi-attribute evaluation approaches. These approaches support trade-off analysis that is increasingly relevant to contemporary hardware-software co-design.

3.1. Characteristics of Sources of Evidence

The included corpus comprises 166 sources of evidence addressing software architecture evaluation under hardware constraints, with emphasis on embedded systems, edge computing, heterogeneous accelerators, immersive systems, architectural quality assessment, and multi-objective optimization. The principal characteristics charted for each source were publication focus, target hardware platform, software architecture context, evaluation method, trade-off dimensions, and the presence of explicit or implicit composite metrics. These characteristics are reflected in the thematic syntheses presented throughout this section. Given the size of the corpus, the main text discusses representative studies in depth, maps a broader portion of the corpus by analytical role, and refers readers to Supplementary Table S1 for the complete high-level corpus-mapping matrix.
For complete corpus-level traceability, the additional included sources represented in Supplementary Table S1 are cited here as part of the evidence base [2,3,4,6,7,8,9,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96].
To make the synthesis transparent and traceable, the charted evidence was mapped by analytical role in Table 2. This corpus mapping distinguishes the sources used to establish the software-architecture and quality vocabulary, the studies that report explicit multi-attribute optimization mechanisms, the evidence that documents constrained or specialized deployment platforms, and the sources that support benchmark-guided, service-oriented, or user-centric evaluation. The table therefore provides an academic traceability structure linking groups of studies to the research questions, while the surrounding subsections discuss the representative mechanisms in greater detail. The complete high-level source-by-source corpus mapping for all 166 included studies is reported separately in Supplementary Table S1.
Table 2. Analytical mapping of the reviewed corpus by contribution to the synthesis.

3.2. Foundational Quality Attributes and Metrics

The literature identifies a wide array of individual metrics used to assess specific aspects of software architecture. These metrics form the building blocks for more complex evaluations.
The ISO/IEC 25010:2011 standard provides a widely accepted framework for organizing these metrics, categorizing them under high-level quality characteristics [99,152]. Key characteristics relevant to this review include maintainability, performance efficiency, reliability, and portability. A comprehensive review conducted by Silva et al. [99] provides a catalog of these foundational attributes and their associated metrics. A summary of the most pertinent examples is presented in Table 3.
Table 3. Foundational Quality Attributes and Associated Metrics.
Within the reviewed corpus, ISO/IEC 25010:2011 serves mainly as a foundational software-quality reference for organizing single-attribute metrics. The review also identified other composition frameworks, including explicit objective functions for hardware-aware optimization, Quality Attribute Scenarios (QAS) for structured qualitative trade-off reasoning, and Quality-of-Experience (QoE)-oriented outcome integration in interactive systems. Beyond the ISO/IEC 25010 [152] vocabulary, the reviewed studies operationalize deployment-specific attributes such as latency, energy or power consumption, area, memory footprint, throughput, resource utilization, end-to-end inference latency, queueing delay, availability, error-detection coverage, timing correctness, communication overhead, and QoS/QoE-oriented outcomes when evaluating ARM-based edge devices, Raspberry Pi-class nodes, FPGA/eFPGA platforms, low-end IoT frameworks, batteryless devices, heterogeneous intelligent devices, real-time task chains, service-function-chaining environments, fog architectures, and interactive service platforms [102,107,116,117,118,120,121,122,128,130,131,132,133,135,139,143,153,154,155].
While this catalog provides the necessary vocabulary for discussing architectural quality, individual metrics are insufficient for modern system design. They measure attributes in isolation, failing to capture the complex and often conflicting relationships between them. Effective co-design for resource-constrained hardware demands evaluation methods that make the trade-offs between these attributes explicit. Across the reviewed corpus, these individual metrics are subsequently combined or balanced in several recurring ways. Quantitative studies use explicit combinations such as accuracy-latency-energy-area [8], accuracy-latency-energy [3], accuracy-latency-energy-peak power [107], accuracy-power-latency-memory [154], computing-performance-memory-power models [128], resource-performance constraints in real-time edge machine-learning pipelines [131], communication cost and model-quality objectives under device heterogeneity [132], and mapping or memory-placement objectives for embedded and NoC-based systems [129,130]. Other studies rely on benchmark-driven comparisons of waiting time, receiving time, processing time, resource utilization, throughput, queuing behavior, timing correctness, and deadline-sensitive latency across ARM-based edge devices, embedded operating-system testbeds, real-time task chains, and virtualized service chains [121,133,139,155], or on QoS/QoE-oriented synthesis that links user satisfaction to technical parameters in service-oriented and simulation-based systems [135,151]. Taken together with the deployment-oriented synthesis later in the manuscript, Table 3 provides the single-attribute portion of the systematic metric inventory requested for this review.

3.3. Composite Evaluation Approaches in HW/SW Co-Design

Within the reviewed corpus, a recurrent pattern is the use of broader composite evaluation approaches to manage architectural trade-offs. However, only a small subset of the included studies explicitly defines architectural-level composite metrics through formal aggregation functions [3,8,102,106,107,154]. Most of the corpus instead relies on implicit multi-attribute reasoning, structured qualitative trade-off assessment, user-centric composite outcomes, or benchmark-guided system-level modeling [5,109,117,118,121,122,128,129,130,131,132,133,135,136,139,143,146,153,155,156]. Taken together, these distinctions provide a working taxonomy for interpreting how multi-attribute architectural evaluation is currently reported in the reviewed literature. These approaches can therefore be categorized into three primary forms, each suited to different design contexts: quantitative methods for automated design space exploration, qualitative methods for reasoning about complex trade-offs in legacy or large-scale systems, and user-centric methods for optimizing end-to-end experiential systems.
Figure 2 summarizes the conceptual relationships among the identified evaluation approaches and now highlights a broader portion of the reviewed corpus, including quantitative studies such as FLASH [8], HW-FlowQ [3], EdgeTran [107], Reg-TuneV2 [154], and mixed-precision FPGA co-design [106], the qualitative Monarch case [5], and user-centric QoE-oriented examples such as ILLIXR [4] and service-oriented SDN evaluation [135].
Figure 2. Conceptual map of composite evaluation approaches, illustrating the relationships among quantitative, qualitative, and user-centric forms of evaluation, together with representative methodologies reported in the reviewed corpus.
Together, Figure 2 and Table 4 provide the conceptual scaffold for interpreting the broader empirical synthesis presented in the following subsections.
Table 4. Comparison of composite evaluation approaches used for assessing software architectures and architecture-relevant software/hardware systems.

3.3.1. Quantitative Composite Metrics via Objective Functions

This approach uses a mathematical formula to combine multiple, distinct metrics into a single, optimizable score. This score serves as a direct, quantitative representation of the trade-offs between competing system goals, making it ideal for automated search and optimization algorithms.
Example 1 
(FLASH Framework). The FLASH framework for Neural Architecture Search (NAS), as reported in [8], exemplifies this approach with the objective function
f obj = θ A × L × E
where the expression is reproduced from the cited source rather than proposed in the present review. This function seeks to maximize test accuracy (θ) while simultaneously minimizing the hardware costs of chip area (A), inference Latency (L), and Energy consumption (E). By encapsulating these competing goals in a single equation, the framework can automatically explore the design space to find architectures that represent an optimal balance of software performance and hardware efficiency.
Example 2 
(HW-FlowQ Framework). Similarly, the HW-FlowQ co-design methodology uses a genetic algorithm guided by the fitness function F ρ = 1 − ψ * − ψ t · log ϕ * ϕ [3]. This formula balances the goal of maintaining high accuracy (ψ) against the benefits of improved hardware efficiency (ϕ, which can represent energy or latency). The logarithmic term rewards significant hardware gains, while the accuracy term penalizes solutions that deviate too far from a baseline, creating a powerful composite metric for navigating the HW-CNN co-design space.
Beyond these two anchor cases, additional quantitative studies in the reviewed corpus combine or jointly optimize multiple deployment metrics rather than treating predictive accuracy alone as sufficient. Hardware platform-aware BNN optimization explicitly balances predictive performance against implementation cost on heterogeneous target hardware [102]. Reg-TuneV2 targets embedded deployment by jointly considering accuracy, power, latency, and memory-aware model-size constraints [154]. EdgeTran profiles transformer models across mobile edge platforms and co-optimizes accuracy, latency, energy consumption, and peak power draw [107]. Likewise, mixed-precision CPU co-design on FPGA minimizes energy and area under accuracy constraints [106], while bit-line computing for edge AI couples model compression and hardware decoding to improve energy efficiency with bounded accuracy degradation [108]. Hardware-specialized acceleration studies extend this pattern to resistive neural accelerators, FPGA-based similarity estimation, FPGA-supported SVM classification, and resource-efficient eFPGA-targeted classification, where accuracy, throughput, resource use, and energy or implementation cost are evaluated jointly [101,105,112,113]. Related optimization-oriented studies also treat resource-constrained scheduling and platform mapping as multi-attribute search problems, as illustrated by iterative compilation optimization guided by metric learning [157], exact modulo scheduling for resource-constrained CGRAs [156], embedded data-placement optimization [130], NoC-based real-time application mapping [129], and high-accuracy multi-FPGA acceleration strategies that balance throughput, parallelism, and hardware efficiency [109]. These studies broaden the quantitative portion of the reviewed corpus beyond the recurring FLASH/HW-FlowQ pair and show that the combined metrics vary according to deployment goals and hardware context.

3.3.2. Qualitative Trade-Off Assessment via Structured Analysis

This approach employs a formal, structured process for reasoning about architectural trade-offs without necessarily reducing them to a single numeric score. It is particularly effective for communicating the complex, multi-faceted impact of architectural changes in large-scale or legacy systems.
Case Study (Google Monarch): The architectural re-design of Google’s Monarch monitoring system illustrates this method [5]. Crucially, the team used Quality Attribute Scenarios (QAS) to translate vague goals such as “high availability” into specific, measurable targets (e.g., “ ≥ 99.99 % of queries return successfully”), which guided the entire analysis [5]. They then modeled the existing and proposed architectures using UML component and sequence diagrams. This structured modeling process enabled a clear, qualitative trade-off analysis, summarized in Table 5, which shows the anticipated impact of the new design. This model-based reasoning served as a form of qualitative multi-attribute assessment, making complex architectural trade-offs explicit and debatable without reducing them to a single numerical score.
Table 5. Qualitative trade-off analysis for Monarch re-design [5].
Monarch is the clearest example of structured qualitative assessment in the strict sense. However, the broader corpus also contains architecture-relevant trade-off methods that remain interpretable without collapsing all criteria into one score. For example, SOLAR uses multi-target design-space exploration to reason about performance, power, energy, and efficiency across CPU/GPU/FPGA execution paths [158], heterogeneous serverless edge orchestration tunes weights across throughput, response time, energy efficiency, AI accuracy, and cost to support deployment decisions [143], and queue-aware service-function evaluation plus load-aware in-server flow scheduling use bottleneck-sensitive latency metrics to guide deployment choices in softwarized infrastructures [139,146]. These studies broaden the notion of architectural trade-off methods even when they are not expressed as purely qualitative scenario tables.

3.3.3. User-Centric Evaluation via Composite Outcomes

This approach evaluates a system based on a high-level, holistic metric that directly captures the end-user’s perceived quality. This is especially relevant for interactive, user-facing systems where the interplay of many low-level system characteristics determines the final experience.
Case Study (ILLIXR Testbed): The Illinois Extended Reality (ILLIXR) project advocates for evaluating XR systems based on end-to-end Quality-of-Experience (QoE) [4]. QoE is a composite user-oriented outcome that integrates numerous underlying factors, including motion-to-photon latency, display refresh rate, rendering quality, and power consumption. A failure in any one of these dimensions can ruin the user’s sense of immersion. In this context, QoE drives architectural decisions because it directly measures the system’s ability to fulfill its primary purpose from the user’s perspective; in the present review, however, it is treated as a user-centric evaluation approach rather than as a quantitative composite metric in the strict sense.
The reviewed corpus also contains user-centered integration strategies beyond XR. In service-oriented software-defined networking, QoS/QoE support is operationalized through adaptive prioritization, server selection, and multi-criteria routing based on an integral additive QoS criterion, thereby linking user satisfaction directly to technical network parameters [135]. Related service and simulation studies connect traffic control, scheduling, and response behavior to user-facing outcomes in smart-city WiFi and farm-simulation contexts [136,151]. This demonstrates that user-centric composite outcomes are not confined to immersive XR platforms, even though the underlying deployment settings differ substantially.
Beyond the conceptual comparison, Table 6 summarizes the practical deployment profiles identified in the reviewed corpus by relating software or system artifacts, deployment contexts, measured attributes, and composite evaluation mechanisms.
Table 6. Deployment-oriented synthesis of software or system artifacts evaluated on resource-constrained or specialized hardware.

3.4. Practical Deployment Profiles and Evaluation Targets

A practical question underlying this review is whether architecture-relevant software systems can in fact be deployed on resource-constrained hardware, or whether such environments are limited to highly optimized low-level routines. Within the reviewed corpus, the answer is that architecture-relevant deployment is not restricted to simple procedural code alone. The evidence includes structured software or system artifacts such as convolutional neural network inference pipelines [3,8,102,108], transformer models on mobile edge platforms [107], hardware-assisted low-end IoT operating-system frameworks [117], containerized edge software stacks on ARM-based devices [133], heterogeneous intelligent-device schedulers and performance models [128,153], real-time edge machine-learning resource optimizers [131], service-oriented accelerator-backed deep learning systems [158], low-end embedded operating-system validation environments [121], energy-aware or batteryless IoT hardware contexts [120,122], fog and smart-city networked architectures [124,125,136], cryptographic or safety-oriented hardware/software co-design cases [116], multi-FPGA molecular-docking acceleration pipelines [109], model-based FPGA dynamical accelerators [159], and immersive XR runtime stacks [4] when these are paired with constrained or specialized hardware platforms. At the same time, programming language was not a charted variable in the present review, so direct comparison against simple C or C++ implementations is outside the scope of the available evidence.
The practical synthesis therefore focuses on software or system artifacts, deployment hardware, measured attributes, and the mechanism used to integrate trade-offs. Representative target platforms in the reviewed corpus span in-memory and FPGA-based accelerators [3,8,159], mobile and ARM-based edge devices [107,121,133], low-end reconfigurable IoT and batteryless platforms [117,122], Raspberry Pi-class computing nodes [120], heterogeneous intelligent-device environments such as Jetson AGX Xavier and Cambricon MLU220 [128,131], distributed embedded and NoC-based systems [129,153], multi-FPGA clusters [109], and specialized latency-sensitive XR platforms [4]. From the perspective of RQ3, the corpus does not converge on a single classical architecture pattern; instead, it recurrently addresses architecture-relevant artifact classes such as inference pipelines, service-oriented accelerator-backed systems, containerized edge application stacks, hardware-assisted OS frameworks, distributed embedded schedulers, service-function chains, fog-computing and smart-city service architectures, hardware/software co-designed cryptographic kernels, physics-oriented model accelerators, and XR runtime stacks [4,107,109,116,117,121,124,125,129,131,133,136,139,143,153,158,159]. Qualitative reference cases such as Monarch remain important conceptually, but because they target server-scale infrastructure rather than constrained deployment hardware, they are retained in Table 4 and not in the deployment-oriented synthesis below.
This deployment-oriented synthesis demonstrates that the reviewed literature is not limited to low-level hand-optimized routines; rather, it includes multiple classes of software or system artifacts integrated with constrained or specialized hardware and evaluated through explicit trade-off-aware mechanisms. It also broadens the narrative coverage of the reviewed corpus beyond the small recurring subset discussed in the previous version by incorporating low-end IoT frameworks, ARM-based edge benchmarking, heterogeneous intelligent-device modeling, serverless edge orchestration, hardware-in-the-loop OS validation, service-function bottleneck assessment, batteryless IoT platforms, embedded memory optimization, real-time edge ML resource optimization, and model-based FPGA acceleration. Together, Table 3 and Table 6 provide a systematic inventory of the principal single-attribute metrics, deployment contexts, and composite evaluation mechanisms identified in the reviewed corpus.

3.5. Trends in Composite Evaluation Methodologies

The temporal analysis of the selected studies suggests an evolution in architectural evaluation practices within the reviewed sample. Earlier works relied more heavily on qualitative or single-metric evaluations, whereas later publications more frequently reported quantitative composite metrics and user-centric approaches.
Quantitative methodologies appear more frequently in later publications, particularly in automated design-space exploration, hardware-aware search, and resource-optimization frameworks such as FLASH [8], HW-FlowQ [3], EdgeTran [107], Reg-TuneV2 [154], mixed-precision FPGA co-design [106], resource-constrained CGRA mapping [156], real-time heterogeneous-edge ML optimization [131], and multi-objective federated learning under device heterogeneity [132]. In parallel, user-centric evaluation, especially Quality-of-Experience (QoE), becomes more visible in immersive and interactive systems and in service-oriented network settings, as exemplified by ILLIXR [4], QoS/QoE-oriented SOSDN evaluation [135], and simulation scheduling for user experience [151]. Figure 3 should therefore be interpreted as a descriptive synthesis of the reviewed corpus rather than as a direct field-wide measurement.
Figure 3. Descriptive trends in architectural evaluation approaches within the reviewed corpus (2016–2025), showing increased visibility of quantitative composite metrics and user-centric evaluation frameworks in later publications [3,4,8].

4. Discussion

4.1. Global Overview of Composite Evaluation Approaches

The results of this review carry significant strategic implications for the design and development of software on resource-constrained hardware. Within the reviewed corpus, the findings suggest a gradual broadening in how system quality is defined and measured, moving beyond isolated metrics toward more integrated perspectives on trade-offs. At the same time, the review also shows that explicit architectural-level composite metrics remain uncommon, and that much of the field still operates through implicit, benchmark-guided, or framework-based multi-attribute evaluation [102,109,117,118,121,128,129,130,131,132,133,135,139,143,153,156].

4.1.1. Key Trends

A prominent pattern in the reviewed sample is the movement away from isolated single-attribute optimization toward more holistic, multi-objective, and co-designed evaluation. For embedded and edge-oriented systems in particular, the reviewed studies suggest that software architecture is often evaluated in close relation to the hardware it targets. Frameworks like FLASH [8], HW-FlowQ [3], EdgeTran [107], Reg-TuneV2 [154], and mixed-precision FPGA co-design [106] exemplify this concept by treating hardware and software parameters as interdependent variables in a unified optimization problem, while Arch2End [153], MultiRuler [128], ChamelIoT [117], and PHiLIP on the HiL [121] show the same tendency in system-level modeling and deployment-oriented embedded frameworks.

4.1.2. Challenges and Limitations

Despite their usefulness, composite evaluation approaches introduce their own set of challenges. A primary difficulty lies in maintaining operational consistency across evaluation forms that do not share the same level of formalization. Quantitative objective functions, qualitative trade-off frameworks, and user-centric composite outcomes cannot always be compared directly, even when they address related architectural decisions. In addition, selecting appropriate weighting coefficients for quantitative objective functions remains difficult. As noted in the context of software-defined networks, this is not a trivial task, especially in dynamic environments where priorities may shift [135]. An incorrect weighting can lead an automated search algorithm to a suboptimal solution. Furthermore, there is an inherent tension between conflicting goals that cannot always be resolved by a single formula. The Monarch case study [5] provides a clear example, where improving maintainability and availability came at the direct cost of increased latency and resource consumption. Qualitative frameworks are important in these scenarios because they facilitate human-led decision-making about which trade-offs are acceptable.

4.1.3. Impact on Development Practices

These evaluation methods have the potential to influence development practices substantially. The use of quantitative composite metrics within automated frameworks like NAS (FLASH [8]) and genetic algorithms (HW-FlowQ [3]) shifts part of architectural design from a purely manual, intuition-based process toward a more data-driven and partially automated one. This enables the exploration of larger design spaces than would normally be feasible through manual reasoning alone, thereby supporting earlier and more evidence-based architectural decisions.

4.1.4. Connection to Technical Debt

Ultimately, the adoption of composite evaluation approaches may serve as a useful mechanism for the proactive management of architectural technical debt [1]. This occurs when a team optimizes for a single, short-term metric (e.g., time-to-market or immediate performance) at the expense of other crucial attributes like maintainability, portability, or energy efficiency. While this may yield a short-term benefit, it can also accrue “interest” in the form of increased future development costs, higher operational expenses (e.g., battery drain), and reduced system resilience. A composite evaluation framework makes these longer-term costs more visible during design-time reasoning, thereby helping teams justify architectural decisions that prioritize long-term system health over myopic optimization.

4.2. Practical Implications for Software/Hardware Integration

From a practical perspective, the reviewed corpus indicates that deployment on resource-constrained hardware is not limited to simple low-level routines. Instead, the evidence base includes architecture-relevant software or system artifacts such as CNN and transformer inference pipelines [3,8,102,107,108], service-oriented accelerator-backed systems [158], low-end IoT operating-system frameworks [117], heterogeneous serverless edge stacks [143], ARM-based containerized edge deployments [133], distributed embedded scheduling environments [128,153], real-time heterogeneous-edge ML systems [131], low-end OS validation frameworks [121], service-function chains [139], fog and smart-city service architectures [124,125,136], embedded memory and NoC-based application mapping cases [129,130], physics-oriented FPGA accelerators [159], multi-FPGA computational pipelines [109], and immersive XR runtime stacks [4]. These artifacts are evaluated through combinations of accuracy, latency, energy, area, resource utilization, throughput, memory usage, power, cost, communication overhead, queueing delay, timing correctness, and QoE-oriented outcomes, depending on the deployment context.
At the same time, the review does not support a direct language-level comparison between these artifacts and simple C or C++ implementations, because the programming language was not a charted variable. The practical implication of the present synthesis is therefore not a programming-language ranking, but a deployment-oriented mapping between software or system artifact classes, hardware constraints, and the metrics used to judge success at the software/hardware boundary.

5. Conclusions

The evaluation of architecture-relevant software or system artifacts for resource-constrained hardware has matured into a broader landscape of multi-attribute reasoning. Rather than treating all such methods as the same evaluative object, this review distinguishes explicit quantitative composite metrics from qualitative trade-off assessment and user-centric QoE-oriented evaluation. Within the reviewed corpus, these approaches collectively support hardware-software co-design by making architectural trade-offs more explicit, although explicit architectural-level composite metrics remain relatively rare. By synthesizing representative techniques from a broader portion of the reviewed corpus—including mathematical objective functions in automated search, benchmark-guided system-level modeling, deployment-oriented edge benchmarking, hardware-assisted IoT frameworks, service-oriented accelerator architectures, and QoE-oriented integration—this report offers a consolidated resource for researchers and practitioners navigating domain-specific system design under hardware constraints.

Future Work

The source documents highlight several promising avenues for future research that build directly upon the findings discussed in this report. In particular, the review suggests the need for a more operational and architecture-centered research agenda. Key directions include:
  • Operational definitions of architectural-level composite metrics: Future work should establish clearer formal criteria for distinguishing explicit composite metrics from broader multi-attribute evaluation approaches, especially in studies that combine software and hardware concerns without providing an explicit aggregation function.
  • Mapping evaluation approaches to architectural decisions: The reviewed corpus would benefit from follow-up studies that connect composite evaluation approaches more directly to software architecture patterns, styles, tactics, and design decisions, thereby improving the practical interpretability of the evaluation results.
  • Reproducible multi-reviewer evidence synthesis: Updated reviews should incorporate dual independent screening, duplicate charting, and consensus-based conflict resolution in order to improve reproducibility and reduce selection and extraction bias.
  • Cross-domain validation of user-centric and hardware-aware approaches: Building on examples such as ILLIXR and hardware-aware optimization frameworks, future research should examine whether user-centric and optimization-driven evaluation approaches can be translated into reusable architecture-level assessment procedures across multiple application domains.

Supplementary Materials

The following supporting information can be downloaded at: https://www.mdpi.com/article/10.3390/app16136436/s1, Table S1: Complete Corpus Mapping Matrix (166 Studies).

Author Contributions

Conceptualization, A.I.L.C. and J.R.G.R.; methodology, A.I.L.C.; investigation, A.I.L.C., J.R.G.R., C.E.B.y.G.L., A.J.L.V., R.S.A. and V.I.R.A.; formal analysis, A.I.L.C.; writing—original draft preparation, A.I.L.C.; writing—review and editing, A.I.L.C., J.R.G.R., C.E.B.y.G.L., A.J.L.V., R.S.A. and V.I.R.A.; visualization, A.I.L.C.; supervision, J.R.G.R.; project administration, A.I.L.C. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding. Funding sources of the included evidence were not charted consistently across the analyzed corpus and therefore were not synthesized separately in this review.

Institutional Review Board Statement

Not applicable.

Data Availability Statement

The protocol for this scoping review is openly available in OSF Registries (DOI: https://doi.org/10.17605/OSF.IO/U85BV; URL: https://osf.io/u85bv/ (accessed on 14 June 2026)). The high-level corpus mapping for the 166 included sources is provided in Supplementary Table S1. The data analyzed in this review are derived from the publications cited in the reference list.

Acknowledgments

The authors thank their academic institutions for their support during the preparation of this manuscript. During the preparation of this manuscript, the authors used OpenAI ChatGPT (GPT-5 family) for proofreading, formatting support, and assistance in organizing the supplementary corpus-mapping matrix. The authors reviewed and edited all outputs and take full responsibility for the content of this publication.

Conflicts of Interest

The authors declare no conflicts of interest.

Abbreviations

The following abbreviations are used in this manuscript:
HW/SWHardware-software
IoTInternet of Things
NASNeural Architecture Search
PRISMA-ScRPreferred Reporting Items for Systematic Reviews and Meta-Analyses extension for Scoping Reviews
QoEQuality of Experience
QASQuality Attribute Scenarios
XRExtended Reality

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