Parasitic Inductance Assessment of E-GaN DPT Circuit Through Finite Element Analysis

Abstract

This article explores the high-frequency characteristics of gallium nitride (GaN) power-switching devices and evaluates their application performance using a double-pulse test (DPT) circuit model. With the increasing adoption of GaN power-switching devices in high-performance and miniaturized electronic products, their low junction capacitance makes them highly suitable for high-frequency applications. However, parasitic inductance in the power loop can introduce resonance phenomena, impacting system stability and switching performance. To address this, this study integrates the parasitic parameters of printed circuit boards (PCBs) with the nonlinear junction capacitance characteristics of GaN devices. Finite element analysis (FEA) is employed to extract PCB parasitic inductance values and analyze their effects on GaN power-switching behavior. The findings indicate that precise extraction and analysis of parasitic inductance are critical for optimizing the performance of GaN switching devices. Additionally, this study investigates mitigation strategies to minimize parasitic inductance, ultimately enhancing GaN device design and reliability. The insights from this research provide valuable guidance for the development of GaN power devices in high-frequency applications.

1. Introduction

Gallium nitride (GaN) power-switching devices, resulting from advancements in power semiconductor technology, provide effective solutions for converters, achieving higher frequency and power density objectives. Contrary to conventional silicon power components nearing their operational limits, the incorporation of GaN and silicon carbide (SiC) in power converters has notably improved power density and efficiency, surpassing traditional silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). In the domain of wide-bandgap power components, silicon-based GaN lateral heterojunction power components gain prominence due to their fabrication on cost-effective, large-sized silicon substrates [1,2,3,4]. When analyzing GaN power-switching devices, the initial focus lies in the simplest double-pulse testing (DPT) circuit. However, a critical aspect often overlooked is the precise examination of switch devices in basic circuits. Various factors, including understanding the component’s operation, designing peripheral circuit elements, and considering printed circuit board (PCB) layouts, should also receive remarkable attention. Understanding how to interpret the contributions of diverse factors is imperative when scrutinizing waveforms.

The existing literature mainly focuses on the loss analysis of switching components, with limited attention paid to the parasitic inductance parameters of the surrounding PCB and the challenges associated with further reducing these parasitic parameters. Only a few analyses have been carried out on effectively capturing parasitic inductance or which frequency range should be targeted. Material theory suggests that copper properties are affected by the skin effect at both low and high frequencies, influencing its skin depth. As a result, the observed parasitic inductance and resistance may vary. This article will explore in detail how to choose an appropriate frequency range for capturing parasitic inductance [5,6,7].

GaN power-switching devices introduce additional complexities to the PCB layout as higher power switch frequencies are achieved [8,9,10]. In practical circuit applications, GaN structures exhibit relatively moderate junction capacitance, typically within the range of a few picofarads. However, parasitic inductance in PCB traces can escalate to the nanohenry range, leading to resonance between the parasitic inductance of PCB and the junction capacitance of GaN. This resonance may pose risks, exceeding the rated voltage of the component, thereby increasing the complexities of the PCB layout. This article primarily focuses on the basic DPT circuit, exploring strategies to mitigate parasitic inductance issues, with the anticipation that this conceptual framework can serve as a reference for diverse applications [11,12,13,14].

To achieve a comprehensive analysis, this study follows a structured approach:

A model is developed for DPT to establish key concepts in power-switching device analysis, including resonance conditions in the power loop, switching device junction capacitance, PCB parasitic inductance, and the use of fast Fourier transform (FFT) analysis on an approximated square wave to assess resonance magnitude. The turn-on and turn-off behavior of GaN power-switching devices is also examined to build a strong theoretical foundation [15].

Finite element analysis (FEA) simulations are performed on the PCB to extract parasitic inductance parameters from the main power loop. The extracted model is then validated through experimental tests to ensure accuracy. This approach provides deeper insights into factors affecting measured waveforms, reducing the risk of misinterpretations—especially in identifying resonance features during testing [16].

A detailed examination of GaN power-switching device modeling within DPT circuits is conducted, focusing on interactions between PCB parasitic inductance and GaN junction capacitance. Methods for extracting parasitic inductance and strategies for mitigating its effects are discussed. Experimental DPT circuit results validate the accuracy of the extracted model, further confirming the effectiveness of FEA simulations in determining PCB parasitic inductance parameters.

Therefore, this study aims to enhance our understanding of power electronics design, ultimately improving the performance and reliability of GaN power-switching devices. By addressing critical challenges related to PCB parasitic inductance, this work contributes to the advancement of high-frequency power conversion and the optimization of GaN-based power system designs.

2. Characteristic of Oscillations of Power Loops on Power E-GaN Switching Applications

Oscillations during switch transitions are primarily caused by the interaction between the switch’s parasitic capacitance (C_oss) and the PCB’s parasitic inductance (L_t). This section first provides a brief explanation of parasitic capacitance in E-GaN power-switching devices; then, an introduction into the principles and operation of the DPT circuit is provided. Based on these foundations, the analysis then extends to the effects of parasitic inductance on the circuit. This discussion enhances our understanding of the cause of resonance.

2.1. The Junction Capacitance of E-GaN

A detailed exploration of crucial parameters associated with GaN power-switching devices encompassing factors such as junction capacitance and nonlinear transconductance is provided. GaN power-switching devices share characteristics with general MOSFETs, featuring significant parameters such as C_ds, C_gd, C_gs, and R_int. To elaborate further, the three intrinsic capacitors in these devices are defined as follows: C_iss, the input capacitance, is obtained by totaling the gate-source capacitance (C_gs) and gate-drain capacitance (C_gd), representing the overall capacitance of GaN as observed from the input. C_oss, the output capacitance, is obtained by adding the drain-source capacitance (C_ds) and the gate-drain capacitance (C_gd), representing the total capacitance on the output side. C_rss, the reverse transfer capacitance, is synonymous with the gate-drain capacitance (C_gd). Their relationships between C_ds, C_gd, and C_gs are illustrated in Figure 1, depicting the junction capacitance of a GaN power-switching device.

$${\mathrm{C}}_{\mathrm{g}\mathrm{d}}={\mathrm{C}}_{\mathrm{r}\mathrm{s}\mathrm{s}}$$

(1)

$${\mathrm{C}}_{\mathrm{d}\mathrm{s}}={\mathrm{C}}_{\mathrm{o}\mathrm{s}\mathrm{s}}-{\mathrm{C}}_{\mathrm{r}\mathrm{s}\mathrm{s}}$$

(2)

$${\mathrm{C}}_{\mathrm{g}\mathrm{s}}={{\mathrm{C}}_{\mathrm{i}\mathrm{s}\mathrm{s}}-\mathrm{C}}_{\mathrm{r}\mathrm{s}\mathrm{s}}$$

(3)

Figure 1. Junction capacitance of a GaN power-switching device.

A curve-fitting method is used to extract the junction capacitance values at each bias voltage. These extracted values are applied in the mathematical model. The curve-fitting methods are used to capture trends and patterns in the data and to estimate junction capacitance values at specific voltage points. Such an analysis contributes to understanding the performance characteristics of junction capacitance, providing valuable information for further engineering design or optimization. The transconductance g_m plays a crucial role in GaN power-switching devices, with its significance underscored by its response to temperature variations. The transconductance diminishes as temperatures increase, resulting in a smaller g_m. Consequently, the Miller plateau becomes wider. This study seeks to establish a mathematical model specifically at room temperature. The transfer characteristic of GaN is nonlinear, as shown in Figure 2 [17].

Figure 2. Transfer characteristics of GS66516T at V_ds = 10 V.

GaN power-switching devices exhibit four distinct operating modes: OFF, the resistive region, saturation region, and third quadrant region (reverse operation region). In the OFF mode, the switch is completely disconnected, with only junction capacitance in operation. The resistive region mode signifies that the switch is in the resistance operating region, indicating an open state. The saturation region mode reflects the state during the transition process. Finally, the third region operating mode denotes that the switch is actively performing operations in the third region, distinguishing itself from the typical MOSFET and silicon carbide (SiC) operating modes. Figure 3 illustrates the four states, providing a clear depiction of the characteristics of the GaN switch in various operating modes [18].

Figure 3. Four operational states of GaN.

2.2. Modeling of DPT Circuit

Several articles have extensively explored the DPT intervals. In this specific study, the DPT circuit intervals are reexamined by incorporating a GaN power-switching device. Clear distinctions become evident when compared with SiC power-switching devices, especially during the turn-off time of states 6 and 7. Following thorough analyses of each state, the subsequent step involves deriving and solving differential equations, leading to the mathematical representation of waveforms. The modeling and experiments are based on the DPT circuit, as illustrated in Figure 4. The model considers the package and external circuit, parasitic inductances, internal resistances, and junction capacitance. In addition, Vin represents the main power loop for DC voltage. A voltage value of zero is applied to the high-side GaN, drive voltage pulses are applied to the low-side GaN, and the inductor L supports the load current.

Figure 4. DPT circuit.

To obtain a comprehensive understanding of the model, waveforms at each state are examined, and temporal considerations are incorporated to engage each junction capacitor of GaN in resonance within those states. This systematic approach seeks to provide a balanced perspective on the behavioral dynamics of each constituent element within every state, promoting a nuanced understanding of the overall dynamic processes inherent in the entire system, as shown in Figure 5 and Figure 6.

Figure 5. Operational ON/OFF switching states.

Figure 6. Timing diagram of ON/OFF switching states.

2.2.1. Turn-On Model

Prior to turning on the GaN power device, the inductor current i_L flows through the third area of the high-side GaN power device, and the voltage V_in is applied. The turn-on transition can be divided into four states as follows:

State 1 (t0–t1) [Figure 5a]: When the gate voltage (V_pulse) is applied, the gate current (i_g) begins charging the C_gs of the low-side GaN. At this point, with V_pulse < V_th (threshold voltage), the 2D electron gas (2DEG) in the low-side GaN is in the off state, resulting in no drain-to-source current. Then, the load current (i_L load) flows through the high-side GaN, which operates in the third quadrant. The equivalent circuit in state 1 can be represented as Equations (4)–(8):

$${\mathrm{V}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}={\mathrm{V}}_{\mathrm{p}\mathrm{u}\mathrm{l}\mathrm{s}\mathrm{e}}-{\mathrm{L}}_{\mathrm{g}}{\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{g}}}{\mathrm{d}\mathrm{t}}}-\left({\mathrm{R}}_{\mathrm{g}}+{\mathrm{R}}_{\mathrm{i}\mathrm{n}\mathrm{t}}\right){\mathrm{i}}_{\mathrm{g}}$$

(4)

$${\mathrm{V}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{L}}_{\mathrm{s}2}\left({\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{d}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)-{\mathrm{L}}_{\mathrm{t}}{\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{d}}}{\mathrm{d}\mathrm{t}}}-{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{H}}-{\mathrm{R}}_{\mathrm{l}}·{\mathrm{i}}_{\mathrm{d}}$$

(5)

$${\mathrm{V}}_{\mathrm{L}}=\mathrm{L}{\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{L}}}{\mathrm{d}\mathrm{t}}}$$

(6)

$${\mathrm{i}}_{\mathrm{d}}={\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)$$

(7)

$${\mathrm{i}}_{\mathrm{g}}={\mathrm{C}}_{\mathrm{g}\mathrm{s}}{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}$$

(8)

where ${\mathrm{L}}_{\mathrm{t}}={\mathrm{L}}_{\mathrm{s}1}+{\mathrm{L}}_{\mathrm{s}3}+{\mathrm{L}}_{\mathrm{s}4}+{\mathrm{L}}_{\mathrm{s}5}$.

State 2 (t1–t2) [Figure 5b]: When the gate voltage (V_pulse) increases above the threshold, the low-side GaN enters the saturation region, which is V_{gs_L} > V_gs(th); the impedance of the 2DEG starts to decrease; and the drain current, i_d, starts to rise. During this state, V_{ds_L} decreases due to di/dt-induced voltages across L and L_t. The load current (i_L) continues to flow through the high-side GaN, which operates in the third quadrant. The equivalent circuit in state 2 can be represented as Equations (5) and (9)–(11):

$${\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}={\mathrm{V}}_{\mathrm{p}\mathrm{u}\mathrm{l}\mathrm{s}\mathrm{e}}-{\mathrm{L}}_{\mathrm{g}}{\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{g}}}{\mathrm{d}\mathrm{t}}}-\left({\mathrm{R}}_{\mathrm{g}}+{\mathrm{R}}_{\mathrm{i}\mathrm{n}\mathrm{t}}\right){\mathrm{i}}_{\mathrm{g}}-{\mathrm{L}}_{\mathrm{s}4}\left({\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{g}}}{\mathrm{d}\mathrm{t}}}+{\displaystyle \frac{\mathrm{d}{\mathrm{i}}_{\mathrm{d}}}{\mathrm{d}\mathrm{t}}}\right)$$

(9)

$${\mathrm{i}}_{\mathrm{d}}={\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}·{\mathrm{g}}_{\mathrm{m}}+{\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)$$

(10)

$${\mathrm{i}}_{\mathrm{g}}={\mathrm{C}}_{\mathrm{g}\mathrm{s}}{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}+{\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)$$

(11)

State 3 (t2–t3) [Figure 5c]: After the current is completely commutated to the low-side GaN, the high-side GaN leaves the third quadrant of the 2DEG and blocks the DC voltage, thereby initiating the voltage reduction in the low-side GaN. At this moment, the C_gd of the low-side GaN is charged. At this point, a Miller voltage is achieved, that is, V_gs reaches V_plateau. During the voltage reduction period, the output capacitance (C_ds + C_gd) in the low-side GaN discharges into the 2DEG of the saturated region, resulting in energy loss. Simultaneously, the C_{ds_H} of the high-side GaN is charged with current from the DC bus and decoupling capacitors. The equivalent circuit in state 3 can be represented as Equations (5), (9), (11) and (12):

$${\mathrm{i}}_{\mathrm{d}}={\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}·{\mathrm{g}}_{\mathrm{m}}-{\mathrm{C}}_{\mathrm{d}\mathrm{s}}{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}+{\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)$$

(12)

State 4 (t3–t4) [Figure 5d]: Once the switch node voltage reaches the designated level, the device will transition to the Ohmic region, marking the completion of the conduction transient. The equivalent circuit for state 4 can be represented as Equations (5), (9), (11) and (13):

$${\mathrm{i}}_{\mathrm{d}}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{{\mathrm{R}}_{\mathrm{d}\mathrm{s}\_\mathrm{o}\mathrm{n}\_\mathrm{l}\mathrm{o}\mathrm{w}}}}+{\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)$$

(13)

2.2.2. Turn-Off Model

Prior to turning off the GaN transistor, the inductor current i_L passes through the R_dson of the low-side switch. The turn-off transition can be segmented into four states, each of which is analyzed in the subsequent sections.

State 5 (t4–t5) [Figure 5e]: The current load (i_L) remains in the ohmic region of the low-side GaN’s 2DEG as the gate voltage (V_pulse) decreases from the driving voltage to the Miller voltage (V_plateau). Simultaneously, the gate current (i_g) discharges the C_gs of the low-side GaN. No current flows into either C_ds of the GaN.

State 6 (t5–t6) [Figure 5f]: When the gate voltage reaches the Miller voltage, the impedance of the low-side GaN’s 2DEG rises, surpassing the R_dson and entering the saturation region. In addition, the load current begins to discharge into the C_ds of the high-side GaN. Most losses occur in this state, and the C_gd of the low-side GaN is discharged. The equivalent circuit in state 6 can be represented as Equations (5), (9), (11) and (14).

State 7 (t6–t7) [Figure 5g]: When the gate voltage falls below the threshold value, the 2DEG of the low-side GaN turns off completely, preventing any current from flowing through. The load current is subsequently redirected to charge the C_ds of the low-side GaN. During this state, no additional resistive losses occur; only lossless displacement is observed, including the energy stored in the C_ds of the low-side GaN. The equivalent circuit in state 7 can be represented as Equations (5), (9), (11) and (15):

$${\mathrm{i}}_{\mathrm{d}}={\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}·{\mathrm{g}}_{\mathrm{m}}+{\mathrm{C}}_{\mathrm{d}\mathrm{s}}{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}+{\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)$$

(14)

$${\mathrm{i}}_{\mathrm{d}}={\mathrm{C}}_{\mathrm{d}\mathrm{s}}{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}+{\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{d}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}-{\displaystyle \frac{\mathrm{d}{\mathrm{v}}_{\mathrm{g}\mathrm{s}\_\mathrm{L}}}{\mathrm{d}\mathrm{t}}}\right)$$

(15)

State 8 (t7–t8) [Figure 5h]: After the completion of charge displacement, voltage rise and current fall are achieved, enabling the entire load current to traverse the 2DEG in a diode-like mode within the high-side GaN. The equivalent circuit in state 8 can be expressed as Equations (4)–(8).

3. The Parasitic Inductance L_t of the DPT Circuit

When scrutinizing GaN switching components, the primary focus is on the junction capacitance within the GaN and the parasitic inductance generated by the PCB trace. These factors can lead to resonance phenomena in the power loop. Furthermore, the junction capacitance of the switching component is a noteworthy characteristic that merits attention because it is inherent to the component and its analysis offers significant observational value [13,19]. Nevertheless, the absence of appropriate settings for parasitic inductance in the power loop model may pose challenges related to insufficient measurement accuracy or misgauge during the analysis of switching components. This condition underscores the complexity of the problem, given variations in modeling methods across different technical studies [12,20]. Prior to delving into an in-depth exploration, prioritizing an understanding and resolution of the absence of a power loop model is crucial. This condition is vital to effectively isolate the junction capacitance of the switching component and the parasitic inductance of the PCB trace. The complete separation of these elements is essential for enhancing the precision of the analysis, enabling a more accurate evaluation of the component’s behavior within the power loop. Adopting this systematic approach establishes a more robust foundation for analysis and adeptly addresses the mutual interaction between components. The topic is divided into two sections for discussion. The first section explores the extraction of parasitic inductance in PCB design, focusing on effective extraction methods during the design process. This extraction is primarily based on the circuit routing. The second section delves into the placement of metal vias, including considerations such as the selection of via locations and ensuring appropriate connectivity. Strategic approaches to placing metal vias on the PCB are explored, involving the use of vias at different layers to meet specific design requirements. This approach aims to enhance our understanding of two critical aspects of PCB design, enabling more effective handling of parasitic inductance and metal via placement.

3.1. Using FEA Tool Extraction for Parasitic Inductance

When extracting the parasitic inductance of the power loop using Ansys 2023 Q3D software, material properties and related parameters must be considered. The software calculates inductance and resistance based on the properties of copper and relevant formulas, considering the skin effect. As frequency increases, the inductance and parasitic resistance characteristics of copper change, as shown in Figure 7. Therefore, a frequency sweep is required to capture data, particularly within the resonance range of GaN power-switching devices, to ensure an accurate evaluation of the impact of parasitic effects on circuit performance.

Figure 7. The relationship between the ACR and ACL and the skin depth.

Step 1: In examining the parasitic inductance model, the initial step involves verifying the current paths within the main power circuit of the DPT circuit. Throughout this procedure, emphasis is placed on the low-side GaN switch circuit. In the preceding section, a comprehensive analysis of the DPT circuit’s operation was provided. By contrast, this section is dedicated to extracting parasitic inductance. To accomplish this objective, an approach from the PCB perspective is necessary, with a focus on the power loop, as illustrated in Figure 8. The inductance of each trace segment can be determined using these paths. In summary, a clear understanding of the current loop in the low-side GaN of the DPT circuit can be attained through this analytical process. Moreover, pertinent information about the power loop from the PCB viewpoint can be grasped. A detailed understanding of the inductance characteristics of each trace segment is gained by extracting the main loop paths, contributing to a more profound understanding of the entire parasitic inductance model.

Figure 8. PCB of DPT circuit.

Step 2: When utilizing FEA tools to calculate parasitic inductance values, initially configuring the excitation source and the frequency scanning method is crucial. A voltage source is used to set the excitation source, and the excitation conditions are defined in a simulated manner. Simultaneously, selecting the frequency scanning method is highly important. Frequency scanning, typically ranging from low to high frequencies, is preferred to acquire parasitic inductance values across different frequency ranges. This approach facilitates the examination of performance variations in parasitic inductance at various operating frequencies. The stepping and range of the scanning should be predefined to ensure comprehensive coverage of the required frequency range.

Step 3: The obtained parasitic inductance is incorporated upon establishing the DPT mathematical model. This step determines the impact of parasitic inductance in the analysis, thereby creating a more comprehensive mathematical model. This analysis seeks to quantify the parasitic inductance present in DPT circuits, providing a clear understanding of potential uncertainties during the operation of switch components. The application of these analysis results in real-world scenarios allows for an accurate understanding and assessment of the performance of switch components. The ultimate objective is to mitigate uncertainties, enabling a precise analysis of the operation of switch components. This systematic approach contributes to enhancing the accuracy of DPT circuit analysis while ensuring accurate prediction and management of the potential impact of parasitic inductance on system performance in practical applications. Therefore, through this process, a thorough analysis of power switch components can be conducted.

3.2. Placement of Metal Vias

Understanding wire inductance begins with the fundamental formula for PCB trace inductance, from which further research and developments have evolved, as shown in Formula (16):

$${\mathrm{L}}_{\mathrm{P}\mathrm{C}\mathrm{B}\_\mathrm{t}\mathrm{r}\mathrm{a}\mathrm{c}\mathrm{e}}={\mathrm{\mu }}_0{\displaystyle \frac{\mathrm{h}}{\mathrm{\omega }}}\mathrm{l}$$

(16)

where μ₀ is the vacuum permeability, h is the distance between two PCB traces, w is the width of the PCB trace, and l is the length of the PCB trace. This section addresses the method used to place the metal vias to minimize parasitic inductance and to prevent oscillations caused by the switch devices’ parasitic capacitance and parasitic inductance on the power loop, which can occur at frequencies in the megahertz range. The PCB traces are simplified to straight lines based on fundamental principles. Four different metal via layouts are used to define the inputs and outputs consistently. Scan parameters are initially set to default values, with a trace width of 10 mm and a trace length of 18 mm, as listed in Table 1. Sequential drilling is employed to observe the impact of metal vias on changes in parasitic inductance, as shown in Table 1.

Table 1. Model parameters for frequency sweep.

Model	Figure 9a	Figure 9b	Figure 9c	Figure 9d
Metal vias (pcs)	0	9	18	27
Length (mm)	18
Width (mm)	10
Thickness (mm)	0.03556

Figure 9a displays a flat trace without any vias. In Figure 9b, a single row of metal vias is shown, totaling nine vias. Figure 9c depicts the placement of two rows of metal vias, resulting in 18 vias. Figure 9d shows three rows of metal vias dispersed from input to output, with a total of 27 vias. Using FEA software, parasitic inductance and resistance values were extracted from the PCB copper at different frequencies to observe the effects of these four distinct via placements. The ACL (Figure 10) and ACR (Figure 11) curves, plotted based on frequency variations, demonstrate that increasing the number of vias helps reduce parasitic inductance and resistance.

Figure 9. Placement of metal vias for a two-layer trace. (a) A flat trace without any vias; (b) A single row of metal vias, nine vias; (c) Two rows of metal vias, eighteen vias; (d) Three rows of metal vias, twenty-seven vias.

Figure 10. Metal vias vs. ACL vs. frequency.

Figure 11. Metal vias vs. ACR vs. frequency.

As the number of vias increases, the total volume of copper also increases. Therefore, the total amount of these four different types of copper is normalized. For example, in Figure 7, l_copper remains constant, and skin depth is also a fixed value, determined based on the extracted frequency. The radius of the circle, r, varies with the total volume, with the extent of this variation depending on the total volume size. As a result, an increase in vias leads to a larger copper area. Based on the fundamental resistance formula, the calculated resistance decreases, while the fundamental inductance formula indicates a corresponding decrease in inductance.

Proper via placement is crucial, and Table 2 provides the ACL and ACR values under various frequency conditions; dispersing the vias effectively reduces parasitic inductance.

Table 2. The model parameters based on the frequency sweep placement.

Model	(a)	(b)	(c)	(d)
	ACL (nH)
10 M	8.501	7.459	7.419	7.417
100 M	8.444	7.423	7.386	7.385
1 G	8.426	7.412	7.375	7.375
	ACR (mΩ)
10 M	5.917	3.808	3.559	3.485
100 M	17.231	11.007	10.133	9.882
1 G	53.039	33.780	30.924	30.115

The effect of parasitic inductance should be enhanced to address potential compromises in layout integrity stemming from mechanical issues, albeit within a trade-off context. The solution elucidated in the preceding section, aimed at mitigating inductance, is extrapolated to tangible circuit applications. This strategy involves implementing a dispersed approach to further attenuate parasitic inductance within the PCB trace. After FEA simulations, the acquired inductance data can be assimilated into an established mathematical model for validation, thereby affirming the reduction in inductance. Consequently, this reduction curtails oscillations linked to the junction capacitance of switch devices. Prior to discussing the results, the four nomenclatural definitions pertaining to the copper plane, namely, Vin+, Vin−, PH, and GNDL, are explained. Following this elucidation, an examination of the specified inductance values outlined in each section is presented, as shown in Table 3. Figure 12a illustrates the design, relying exclusively on copper plane connections, abstaining from the implementation of a dispersed layout methodology. By contrast, Figure 12b introduces a modification by adopting a dispersed layout approach, incorporating the interconnection of discrete PCB layers through the integration of metal vias. The figure clearly shows the implications of the dispersed layout approach, revealing a clear diminishing trend in parasitic inductance values as the frequency progressively increases.

Table 3. Extracting separate parasitic inductance values (a) without and (b) with dispersed vias.

Freq [Hz]	Vin+ [nH]		Vin− [nH]
	(a)	(b)	(a)	(b)
10 M	7.312	5.705	0.946	0.840
100 M	7.175	5.574	0.938	0.830
1 G	7.132	5.533	0.935	0.827
Freq [Hz]	PH [nH]		GNDL [nH]
	(a)	(b)	(a)	(b)
10 M	20.090	14.935	1.707	1.628
100 M	19.868	14.665	1.684	1.602
1 G	19.797	14.579	1.677	1.594

Figure 12. (a) Without and (b) with dispersed vias.

The test waveform results estimated from the two boards show minimal differences compared with the finite element analysis results, approximately ±2 nH, as shown in Table 4.

Table 4. Extracting combined parasitic inductance values (a) without and (b) with dispersed vias and a comparison of test values.

	(a) Without Dispersed Vias		(b) With Dispersed Vias
	ACL [nH]		ACL [nH]
Freq [Hz]	FEA	Testing	FEA	Testing
10 M	31.707	29.455	24.327	25.959
100 M	31.307		23.881
1 G	31.181		23.740

4. Experimental Validation

4.1. Parasitic Inductance L_t and the C_oss of E-GaN

The inductor L_t on the PCB, alongside the parasitic capacitance C_oss of the switching component, forms a resonant circuit. By applying the formula for a basic RLC series resonant circuit, as shown in Formula (17), the relationship between these components can be analyzed. The parasitic capacitance C_oss of a commercially available E-GaN power-switching device typically ranges from 50 to 150 pF. Similarly, the parasitic inductance L_t on the PCB generally falls between 5 and 50 nH for standard PCB traces.

To illustrate the impact of these parameters, the curves plotted in Figure 13 are visible, which show the variation in resonance frequency. This frequency ranges approximately from 50 to 450 MHz. Based on these findings, a frequency sweep method can be employed in finite element analysis (FEA) software to extract the parasitic inductance values from the PCB.

$${\mathrm{frequency}}_{\mathrm{ringing}}={\displaystyle \frac{1}{2\mathrm{\pi }\sqrt{{\mathrm{L}}_{\mathrm{t}}·{\mathrm{C}}_{\mathrm{oss}}}}}$$

(17)

Figure 13. The resonance frequency vs. C_oss.

When the power-switching devices toggles, the drain-to-source voltage (V_ds) of the switching device exhibits a square wave pattern, making it crucial to monitor this input voltage condition. To analyze its frequency-domain characteristics, fast Fourier transform (FFT) analysis can be applied, treating the V_ds waveform as a fundamental square wave, as shown in Figure 14. This approach enables a more in-depth investigation of the resonant effects generated by the fundamental V_ds square wave on the PCB’s parasitic inductance (L_t) and the parasitic output capacitance (C_oss) of the switching component.

Figure 14. The FFT analysis of V_ds of the approximate square wave. (a) Increasing switching frequency; (b) Increasing input voltage; (c) Adjusting the duty cycle; (d) Increasing the fall time of the V_ds voltage.

As the switching frequency increases, the influence of the basic square wave of V_ds on the resonance amplitude becomes more pronounced, as shown in Figure 14a. Similarly, an increase in the input voltage results in a higher amplitude, as shown in Figure 14b. Furthermore, when adjusting the duty cycle, the maximum amplitude usually occurs at a 50% duty cycle, as shown in Figure 14c. Changes in switching frequency, duty cycle, or input voltage primarily affect the amplitude, which corresponds to the changes along the Y-axis of the curve.

Another important factor to consider is the fall time and slope of the V_ds voltage. Different fall rates result in variations in the spectral changes, and the slope of the fall is influenced by the switching current and the C_oss parameter. As illustrated in Figure 14d, in the basic square wave approximation, an increase in the fall rate of the V_ds voltage (i.e., when the V_ds voltage drops faster) causes the frequency range of the first wave to shift upward.

Examining the impact of the V_ds on the FFT curve reveals important insights regarding the Lt and C_oss curves. A decrease in resonance frequency, as indicated by L_t and C_oss, generally suggests an increase in parasitic inductance. This increase leads to higher resonance amplitude, which subsequently affects the oscillation of the switching current. Additionally, it results in a greater overlap between V_ds and I_ds, ultimately increasing switching losses. For instance, when the commercial switch devices, identified as GS66516T, operate under a 350 V condition with a C_oss of approximately 120 pF, the parasitic inductance can vary from 10 to 50 nH at a 50% duty cycle. This can be assessed through the square wave FFT curve, which shows resonance frequency points within the range of 65 to 150 MHz, as highlighted in the red area in Figure 14.

To verify this phenomenon, simulation software was used to observe the time-domain waveforms, as shown in Figure 15. A lower frequency results in greater energy overlap between V_ds and I_ds at the switching point, leading to an increase in switching losses. Additionally, Figure 16 presents the actual circuit test results, confirming the simulated trends and demonstrating the impact of different parasitic inductance values.

Figure 15. Simulation with different L_t values.

Figure 16. Comparison of L_t in a real circuit and the turn-on energy of V_gs. CH1: V_gs; CH2: V_ds; CH3: I_ds; Math: Energy, CH2*CH3.

From the test results in Figure 16, an analysis of the I_ds current at the switching point allows for an estimation of the parasitic inductance, and the inductance value can be calculated using Formula (17). As parasitic inductance increases, the V_ds slope falls slower, contributing to higher switching losses. Therefore, minimizing parasitic inductance during the PCB layout process is crucial for improving switching efficiency, making it a key aspect of PCB design.

This section examines the characteristics by approximating the voltage on the switch as a square wave and performing an FFT frequency domain analysis. It also introduces the working principle of the DPT circuit and the interaction between parasitic capacitance on the switch and parasitic inductance on the PCB. These analyses provide a deeper understanding of their roles and relationships in switching operations.

4.2. Circuit Validation and Test Configuration

The DPT circuit utilizes a modular design to ensure testing under the same conditions. The board includes half-bridge transistors, decoupling capacitors, and gate drivers. Here, we briefly introduce the testing parameters of the DPT circuit: time is adjusted based on fixed inductance, current, and voltage, following values specified in Figure 17. For example, under testing conditions of 350 V, 5 A, and 370 µH, the required time is 5.28 µs. During the design process, the charging inductor’s timing is adjusted with reference to the actual parameter. In the entire system, the digital signal processor is responsible for providing gate signals through optical fibers. Simultaneously, precise voltage measurements are made using passive (high-bandwidth) probes. The switching current on the measurement path is measured using a low-inductance current shunt through a BNC coaxial cable. During testing, the primary step is to calibrate the probes. This strategy is crucial because GaN components have extremely fast switching speeds, reaching levels in the nanosecond range. Any delay in voltage and current waveforms could potentially affect accuracy. Therefore, calibrating the probes becomes crucial, as shown in Figure 18, where each probe is adjusted to the same starting and ending points. When selecting an oscilloscope, a higher resolution is recommended to ensure that the probes have sufficient bandwidth for accurate measurements, as shown in Table 5.

Figure 17. Illustration of DPT.

Figure 18. Calibration of each probe. All probes move in sync, as highlighted by the red circles.

Table 5. List of test parameters.

Instruments
Oscilloscope	RTO2034 3 GHz 10 GSa/s
Passive probe Vgs	500 MHz, 10 pF
Passive probe Vds	High voltage, 250 MHz, 10 pF
BNC coaxial cable Ids	Low-inductance current shunt
The Board Parameters
Test condition	350 V, 5 A
Device	GS66516T (Infineon Technologies, Neubiberg, Germany)
Turn-on resistor	10 Ω
Turn-off resistor	2 Ω

A comparison of tests between two boards is provided in Figure 19. As shown in Figure 20, the absence of dispersed vias leads to more severe ringing. The V_gs comparison reveals that without dispersed vias, the turn-on process exhibits a noticeable delay, which correlates with the increased ACL and ACR discussed in the previous section. It was previously noted that as inductance increases, the current ringing time also extends, which increases the crossover area.

Figure 19. Boards (a) without and (b) with dispersed vias.

Figure 20. Comparison of V_gs, V_ds, and I_ds without and with dispersed vias.

Figure 16 shows the turn-on V_gs, and Figure 21 shows the turn-off V_gs. The test results for turn-on switching with dispersed vias show an energy consumption of 36.353 µW·s, whereas without dispersed vias, it is 38.827 µW·s, resulting in a difference of 2.47 µW·s. The test results for turn-off switching with dispersed vias show an energy consumption of 8.5024 µW·s, whereas without dispersed vias, it is 9.0543 µW·s, resulting in a difference of 0.5519 µW·s, as shown in Table 6.

Figure 21. Comparison of the turn-off energy of V_gs. CH1: V_gs; CH2: V_ds; CH3: I_ds.

Table 6. Comparison of parasitic inductance and measured switching energy losses.

Parameter	Figure 12a	Figure 12b
Extracted Inductance (Measurement) Lt	29.455 nH	25.959 nH
Ringing Frequency frequencyringing	77.012 MHz	82.034 MHz
Turn-On Energy Eon	38.827 µW·s	36.353 µW·s
Turn-Off Energy Eoff	9.0543 µW·s	8.5024 µW·s

5. Conclusions

This study provides an in-depth analysis of E-GaN switching components, establishing a thorough understanding of the DPT basic circuit platform through detailed circuit analysis. Building on this foundation, the investigation reveals oscillation issues, emphasizing the impact of parasitic inductance in the PCB power loop on switching losses. FEA and measurement results indicate that parasitic inductance varied by approximately ±2 nH during testing. By optimizing the distributed metal layout, parasitic inductance was effectively reduced by about 5 nH, leading to an approximate reduction of 2 µW·s in energy consumption for practical circuit applications. Additionally, this approach enhances the accuracy of switching device evaluations. Through a systematic analysis of the key parameters, this study not only highlights the effects of various circuit components but also introduces precise data estimation methods, providing valuable insights for improving the circuit performance and optimizing the power loop design.