Design and Implementation of a High-Efficiency T-Type Three-Level Inverter for Interior Permanent Magnet Synchronous Motor Drive Systems ^†

Abstract

This study presents a high-efficiency T-type three-level inverter for interior permanent magnet synchronous motor (IPMSM) drive applications, featuring a comprehensive performance comparison with a conventional two-level inverter. To address the high switching losses and noticeable harmonic distortion typically associated with conventional two-level configurations, the T-type architecture is developed and evaluated. First, PLECS simulations are conducted to verify the proposed dual-loop control architecture, which integrates field-oriented control (FOC), space-vector pulse-width modulation (SVPWM), and a neutral-point voltage balancing mechanism. Subsequently, a 2.2 kW experimental platform is constructed using silicon carbide (SiC) wide-bandgap (WBG) semiconductor devices. To characterize the dynamic switching behavior of the adopted SiC MOSFETs, a dedicated double-pulse test (DPT) platform is developed to evaluate their switching losses and determine appropriate gate-drive parameters. In addition, the digital control firmware is implemented on a digital signal processor (DSP) platform. The dual-loop control algorithms, SVPWM strategy, and two-layer protection framework are implemented as real-time executable routines, enabling close integration of the control software and hardware platform. Finally, motor drive experiments at switching frequencies of 20 kHz and 40 kHz are performed to validate the proposed system. The experimental results demonstrate that the developed architecture significantly reduces phase-current total harmonic distortion (THD) and improves overall energy conversion efficiency compared with a conventional two-level inverter, confirming its potential for high-efficiency next-generation electric vehicle applications.

1. Introduction

As global climate change intensifies and environmental awareness continues to increase, stringent regulations on internal combustion engine vehicles have made EVs [1,2] an inevitable global trend. Consequently, the efficiency of power inverters and electric motors has become increasingly critical. Optimizing energy conversion efficiency extends vehicle range, reduces the size of the cooling system, and enhances overall reliability under demanding operating conditions. Thus, developing advanced inverter topologies and high-efficiency motors [3] has become an important research focus in both academia and industry.

AC drive systems [4] offer several advantages over DC drive systems, including lightweight construction, efficient regenerative braking, robustness, reliability, and near-maintenance-free operation, all of which are essential for EV applications. Among AC motors, compared with induction motors (IM), the rotor of a permanent-magnet synchronous motor (PMSM) utilizes permanent magnets. Consequently, the stator current does not need to supply magnetizing current, resulting in a higher power factor and efficiency at the same output. Furthermore, PMSMs [5,6,7,8] dominate the EV motor sector due to their strong overload capacity and high efficiency during acceleration and deceleration.

Power semiconductors directly affect the efficiency of power converters. As traditional silicon (Si) devices approach their physical limits, wide-bandgap materials such as SiC and gallium nitride (GaN) are gaining prominence. Compared with conventional Si devices, WBG devices [9,10] possess higher critical breakdown electric fields and lower on-resistance, enabling operation at higher voltages, frequencies, and junction temperatures while reducing switching losses.

Recent comparative evaluations of Si, SiC, and GaN devices in inverters have demonstrated that wide-bandgap materials can further elevate system efficiency [11]. Among these devices, SiC has achieved broader adoption than GaN in EV traction inverters and high-voltage converters, primarily due to its superior thermal conductivity, which supports efficient thermal management in compact, high-power modules [12]. Although GaN offers high switching speeds, its low gate-threshold voltage and narrow allowable gate-voltage range make it susceptible to oscillations caused by parasitic inductance under high dv/dt conditions, increasing the risk of false triggering. Consequently, SiC MOSFETs remain preferred for high-reliability applications due to their mature technology and robust thermal performance.

Dynamic characterization [13,14] is essential for power electronics design, providing insights into the switching behavior, efficiency, and thermal performance of semiconductor devices under actual operating conditions. The DPT circuit architecture [15], comprising the power module, DC capacitors, gate driver, and load inductor, is widely used to evaluate the dynamic performance of power modules.

Three-level inverters, such as neutral-point-clamped (NPC) and T-type topologies, offer reduced switching losses, lower semiconductor voltage stress, higher power density, and improved harmonic performance compared with traditional two-level voltage-source inverters (VSIs) [16,17,18]. The T-type inverter is particularly suitable for low- to medium-voltage applications, including EV drivetrains below 800 V [19]. It retains the low conduction losses of conventional two-level VSIs because its asymmetrical voltage distribution allows the main switches to withstand the full DC-link voltage, while the neutral-point switches withstand only half, enabling lower-voltage devices with lower on-resistance. In addition, fewer components than the NPC topology simplify control and system design. By balancing switching and conduction losses, the T-type inverter [20,21,22] provides high-efficiency power conversion with reliable performance in automotive applications.

Despite these advancements, many existing studies evaluating the T-type topology lack direct experimental comparisons with conventional two-level configurations. To explicitly address these literature gaps, this study develops a high-efficiency SiC-based T-type three-level IPMSM drive system to demonstrate its advantages over the conventional two-level baseline. The main contributions of this work include utilizing a dedicated DPT platform to optimize gate-drive parameters, implementing a simplified carrier-based SVPWM strategy integrated with dual-layer protection on a DSP platform, and conducting an experimental comparative evaluation. Ultimately, this study systematically visualizes the benefits of the T-type architecture, highlighting its superior energy conversion efficiency and significant reduction in phase-current THD compared to the traditional two-level inverter under practical operating conditions.

This article is a revised and expanded version of a paper (Paper No. K260193) [23] entitled “Development and Performance Analysis of a High-Efficiency Interior Permanent Magnet Synchronous Motor Drive System Based on a T-type Three-Level Inverter”, which was presented at the 9th International Conference on Knowledge Innovation and Invention 2026 (ICKII 2026), Sendai, Japan, 14–16 August 2026.

This study is organized into seven sections. A brief outline of each section is presented as follows: Section 1 introduces the research motivation, background, and literature survey, followed by the organization of the paper. Section 2 provides an overview of the fundamental characteristics of permanent magnet synchronous motors and the operating principles of the T-type three-level inverter. Section 3 describes the system simulation constructed in the PLECS environment. It details the FOC strategy integrated with SVPWM and verifies the effectiveness of the neutral-point voltage balancing control for the T-type architecture. Section 4 presents the dynamic characterization of power modules using the double-pulse test. Section 5 focuses on the real-time firmware architecture developed on the DSP platform. It details the progressive firmware expansion from basic motor control to specific T-type logic, including the allocation of computational tasks to the control law accelerator and the implementation of a dual-layer system protection framework. Section 6 provides comprehensive experimental results and performance comparisons between the conventional two-level reference and the proposed T-type inverter. It evaluates the conversion efficiency and phase-current THD under different switching frequencies. Section 7 summarizes the major contributions and conclusions of this research and proposes several potential directions for future investigation.

2. Configuration and Control of the Proposed T-Type IPMSM Drive

This section introduces the power-stage configuration and control architecture of the proposed T-type three-level inverter-fed IPMSM drive system. The carrier-based SVPWM strategy, switching logic, and neutral-point voltage balancing mechanism are described before their effectiveness is evaluated through PLECS simulations.

2.1. System Configuration

The system configuration of the proposed IPMSM drive system is shown in Figure 1. The system consists of a DC power source, a split DC-link formed by two series-connected capacitors, a T-type three-level inverter, an IPMSM. The DC link voltage is set to 350 V, and the upper and lower DC-link capacitors $C_U$ and $C_L$ are used to establish a neutral point for three-level voltage operation. The T-type inverter contains three identical phase legs. The three-phase inverter outputs are directly connected to the stator windings of the IPMSM, and the phase currents $i_{us}, i_{vs}$ and $i_{ws}$ are supplied to the motor. An encoder is employed to provide rotor position and speed information for feedback control in the DSP. In addition, an IPMSG was mechanically coupled to the motor shaft, and an electrical load was connected to the generator terminals to serve as the load torque.

Figure 1. System configuration of the IPMSM drive system.

2.2. Carrier-Based Three-Level SVPWM

Although three-level SVPWM offers superior performance, its implementation requires region identification and dwell-time calculation, resulting in considerable computational burden. Therefore, a simplified strategy based on two-level zero-sequence injection is adopted to convert the three-phase sinusoidal reference signals into saddle-shaped modulation waves equivalent to SVPWM:

$$V_{com}={\displaystyle \frac{1}{2}}\left[\max \left(V_a,V_b,V_c\right)+\mathrm{m}\mathrm{i}\mathrm{n}(V_a,V_b,V_c)\right]$$

(1)

$$V_{mod,i}=V_i-V_{com}$$

(2)

where $i\in \left\{a,b,c\right\}$ denotes the corresponding system phase, and $V_i$ represents the original sinusoidal voltage reference of that phase. By algebraically incorporating the offset voltage, the DC-link voltage utilization is improved without requiring complex geometric calculations. To ensure the modified signals $V_{mod,i}$ are correctly mapped onto the switching states of the T-type inverter, a polarity-based voltage-level assignment logic is adopted. This logic is established according to the physical arrangement of switches $S_1, S_2, S_3$ and $S_4$ defined in Figure 1. Furthermore, to prevent device damage, three fundamental forbidden states are strictly avoided: (1) simultaneous conduction of $S_1$ and $S_4$, (2) $S_1$ and $S_3$, and (3) $S_2$ and $S_4$. According to the polarity of the modulation wave $V_{mod,i}$, the switching operations are restricted to the corresponding voltage subintervals, and the commutation sequences are arranged to avoid these forbidden switching configurations.

During transitions between stable states, a protection sequence is applied in which any switch conflicting with the subsequent state is turned off before the next device is activated. This ensures that only safe intermediate configurations occur during the dead-time interval. The corresponding switching-state and gate-signal assignments are summarized in Table 1.

Table 1. Switching state mapping and operational logic.

State	Output	${\mathit{S}}_1$	${\mathit{S}}_2$	${\mathit{S}}_3$	${\mathit{S}}_4$	Modulation Region
P	$V_{dc}/2$	1	1	0	0	$V_{mod,i}\ge 0$
O	0	0	1	1	0	Transition State
N	$-V_{dc}/2$	0	0	1	1	$V_{mod,i}<0$

The switching sequence is determined by the phase-current polarity to prevent the forbidden states. As shown in Figure 2a, when the phase current is nonnegative, modulation is performed between States P and O. $S_3$ is turned off while $S_2$ remains on before $S_1$ is activated, whereas the reverse transition is completed by turning off $S_1$ before reactivating $S_3$. For negative phase current, the phase leg switches between States O and N, as shown in Figure 2b. $S_2$ is turned off before $S_4$ is activated while $S_3$ remains on, and the reverse transition is performed by turning off $S_4$ before $S_2$ is reactivated. This current-dependent commutation sequence maintains a safe neutral-point current path, avoids the forbidden switch combinations, and enables a stable five-level line-to-line voltage output.

Figure 2. Conduction paths of the T-type phase leg: (a) $i_{phase}\ge 0$; (b) $i_{phase}<0.$

3. Simulation Verification

Based on the system configuration and carrier-based three-level SVPWM presented in Section 2, the proposed IPMSM drive system is modeled in PLECS for simulation verification. The proposed modulation strategy is integrated with the FOC-based dual-loop control and neutral-point voltage balancing mechanism to form the complete control architecture. To enable a control-oriented assessment, ideal switching devices and a stable DC bus are assumed in the simulation model. Ideal switching devices and a stable DC bus are assumed in the simulation model. Accordingly, non-ideal effects, including switching delays, parasitic components, and digital implementation delays, are neglected in this section. This assumption allows the analysis to focus clearly on the fundamental feasibility of the control architecture, modulation scheme and operational logic for the T-type inverter, establishing a verified baseline for the subsequent hardware implementation.

The main system parameters of the IPMSM drive, including the DC-link voltage, rated current, and switching frequency, are listed in Table 2. In addition, the electrical and mechanical parameters used in the simulations were selected according to the specifications of the actual motor and are summarized in Table 3.

Table 2. Specifications of the IPMSM drive system.

Parameters	Value
Input Voltage	$350{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
Rated output voltage	220 ${\mathrm{V}}_{\mathrm{r}\mathrm{m}\mathrm{s}}$
Rated output current	5.77 ${\mathrm{A}}_{\mathrm{r}\mathrm{m}\mathrm{s}}$
Rated output power	2.2 $\mathrm{k}\mathrm{W}$
Switching frequency $f_s$	20$\mathrm{k}\mathrm{H}\mathrm{z}$ and 40$\mathrm{k}\mathrm{H}\mathrm{z}$
Upper DC capacitor $C_U$	3300$\mathsf{\mu }\mathrm{F}$
Lower DC capacitor $C_L$	3300$\mathsf{\mu }\mathrm{F}$

Table 3. Specifications and parameters of IPMSM.

Parameters	Value
Company	ADLEEPOWER (Taichung, Taiwan)
Model	MA-2200H
Voltage	220 $\mathrm{V}$
Rated speed	6000 $\mathrm{r}\mathrm{p}\mathrm{m}$
Torque	$3.5 \mathrm{N}·\mathrm{m}$
Rated power	2.2 $\mathrm{k}\mathrm{W}$
Number of poles	4
Inductance $L_q$	2.11 $\mathrm{m}\mathrm{H}$
Inductance${ L}_d$	1.14 $\mathrm{m}\mathrm{H}$
Back-EMF constant	14.91 $\mathrm{V}/\mathrm{k}\mathrm{r}\mathrm{p}\mathrm{m}$

3.1. Control Scheme of Simulation

The integrated control architecture of the T-type inverter system is shown in Figure 3, in which FOC is employed to achieve high-performance motor-drive operation. The mechanical speed and rotor position are measured using the encoder and processed by the speed control loop to generate the torque-producing current reference. This reference is subsequently applied to the inner current control loop, where the decoupled d-axis and q-axis currents are controlled to obtain the required voltage commands. To ensure stable operation, a neutral-point voltage balancing compensator is incorporated to regulate the split-capacitor voltages $V_{cu}$ and $V_{cl}$, while the total DC-link voltage $V_{dc}$ is supplied by a regulated DC source. The resulting voltage commands are then converted into gate signals using the simplified zero-sequence-injection-based PWM scheme together with the current-polarity detection logic. This multi-loop control structure provides accurate motor-drive control while maintaining balanced split DC-link capacitor voltages. The PI controller parameters adopted in the PLECS model are listed in Table 4.

Figure 3. The integrated control architecture for the T-type inverter system.

Table 4. PI controller parameters in PLECS.

	Speed Controller	d-Axis Controller	q-Axis Controller	NP Controller
$K_p$	100	50	50	15
$K_i$	10	1.5	1.5	0.1

3.2. Simulation Results

The simulation results of the proposed IPMSM drive system are shown in Figure 4. As illustrated in Figure 4a, the line-to-line voltage $V_{ab}$ exhibits five distinct voltage levels, confirming the proper operation of the proposed carrier-based three-level SVPWM strategy. Figure 4b confirms that the switching sequences are executed based on the logic mentioned in Section 2. Figure 4c shows the motor speed response from standstill to a command of 6000 rpm. The motor follows the ramp reference smoothly without evident overshoot or instability. The enlarged steady-state waveform in Figure 4d further shows that the actual speed closely tracks the reference at 6000 rpm with only a small tracking error. In addition, the robustness of the neutral-point voltage balancing compensator is evaluated under severely unbalanced initial conditions, with $V_{cu}$ and $V_{cl}$ initially set to 349 V and 1 V, respectively. As shown in Figure 4e, both capacitor voltages are rapidly regulated toward the balanced operating point and converge to approximately 175 V, corresponding to half of the total DC-link voltage. Furthermore, Figure 4f demonstrates that the proposed control strategy along with well-tuned PI controllers can effectively achieve stable dynamic responses during sudden loading and de-loading conditions at the rated speed of 6000 rpm.

Figure 4. Simulation results: (a) Line-to-line voltage $V_{ab}$ of the proposed SVPWM strategy; (b) single-phase gate signal of the T-type inverter; (c) speed response from standstill to 6000 rpm; (d) zoomed-in steady-state speed tracking at 6000 rpm; (e) transient response of neutral-point voltage balancing control; and (f) ${(i}_{qs}^{\ast },i_{qs})$ and ${(rpm}^{\ast },rpm)$ of the IPMSM drive under a step load change (10% load$\to$full load$\to$10% load, ${rpm}^{\ast }$ = 6000 rpm).

4. Double-Pulse Test and SiC Device Characterization

A double-pulse test (DPT) is employed to characterize the switching behavior of the SiC MOSFETs adopted in the T-type inverter under controlled voltage and current conditions.

As shown in Figure 5a, the DPT circuit consists of a regulated DC source, a half-bridge leg, and an inductive load. The first pulse establishes the required load current, and its falling edge is used to evaluate the turn-off characteristics. After a short freewheeling interval, the second pulse is applied to assess the turn-on behavior, as illustrated in Figure 5b.

Figure 5. Principle of the double-pulse test: (a) Circuit schematic; (b) typical operating waveforms.

4.1. Experimental Setup and Test Conditions

To accurately evaluate the dynamic switching characteristics of the selected SiC MOSFETs, this study developed a double-pulse test platform. The overall hardware configuration is shown in Figure 6. In terms of system architecture, the platform consists primarily of a digital signal generator responsible for outputting precise double-pulse timing, an auxiliary power supply providing a stable operating voltage for the isolated gate drive circuit, and a high-power DC power supply for establishing a high-voltage DC bus to simulate the actual operating voltage of the inverter. Together, these devices provide a complete dynamic test environment for the half-bridge power modules under test. The key specifications of this SiC MOSFET are summarized in Table 5, and the oscilloscope (Teledyne LeCroy, Chestnut Ridge, NY, USA), voltage probes (Cybertek, Shenzhen, China), and Rogowski current probe (Cybertek, Shenzhen, China) used in the DPT are listed in Table 6, together with their respective bandwidths.

Figure 6. Photograph of the complete double-pulse test platform.

Table 5. Key specifications of the selected SiC MOSFET.

Manufacturer	FastSiC (Hsinchu, Taiwan)
Model	FF07040M2T
${\mathit{V}}_{\mathit{D}\mathit{S}}$	750 V
Max  ${\mathit{I}}_{\mathit{D}}$	57 A
${\mathit{V}}_{\mathit{G}\mathit{S}\left(\mathit{t}\mathit{h}\right)}$	2.5 V
${\mathit{R}}_{\mathit{d}\mathit{s}\left(\mathit{o}\mathit{n}\right)}$	40 m$\mathsf{\Omega }$
${\mathit{C}}_{\mathit{i}\mathit{s}\mathit{s}}$	2002 pF
${\mathit{C}}_{\mathit{o}\mathit{s}\mathit{s}}$	97 pF

Table 6. Measurement equipment and bandwidths used in the DPT.

Equipment	Model	Bandwidth
Oscilloscope	HDO4104A	1 GHz
Differential probe	CB6150B	200 MHz
GaN/SiC probe	P2000A	700 MHz
Rogowski coils	CP9012S	30 MHz

To evaluate the effects of DC-link voltage and switching slew rate on the switching losses and transient electrical stresses of the SiC MOSFET, two sets of DPT conditions are considered. First, the gate resistance is fixed, while the load current is varied from 3 A to 10 A under DC-link voltages of 200 V and 400 V, as summarized in Table 7. Subsequently, the DC-link voltage is fixed at 200 V, and different gate resistances are selected to obtain three target slew rates for both the turn-on and turn-off transitions over a load-current range of 0–10 A. The corresponding turn-on and turn-off test conditions are listed in Table 8 and Table 9, respectively.

Table 7. Test conditions for evaluating the impact of DC-link voltage.

Test Voltage (V)	Test Current (A)
200	3~10
400	3~10

Table 8. Test conditions for evaluating the impact of turn-on switching slew rate.

Slew Rate at 10 A (V/ns)	${\mathit{R}}_{\mathit{g},\mathit{o}\mathit{n}}$ (Ω)	Test Voltage (V)	Test Current (A)
1	270	200	0~10
5	43	200	0~10
10	2	200	0~10

Table 9. Test conditions for evaluating the impact of turn-off switching slew rate.

Slew Rate at 10 A (V/ns)	${\mathit{R}}_{\mathit{g},\mathit{o}\mathit{f}\mathit{f}}$ (Ω)	Test Voltage (V)	Test Current (A)
5	22	200	0~10
10	4.48	200	0~10
20	1.43	200	0~10

4.2. Experimental Results

As shown in Figure 7a,b, the total switching energy increases with both the DC-link voltage and drain-source current. Compared with the 200 V condition, the switching energy measured at 400 V is consistently higher, and the difference becomes more pronounced as the current increases. Figure 7c,d further show that the switching energy decreases as the switching slew rate increases. At a drain-source current of 10 A, increasing the turn-on slew rate from 1 V/ns to 10 V/ns reduces the turn-on energy from approximately 300 μJ to below 50 μJ. Similarly, a turn-off slew rate of 20 V/ns yields lower turn-off energy than at 5 V/ns. Based on the measured loss trends and switching behavior, the gate resistance value of 10 Ω is selected for both $R_{g,on}$ and $R_{g,off}$ to achieve a suitable compromise between switching efficiency and operational stability.

Figure 7. Measured switching-energy characteristics of the SiC MOSFET under different DC-link voltages and switching slew rates: (a) Switching energies at 200 V; (b) switching energies at 400 V; (c) turn-on energy under different turn-on slew rates; and (d) turn-off energy under different turn-off slew rates.

5. DSP Firmware Implementation

To accommodate the modular hardware platform, the control firmware is developed in a progressive manner. The baseline FOC and SVPWM routines are first implemented and experimentally verified using the two-level inverter configuration. Based on this verified framework, the firmware is subsequently extended to the T-type three-level inverter by incorporating the proposed carrier-based three-level SVPWM, neutral-point voltage balancing, two-layer protection. This staged implementation enables both inverter configurations to operate on the same DSP platform and provides a consistent basis for the subsequent experimental comparison.

5.1. Firmware Architecture

The firmware control architecture of the two-level inverter-fed IPMSM drive system is shown in Figure 8. The FOC and SVPWM algorithms are integrated with the ADC, eQEP, and ePWM peripherals to achieve closed-loop motor-drive control. Based on this verified framework, the firmware is extended to the T-type three-level inverter by incorporating the proposed carrier-based three-level SVPWM and neutral-point voltage balancing control, as shown in Figure 9.

Figure 8. Firmware control architecture of the two-level inverter-fed IPMSM drive system.

Figure 9. Firmware control architecture of the T-type three-level inverter-fed IPMSM drive system.

5.2. PWM Protection Logic

In each T-type phase leg, four switches are driven by two complementary PWM pairs. The conventional dead-band submodules can prevent simultaneous conduction within each complementary pair, thereby avoiding the forbidden combinations of $S_1$–$S_3$ and $S_2$–$S_4$. However, the cross-pair combination of $S_1$ and $S_4$ cannot be directly protected by the standard dead-band function. Simultaneous conduction of these two switches creates a direct DC-link shoot-through path. Therefore, additional software- and hardware-based protection mechanisms are implemented to ensure safe commutation of the T-type inverter.

As the first protection layer, a software-based zero-crossing mechanism is implemented. As shown in Figure 10a, a hysteresis band is introduced around the zero-crossing point of the modulation signal. When the reference falls within this region, the phase leg is forced into State O, ensuring that the voltage-state transition follows P → O → N or N → O → P rather than directly switching between States P and N. As the second protection layer, a hardware interlock is implemented using the DSP Input X-BAR, Digital Compare, and ePWM Trip-Zone modules. As illustrated in Figure 10b, the $S_1$ and $S_4$ drive signals are continuously monitored. If simultaneous high-level signals are detected, the Trip-Zone module immediately disables the corresponding ePWM output without CPU intervention. The cycle-by-cycle protection mode allows normal switching to resume automatically after the abnormal condition is cleared.

Figure 10. Two-layer protection scheme for the T-type inverter: (a) Software-based zero-crossing protection of the modulation signal; (b) hardware interlock implemented using the DSP digital-comparator and ePWM trip-zone modules.

6. Experimental Results of the Proposed IPMSM Drive System

A 2.2 kW experimental platform is constructed to validate the proposed IPMSM drive system, as shown in Figure 11. The setup includes a DSP, a modular inverter, DC-link capacitors, solid-state circuit breakers, voltage and current sensors, an encoder, an IPMSM, and an IPMSG load machine. The inverter is implemented using separate half-bridge and auxiliary boards, allowing the same DSP and motor platform to be configured for both two-level and T-type inverter operation. The gate-drive parameters selected from the DPT results are adopted in the experimental inverter.

Figure 11. Photograph of the experimental setup for the T-type inverter-fed IPMSM drive system.

The measured line-to-line voltage $V_{ab}$ of the T-type inverter is shown in Figure 12. Five distinct voltage levels are observed, verifying the correct operation of the proposed carrier-based three-level SVPWM and voltage-level assignment logic. The motor-drive performance is further evaluated at the rated operating condition of 6000 rpm and 2.2 kW. As shown in Figure 13, both inverter configurations maintain stable motor speed and balanced three-phase currents under full-load operation.

Figure 12. Measured five-level line-to-line voltage $V_{ab}$ of the T-type inverter.

Figure 13. Measured steady-state waveforms at 6000 rpm and 2.2 kW under full-load operation: (a) Two-level inverter; (b) T-type inverter.

After stable operation is confirmed, the inverter efficiency and phase-current THD are compared under various load conditions at switching frequencies of 20 kHz and 40 kHz, as shown in Figure 14 and Figure 15, respectively. The T-type inverter generally achieves higher efficiency and lower current THD than the conventional two-level inverter at both switching frequencies. The efficiency improvement is mainly attributed to the reduced switching losses associated with smaller voltage transitions, while the lower THD results from the reduced output-voltage step of the three-level topology.

Figure 14. Measured performance comparison between the proposed T-type and conventional two-level inverters at 20 kHz: (a) Inverter efficiency; (b) phase-current THD.

Figure 15. Measured performance comparison between the proposed T-type and conventional two-level inverters at 40 kHz: (a) Inverter efficiency; (b) phase-current THD.

Specifically, under near full-load conditions at 20 kHz, the T-type inverter achieves 99.29% efficiency and 1.36% THD, outperforming the two-level baseline, which operates at 98.43% efficiency and 3.11% THD. At 40 kHz, its high-frequency advantage becomes more pronounced. The T-type topology achieves 98.86% efficiency compared to the two-level’s 97.84%, and it further suppresses the THD to 1.12% compared to the two-level’s 1.99%. These quantitative results explicitly demonstrate the proposed architecture’s ability to minimize switching losses and improve waveform quality.

7. Conclusions

This paper presents a 2.2 kW SiC-based T-type three-level inverter for high-efficiency IPMSM drive applications. A simplified carrier-based SVPWM strategy combined with active neutral-point voltage balancing is developed and verified through PLECS simulations. The switching characteristics of the adopted SiC MOSFETs are evaluated using a double-pulse test platform, while the control algorithms and protection functions are implemented on a TMS320F280049C DSP. Experimental validation is conducted at switching frequencies of 20 kHz and 40 kHz. The results confirm that the proposed T-type inverter achieves higher conversion efficiency and lower phase-current THD than the conventional two-level inverter under various load conditions. This improvement is attributed to the reduced switching voltage stress and smaller output-voltage steps of the three-level topology. Across all tested operating points, the inverter efficiency remains above 95%, while the phase-current THD is maintained below 4%. Specifically, under near full-load conditions, the T-type inverter achieves an outstanding peak efficiency of 99.29% at 20 kHz. Furthermore, at the higher switching frequency of 40 kHz, it significantly suppresses the THD to 1.12%. These results demonstrate the effectiveness and practical feasibility of the developed system for high-efficiency electric vehicle drive applications. Future investigations will focus on conducting comprehensive dynamic motor drive experiments, exploring thermomechanical considerations for high-density co-packaged inverter-motor integrations and extending the comparative analysis to other advanced multilevel architectures, such as the Active Neutral-Point-Clamped (ANPC) topology.