Search Results (42)

As semiconductor packaging technology evolves from two-dimensional to three-dimensional integration, the through-glass via (TGV) technique, as a core interconnect method in advanced packaging, is emerging as a strong candidate to replace through-silicon vias (TSVs) and plated through-holes (PTHs) in organic substrates. Glass substrates offer excellent electrical insulation, low dielectric loss, tunable thermal expansion coefficients, and the potential for large-scale panel-level manufacturing. However, issues related to TGV hole quality, metallization uniformity, and thermomechanical reliability remain key bottlenecks limiting their large-scale industrialization. This investigation provides a comparative review of non-laser and laser machining for TGVs to address the above problems. First, the technical background and core advantages of TGVs are outlined. Second, this study details non-laser processing methods, including sandblasting erosion, mechanical drilling, the photosensitive glass method, electrochemical discharge machining (ECDM), deep reactive ion etching (DRIE), and others. Third, laser processing methods, covering laser ablation drilling, laser-induced deep etching (LIDE), femtosecond laser-assisted wet etching and others, are given focus. Moreover, this study analyzes typical applications of TGVs in 3D/2.5D packaging, MEMS devices, optoelectronic integration, and others. In addition, the machining processes of non-laser and laser-based TGVs, such as mechanical machining, ECDM, and LIDE, are compared, and key process challenges, technical trade-offs, and reliability failure mechanisms are discussed. Finally, this review looks ahead to future trends, aiming to provide a systematic technical reference for researchers in the TGV field. Full article

The rapid advancement of high-performance computing has spurred growing demand for miniaturized, high-density, high-power, and highly reliable electronic packaging. Through-silicon via (TSV), as a pivotal technology enabling high-density integrated packaging, achieves vertical interconnection that reduces signal latency and power consumption while substantially improving system integration. However, inherent challenges persist due to coefficient of thermal expansion mismatches among heterogeneous materials in TSV and parasitic effects introduced by high-density TSV arrays, leading to critical concerns regarding thermomechanical reliability and signal integrity. This study focuses on TSV structures, investigating their thermomechanical reliability and electrical performance. First, the macro–micro model of 2.5D package structure was established to address cross-scale challenges based on Representative Volume Element (RVE) homogenization and sub-model technique. Then, an equivalent circuit model integrating transmission line network theory was developed and validated through full-wave electromagnetic simulations using S-parameter analysis to analyze signal transmission characteristics. Finally, by introducing an improved multi-objective grasshopper algorithm, the structural parameters of TSV are co-optimized using a genetic algorithm back propagation network (GA-BP) and an improved multi-objective grasshopper algorithm (IMOGOA) to enhance both thermomechanical reliability and electrical characteristics simultaneously. The proposed approach offers a practical and effective solution for improving the reliability and performance of high-density integrated packaging, providing valuable insights for future packaging design and optimization. Full article

Fueled by the push for “More than Moore”, three-dimensional integrated circuits (3D ICs) have become a backbone of next-generation electronics. Their complex architectures place unprecedented demands on etching technologies, which must now deliver atomic precision, stringent high-aspect-ratio (HAR) control, and virtually damage-free profiles. Meeting these challenges requires metrology capable of true 3D, quantitative analysis at the nanoscale. Atomic force microscopy (AFM) has proven essential in this regard, offering non-destructive, sub-nanometer characterization that other techniques cannot provide. This review systematically examines AFM’s pivotal role in advancing key etching processes for 3D ICs, including deep reactive ion etching of through-silicon vias (TSVs), atomic layer etching (ALE), and cryogenic plasma etching. We detail AFM’s unique contributions to quantifying sidewall roughness, verifying etch-per-cycle rates, and assessing surface damage. We also discuss how recent innovations, such as tilting-AFM, HAR probes, and automated inline systems, are overcoming traditional barriers in throughput and access to sidewalls and deep trenches. Looking forward, the integration of AFM with optical metrology, machine learning, and multi-scale modeling opens a path toward truly autonomous process control and optimization. As such, AFM stands as an indispensable tool for developing and refining the etching processes that underpin next-generation 3D semiconductor manufacturing. Full article

Three-dimensional integrated circuits (3D ICs) have emerged as a key technology to sustain scaling trends in the microelectronics industry. This advancement calls for a fundamental shift in how electrical interconnects are implemented, with through-silicon vias (TSVs) playing a pivotal role in enabling vertical connectivity between stacked chips. However, the metallization of TSVs traditionally involves elaborate and demanding processes, which can limit the speed and flexibility of prototyping and design modifications. In this paper, we investigate the use of Ultra-Precise Dispensing (UPD) technology of novel silver nanoparticle-based pastes as a simple and adaptable alternative to the metallization of TSVs process. The TSV filling process is outlined, followed by a detailed analysis of their morphology, filling quality, and electrical performance. We successfully achieve filled vias through a 280 μm thick silicon substrate with diameters down to 20 μm, resulting in an aspect ratio of up to 14:1, exhibiting favorable electrical properties. This work contributes to the achievement of dense, high-aspect ratio TSV fabrication using additive manufacturing, demonstrating a path towards reduced complexity of standard technology processes cycle, lower cost potential, and increased design flexibility. Full article

Finite element modeling (FEM) of hybrid bonding stacks for high-density 3D integration suffers from excessive computational load and prohibitive simulation time. To address this critical technical bottleneck, this paper proposes an analytical lumped-distributed equivalent circuit model based on multi-layer structures. The model incorporates both redistribution layer (RDL) parasitics and metal–insulator–semiconductor (MIS) depletion effects for comprehensive signal integrity analysis. Frequency-dependent RLGC electromagnetic parameters were extracted from through-silicon via (TSV) and RDL interconnects. These parameters were numerically calculated using MATLAB R2020a to construct the equivalent circuit model in ADS. The model was subsequently validated against COMSOL finite element simulations. The results demonstrated that the proposed methodology achieved maximum deviations below 5% for all S-parameters in double-layer structures. For 5-layer stacks, errors were controlled within 10% across the 0–40 GHz frequency range. Computation time was reduced from several minutes to seconds. The proposed equivalent circuit method significantly reduces computational time while maintaining accuracy, providing an efficient simulation methodology for signal integrity analysis and verification of hybrid bonding stack structures. Compared to existing single-layer models, this work extends the modeling approach to multi-layer hybrid bonding stacks while comprehensively accounting for both RDL parasitics and MIS depletion effects, addressing a critical gap in the current state of the art. Full article

In this study, the Monte Carlo (MC) method is employed to generate the diameter and relative positional distributions of carbon nanotubes (CNTs). Based on this, we develop a three-layer thermal model for a copper-carbon nanotube (Cu-CNT) through-silicon via (TSV). By integrating Gauss–Hermite quadrature with the Law of Large Numbers (LLN), an analytical expression for thermal conductivity is derived, enabling efficient and accurate estimation of the thermal conductivity of Cu-CNT-filled TSV. Contrary to expectations, the thermal conductivity of TSV does not increase significantly with CNT volume fraction, primarily due to the interfacial thermal resistance at Cu-CNT and CNT-CNT junctions. Through calibration against previously reported experimental data, the effective Cu-CNT interfacial thermal resistance is estimated to be on the order of 10⁻⁷ m²K/W. Comparison with previously reported effective thermal conductivity data of Cu-CNT composites shows that the model maintains an error below 2% when the CNT volume fraction is below 10%. The model is therefore most suitable for low CNT volume fractions, where the assumed spatial distribution and structural simplifications remain physically valid. Furthermore, this study investigates the influence of TSV length on thermal performance, predicts the variation in thermal conductivity of Cu-CNT composites under different volume fractions, and the extracted thermal conductivity values are further used as material inputs for device-level electro-thermal COMSOL 6.1 simulations. Full article

Electromagnetic compatibility (EMC) diagnostics for high-density through-silicon via (TSV)-based chips face significant challenges due to complex three-dimensional electromagnetic coupling and inefficient source reconstruction workflows. This paper proposes a universal contribution-driven dipole preprocessing technique tailored for dipole array-based source reconstruction methods, addressing the critical efficiency-accuracy trade-off inherent in traditional approaches. The core innovation is an influence factor-based evaluation-elimination mechanism that extracts effective dipole components aligned with the structural characteristics of TSV-based chips and multilayer printed circuit boards, while eliminating redundant dipoles independently of the downstream source reconstruction algorithm. Validation on a multilayer PCB (1 GHz) and a TSV-based chip (4 GHz) demonstrates that the technique maintains high reconstruction accuracy, with error increase limited to ≤0.2% for the simulated PCB and ≤0.05% for the physically measured TSV-based chip. Computational time is reduced by 28–61% for the PCB and 20–28% for the TSV chip compared to traditional source reconstruction without preprocessing. For TSV-based chips exhibiting complex electromagnetic behavior, the technique delivers consistent performance across different dipole configurations, providing a fast, robust, and universal EMC diagnostic tool for high-density electronic devices. Full article

The rapid growth of artificial intelligence (AI), data centers, and high-performance computing (HPC) has increased the demand for large bandwidth, high energy efficiency, and high-density optical interconnects. Co-packaged optics (CPO) technology offers a promising solution by integrating photonic integrated circuits (PICs) directly within or close to electronic integrated circuit (EIC) packages. This paper explores the evolution of CPO performance from various perspectives, including fan-out wafer level packaging (FOWLP), through-silicon via (TSV)-based packaging, through-glass via (TGV)-based packaging, femtosecond laser direct writing waveguides, ion-exchange glass waveguides, and optical coupling. Micro ring resonators (MRRs) are a high-density integration solution due to their compact size, excellent energy efficiency, and compatibility with CMOS processes. However, traditional thermal tuning methods face limitations such as high static power consumption and severe thermal crosstalk. To address these issues, non-volatile neuromorphic photonics has made breakthroughs using phase-change materials (PCMs). By combining the integrated storage and computing capabilities of photonic memory with the efficient optoelectronic interconnects of CPO, this deep integration is expected to work synergistically to overcome material, integration, and architectural challenges, driving the development of a new generation of computing hardware with high energy efficiency, low latency, and large bandwidth. Full article

Three-dimensional integrated circuit (3D IC) technology is an innovative approach in the semiconductor industry aimed at enhancing performance and reducing power consumption. However, thermal management issues arising from high-density stacking pose significant challenges. Carbon nanotubes (CNTs) have gained attention as a promising material for addressing the thermal management problems of through-silicon vias (TSVs) owing to their unique properties, such as high thermal conductivity, electrical conductivity, excellent mechanical strength, and low coefficient of thermal expansion (CTE). This paper reviews various applications and the latest research results on CNT-based TSVs. Furthermore, it proposes a novel TSV design using CNT–copper–tin composites to optimize the performance and assess the feasibility of CNT-based TSVs. Full article

High-Bandwidth Memory (HBM) enables the bandwidth required by modern AI and high-performance computing, yet its three dimensional stack traps heat and amplifies thermo mechanical stress. We first review how conventional solutions such as heat spreaders, microchannels, high density Through-Silicon Vias (TSVs), and Mass Reflow Molded Underfill (MR MUF) underfills lower but do not eliminate the internal thermal resistance that rises sharply beyond 12layer stacks. We then synthesize recent hybrid bonding studies, showing that an optimized Cu pad density, interface characteristic, and mechanical treatments can cut junction-to-junction thermal resistance by between 22.8% and 47%, raise vertical thermal conductivity by up to three times, and shrink the stack height by more than 15%. A meta-analysis identifies design thresholds such as at least 20% Cu coverage that balances heat flow, interfacial stress, and reliability. The review next traces the chain from Coefficient of Thermal Expansion (CTE) mismatch to Cu protrusion, delamination, and warpage and classifies mitigation strategies into (i) material selection including SiCN dielectrics, nano twinned Cu, and polymer composites, (ii) process technologies such as sub-200 °C plasma-activated bonding and Chemical Mechanical Polishing (CMP) anneal co-optimization, and (iii) the structural design, including staggered stack and filleted corners. Integrating these levers suppresses stress hotspots and extends fatigue life in more than 16layer stacks. Finally, we outline a research roadmap combining a multiscale simulation with high layer prototyping to co-optimize thermal, mechanical, and electrical metrics for next-generation 20-layer HBM. Full article

In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer formation, and double-sided Cu electroplating. This method enhances the TSV stability by eliminating Cu contamination issues during chemical–mechanical polishing (CMP), which are a common challenge in traditional blind via fabrication processes. Additionally, the liner and barrier layer/seed layer achieve a high step coverage exceeding 80%, ensuring excellent conformality and structural integrity. For electroplating, a multi-stage bi-directional electroplating technique is introduced to enable void-free Cu filling in TSVs. The fabricated TSVs exhibit an ultra-low leakage current of 135 fA at 20 V, demonstrating their potential for advancing 3D integration technologies in heterogeneous integration. Full article

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs. Full article

With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore’s Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps’ reliability, through-silicon vias’ (TSVs) and redistribution layers’ (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing. Full article

As semiconductor packaging technologies face limitations, through-silicon via (TSV) technology has emerged as a key solution to extending Moore’s law by achieving high-density, high-performance microelectronics. TSV technology enables enhanced wiring density, signal speed, and power efficiency, and offers significant advantages over traditional wire-bonding techniques. However, achieving fine-pitch and high-density interconnects remains a challenge. Solder flip-chip microbumps have demonstrated their potential to improve interconnect reliability and performance. However, the environmental impact of lead-based solders necessitates a shift to lead-free alternatives. This review highlights the transition from Sn-Pb solders to lead-free options, such as Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Zn, and Bi- or In-based alloys, driven by regulatory and environmental considerations. Although lead-free solders address environmental concerns, their higher melting points pose challenges such as thermal stress and chip warping, which affect device reliability. To overcome these challenges, the development of low-melting-point solder alloys has gained momentum. This study examines advancements in low-temperature solder technologies and evaluates their potential for enhancing device reliability by mitigating thermal stress and ensuring long-term stability. Full article

This study introduces a manufacturing process based on industrial MEMS technology, enabling the production of diverse sensor designs customized for a wide range of absolute pressure measurements. Using monocrystalline silicon as the structural material minimizes thermal stresses and eliminates temperature-dependent semiconductor effects, as silicon functions solely as a mechanical material. Integrating a eutectic bonding process in the sensor fabrication allows for a reliable operation at temperatures up to 350 °C. The capacitive sensor electrodes are enclosed within a silicon-based Faraday cage, ensuring effective shielding against external electrostatic interference. An innovative Through-Silicon Via (TSV) design, sealed using gold–gold (Au-Au) diffusion and gold–silicon (Au-Si) eutectic bonding, further enhances the mechanical and thermal stability of the sensors, even under high-temperature conditions. The unfilled TSV structure mitigates mechanical stress from thermal expansion. The sensors exhibited excellent performance, achieving a linearity of 99.994%, a thermal drift of −0.0164% FS (full scale)/K at full load and 350 °C, and a high sensitivity of 34 fF/kPa. These results highlight the potential of these sensors for high-performance applications across various demanding environments. Full article