High-Reliability Semiconductor Devices and Integrated Circuits, 4th Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 10 August 2026 | Viewed by 2152

Special Issue Editors


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Guest Editor
Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, The No. 5 Electronics Research Institute of the Ministry of Industry and Information Technology, Guangzhou 510610, China
Interests: failure mechanism and model of key devices; prognostics and health management (PHM) of power conversion system (PCS); PHM of system on chip (SoC)
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Guest Editor
School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: integrated circuits design; simulation and evaluation method of radiation effects in aerospace integrated circuits
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In this Special Issue on “High-Reliability Semiconductor Devices and Integrated Circuits, 4th Edition”, we focus on the simulation, modeling, design, and optimization of high-reliability devices and integrated circuits for automobiles, avionics, and aerospace. High-reliability devices and integrated circuits are intensely studied because they are widely used in traditional aerospace electronic systems, avionics, automobiles, etc. In recent years, in addition to the development of traditional highly reliable devices and circuits, new technologies such as intelligent analysis, optimization, and manufacturing based on artificial intelligence and other novel technologies have brought vitality to the field of high-reliability devices and circuits.

The objective of this Special Issue is to collect research works focused on mathematical models, high-efficiency/-precision numerical solution methods, and intelligent design and optimization methods for high-reliability materials and devices and integrated circuits. We welcome novel works reporting on high-reliability devices and circuits and their applications to discuss the most recent breakthroughs and the potential impacts in related research fields. The specific topics of interest include, but are not limited to, the following:

  • Novel design methods for high-reliability devices and integrated circuits;
  • Novel optimization technologies for high-reliability devices and integrated circuits;
  • Advanced device structures or materials for high-reliability design;
  • Reliability analyses of special environments, such as those with a strong magnetic field, radiation environment, etc.;
  • Applications of novel technology, such as AI, in high-reliability design and analysis;
  • Novel simulation technologies for functional safety.

Dr. Yiqiang Chen
Prof. Dr. Yi Liu
Dr. Changqing Xu
Guest Editors

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Keywords

  • high reliability
  • semiconductor devices
  • integrated circuits
  • strong magnetic field
  • radiation environment
  • intelligent design

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Published Papers (3 papers)

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26 pages, 6927 KB  
Article
Multi-Objective Optimization for Through-Silicon via Structure Considering Thermomechanical Reliability and Electrical Performance
by Siyi Chen, Wanlu Hu, Song Xue, Qiongfang Zhang, Jinyang Mu, Shaoyi Liu, Wenzhi Wu, Dongchao Diwu and Congsi Wang
Micromachines 2026, 17(5), 601; https://doi.org/10.3390/mi17050601 - 14 May 2026
Viewed by 176
Abstract
The rapid advancement of high-performance computing has spurred growing demand for miniaturized, high-density, high-power, and highly reliable electronic packaging. Through-silicon via (TSV), as a pivotal technology enabling high-density integrated packaging, achieves vertical interconnection that reduces signal latency and power consumption while substantially improving [...] Read more.
The rapid advancement of high-performance computing has spurred growing demand for miniaturized, high-density, high-power, and highly reliable electronic packaging. Through-silicon via (TSV), as a pivotal technology enabling high-density integrated packaging, achieves vertical interconnection that reduces signal latency and power consumption while substantially improving system integration. However, inherent challenges persist due to coefficient of thermal expansion mismatches among heterogeneous materials in TSV and parasitic effects introduced by high-density TSV arrays, leading to critical concerns regarding thermomechanical reliability and signal integrity. This study focuses on TSV structures, investigating their thermomechanical reliability and electrical performance. First, the macro–micro model of 2.5D package structure was established to address cross-scale challenges based on Representative Volume Element (RVE) homogenization and sub-model technique. Then, an equivalent circuit model integrating transmission line network theory was developed and validated through full-wave electromagnetic simulations using S-parameter analysis to analyze signal transmission characteristics. Finally, by introducing an improved multi-objective grasshopper algorithm, the structural parameters of TSV are co-optimized using a genetic algorithm back propagation network (GA-BP) and an improved multi-objective grasshopper algorithm (IMOGOA) to enhance both thermomechanical reliability and electrical characteristics simultaneously. The proposed approach offers a practical and effective solution for improving the reliability and performance of high-density integrated packaging, providing valuable insights for future packaging design and optimization. Full article
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12 pages, 6028 KB  
Article
A Universal Deep Learning Model for Predicting Detection Performance and Single-Event Effects of SPAD Devices
by Yilei Chen, Jin Huang, Yuxiang Zeng, Yi Jiang, Shulong Wang, Shupeng Chen and Hongxia Liu
Micromachines 2026, 17(4), 452; https://doi.org/10.3390/mi17040452 - 7 Apr 2026
Viewed by 1176
Abstract
Single-event effects (SEEs) present a significant challenge to the radiation reliability of integrated circuits. Conventional SEE analysis methods for single-photon avalanche diode (SPAD) devices primarily rely on Sentaurus Technology Computer-Aided Design (TCAD) numerical simulation, which is computationally intensive and time-consuming. In this study, [...] Read more.
Single-event effects (SEEs) present a significant challenge to the radiation reliability of integrated circuits. Conventional SEE analysis methods for single-photon avalanche diode (SPAD) devices primarily rely on Sentaurus Technology Computer-Aided Design (TCAD) numerical simulation, which is computationally intensive and time-consuming. In this study, we propose a generalized deep learning (DL) model, using a silicon-based SPAD device with a double-junction double-buried-layer (DJDB) structure fabricated in 180 nm CMOS process as the research subject. By incorporating key parameters that influence SEEs as model inputs, the proposed approach enables rapid prediction of critical parameter metrics, including transient current peaks and dark count rates. Experimental results show that the DL model achieves a prediction accuracy of 97.32% for transient current peaks and 99.87% for dark count rates, demonstrating extremely high prediction precision. To further validate the generalization capability of the proposed network, the model is applied to predict the detection performance of the DJDB-SPAD device. The prediction accuracies for four key performance parameters all exceed 97.5%, further confirming the accuracy and robustness of the developed model. Meanwhile, compared with the conventional Sentaurus TCAD simulation method, the proposed method achieves a 336-fold improvement in computational efficiency. Overall, this method realizes the dual advantages of high precision and high efficiency, which provides an efficient and accurate technical solution for the rapid characteristic analysis and reliability evaluation of SPAD devices under single-event effects (SEEs). Full article
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14 pages, 2146 KB  
Article
SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction
by Tianwen Li, Jianbing Tian and Jingli Qi
Micromachines 2026, 17(3), 342; https://doi.org/10.3390/mi17030342 - 11 Mar 2026
Viewed by 447
Abstract
This paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs) in radiation-prone environments. By leveraging extended Hamming coding and [...] Read more.
This paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs) in radiation-prone environments. By leveraging extended Hamming coding and dynamic circuits, the design achieves a 29.1% RW speed improvement, reduces SEU cross-section by one order of magnitude, and incurs a 29.8% area overhead and a 95.2% dynamic power increase of the ECC module, leading to an overall chip area increase of ~14.2% compared to static logic-based RH SEC-DED SRAM. Radiation experiments validate superior tolerance across a LET range of 1.63–21.8 MeV·cm2/mg, demonstrating nearly doubled SEU resilience compared to conventional SEC-DED-based designs. This work balances error correction capabilities with system efficiency, making it suitable for high-reliability applications in space electronics and advanced processors. Full article
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