Modeling Method for the Equivalent Circuit of Hybrid Bonding Stacks

Abstract

Finite element modeling (FEM) of hybrid bonding stacks for high-density 3D integration suffers from excessive computational load and prohibitive simulation time. To address this critical technical bottleneck, this paper proposes an analytical lumped-distributed equivalent circuit model based on multi-layer structures. The model incorporates both redistribution layer (RDL) parasitics and metal–insulator–semiconductor (MIS) depletion effects for comprehensive signal integrity analysis. Frequency-dependent RLGC electromagnetic parameters were extracted from through-silicon via (TSV) and RDL interconnects. These parameters were numerically calculated using MATLAB R2020a to construct the equivalent circuit model in ADS. The model was subsequently validated against COMSOL finite element simulations. The results demonstrated that the proposed methodology achieved maximum deviations below 5% for all S-parameters in double-layer structures. For 5-layer stacks, errors were controlled within 10% across the 0–40 GHz frequency range. Computation time was reduced from several minutes to seconds. The proposed equivalent circuit method significantly reduces computational time while maintaining accuracy, providing an efficient simulation methodology for signal integrity analysis and verification of hybrid bonding stack structures. Compared to existing single-layer models, this work extends the modeling approach to multi-layer hybrid bonding stacks while comprehensively accounting for both RDL parasitics and MIS depletion effects, addressing a critical gap in the current state of the art.

1. Introduction

Hybrid bonding has emerged as a key enabling technology for high-density 3D integration [1], distinguished by its submicrometer interconnect pitch, high-density Cu–Cu interconnect capabilities, and low parasitic effects. This technique utilizes van der Waals forces generated from smooth surfaces to enable permanent bumpless bonding under low-temperature and low-pressure conditions, and has been widely adopted in chip stacking applications.

However, as the stack layer count increases, signal integrity analysis of high-layer structures becomes particularly critical [2]. Simultaneously, energy-efficient and low-power 3D system design has emerged as a crucial requirement for modern high-density integration technologies [3]. Consequently, developing accurate yet computationally efficient modeling methodologies is essential to address both signal integrity and power optimization challenges. Full-wave FEM theoretically enables accurate characterization of stacked structures. The requirement for ultra-fine mesh discretization results in exponentially increasing computational demands with frequency and structural complexity. This produces prohibitive simulation times that are unsuitable for engineering applications [4]. In contrast, equivalent circuit models offer significant advantages in computational efficiency, modeling flexibility, and scalability. Specifically, RLGC parameter-based equivalent circuit modeling maintains sufficient accuracy while substantially reducing simulation time, thereby providing an ideal solution for signal integrity analysis.

Existing models primarily address single-layer configurations. Kim [5] established a benchmark for ground-signal (GS) TSV, yet neglected crosstalk analysis. Li [6] extended this to ground–signal–signal–ground (GSSG) structures incorporating RDL but omitted depletion effects. Yang [7] subsequently incorporated MIS depletion capacitance; however, all aforementioned approaches remain confined to single-layer stacks. Tsai [8] analyzed micro-bump structures, yet failed to characterize inter-layer coupling. More recently, Huang [9] proposed a single-layer hybrid bonding model that likewise overlooks multi-layer scalability, RDL parasitics, and MIS depletion effects.

To address these limitations in multi-layer hybrid bonding stack analysis, this study establishes an equivalent circuit model that simultaneously accounts for RDL parasitics and MIS structure effects. Based on GSSG configuration, the model extracts RLGC parameters for both TSVs and RDL to construct a lumped-distributed equivalent circuit applicable to 2 to 5-layer stacks. The accuracy was first validated using a double-layer structure and subsequently extended to 3 to 5-layer structures to demonstrate scalability and generalizability, thereby providing an efficient simulation methodology for signal integrity analysis of high-frequency 3D integrated devices. The main contributions of this work include: (1) extension of hybrid bonding equivalent circuit modeling from single-layer to multi-layer stack structures; (2) comprehensive integration of both RDL parasitics and MIS depletion effects in a unified modeling framework; and (3) validation of model accuracy and scalability across 2 to 5-layer configurations with computation time reduced from minutes to seconds.

The paper is organized as follows: Section 2 describes the finite element model and equivalent circuit model creation, including RLGC parameter extraction. Section 3 presents the simulation results and validation for 2-layer to 5-layer structures. Section 4 concludes the paper and discusses future work.

2. Model Creation

2.1. Finite Element Model

A basic two-layer hybrid bonding stack model was constructed in COMSOL Multiphysics 6.2. As shown in Figure 1, a Cu–Cu interconnect, 1 µm in height, was employed at the bonding interface [10]. The detailed model and material parameters are listed in

Table 1. Model parameters for hybrid bonding.

Symbol	Description	Value (µm)
HTSV	Height of TSV	30
HSi	Height of silicon substrate	28
Hpad	Height of copper interconnect	0.5
HIMD	Height of IMD layer	1
HRDL	Height of RDL	2
Lpad	Length of copper interconnect	10
P	Pitch of TSV	20
DTSV	Diameter of TSV	8
Tox	Thickness of silicon dioxide	0.3
Hox	Height of bonding layer SiO2	1
LRDL	Length of RDL	25
WRDL	Width of RDL	8
PRDL	Pitch of RDL	20

and

Table 2. Material parameters for hybrid bonding.

Material	Conductivity (S/m)	Relative Permittivity
Cu	5.998 × 107	1
SiO2	0	3.9
Si	10	11.7

. The silicon substrate conductivity of 10 S/m corresponds to a p-type doping concentration of 10¹⁶ cm⁻³, representing a standard moderately doped silicon substrate. Lumped ports with uniform distribution are employed for excitation, with a port impedance of 50 Ω and perfect electric conductor boundary conditions applied, and the analysis is performed in the frequency domain over the range of 0.1–40 GHz.

2.2. Equivalent Circuit Model

Equivalent circuit models for the TSV and RDL are illustrated in Figure 2. For the TSV in hybrid bonding structures, the filling layer is excluded from the equivalent circuit model.

The resistance comprises both DC and AC components; the resistance is expressed as follows:

$$R=\sqrt{R_{dc}^2+R_{ac}^2}$$

(1)

the R denotes the total equivalent resistance, comprising R_dc and R_ac components.

The R_ac component exhibits frequency dependence due to the skin effect:

$$\delta ={\displaystyle \frac{1}{\sqrt{\pi {\mu }_0\mu f\sigma }}}$$

(2)

among them, δ is the skin depth, μ₀ is the permeability of free space, μ_r is the relative permeability of the conductor, f denotes the operating frequency, and σ is the electrical conductivity.

The TSV DC and AC resistances are given by:

$$R_{dc,TSV}={\rho }_{TSV}\times {\displaystyle \frac{H_{TSV}}{\pi {\left(D_{TSV}/2\right)}^2}}$$

(3)

$$R_{ac,TSV}={\displaystyle \frac{{\rho }_{TSV}{H}_{TSV}}{\pi D_{TSV}{\delta }_{TSV}}}$$

(4)

where ρ_TSV, H_TSV, D_TSV, and δ_TSV denote the TSV material resistivity, height, diameter, and skin depth.

The RDL DC and AC resistances are expressed as follows:

$$R_{dc,RDL}={\rho }_{RDL}{\displaystyle \frac{L_{RDL}}{W_{RDL}{H}_{RDL}}}$$

(5)

$$R_{\mathrm{ac},RDL}={\displaystyle \frac{{\rho }_{RDL}}{W_{RDL}{\delta }_{RDL}}}$$

(6)

where ρ_RDL, L_RDL, W_RDL, H_RDL, and δ_RDL denote the RDL material resistivity, length, width, height, and skin depth.

TSV inductance comprises both mutual and self-inductance components [11,12], expressed as:

$$L_{TSV}={\displaystyle \frac{H_{TSV}}{2}}{L}_{TSV,ex}+L_{TSV,in}$$

(7)

$$L_{TSV,ex}={\displaystyle \frac{{\mu }_0{\mu }_{TSV}}{\pi }}\ln \left({\displaystyle \frac{P}{D_{TSV}}}+\sqrt{{\left({\displaystyle \frac{P}{D_{TSV}}}\right)}^2-1}\right)$$

(8)

$$L_{TSV,in}={\displaystyle \frac{R_{ac,TSV}}{2\pi f}}$$

(9)

where L_TSV denotes the TSV total equivalent inductance, L_TSV,ex denotes the TSV mutual inductance, L_TSV,in denotes the TSV self-inductance, and P represents the pitch between the TSVs.

RDL inductance is extracted using the loop inductance model of a two-wire transmission line, given by:

$$L_{RDL}=L_{RDL,ex}+L_{RDL,in}$$

(10)

$$L_{RDL,ex}={\displaystyle \frac{{\mu }_0{\mu }_{RDL}}{2\pi }}\left[\ln \left({\displaystyle \frac{2L_{RDL}}{H_{RDL}}}\right)-{\displaystyle \frac{3}{4}}\right]$$

(11)

$$L_{RDL,in}={\displaystyle \frac{{\mu }_0{\mu }_{RDL}}{2\pi }}\left[\ln \left({\displaystyle \frac{2L_{RDL}}{P_{RDL}}}\right)-1\right]$$

(12)

where L_RDL denotes the RDL total equivalent inductance, L_RDL,ex denotes the RDL mutual inductance, L_TSV,in denotes the RDL self-inductance, and P_RDL represents the pitch between the RDLs.

The MIS structure necessitates depletion capacitance to capture interfacial parasitics at the silicon substrate, with depletion width and depletion capacitance [13] expressed as:

$$T_{dep}=\sqrt{{\displaystyle \frac{4{\epsilon }_{si}kT}{q^2{N}_a}}\ln {\displaystyle \frac{N_a}{n_i}}}$$

(13)

$$C_{dep}={\displaystyle \frac{2\pi {\epsilon }_0{\epsilon }_{ox}{H}_{ox}}{\ln \frac{D_{TSV}/2+T_{dep}}{D_{TSV}/2}}}$$

(14)

where k is the Boltzmann constant (1.38 × 10⁻²³ J/K), the reference temperature T is set to 300 K, q is the elementary charge (1.602 × 10⁻¹⁹ C), N_a is the acceptor doping concentration (10¹⁶ cm⁻³), n_i is the intrinsic carrier concentration (1.5 × 10¹⁰ cm⁻³), and H_ox represents the oxide thickness.

The silicon substrate capacitance is calculated as follows:

$$C_{si}={\displaystyle \frac{\pi {\epsilon }_0{\epsilon }_{si}{H}_{Si}}{\ln \left(\frac{P}{D_{TSV}+2T_{ox}}+\sqrt{{\left(\frac{P}{D_{TSV}+2T_{ox}}\right)}^2-1}\right)}}$$

(15)

where H_Si denotes the height of the silicon substrate, and P represents the pitch between TSV.

As the IMD layer comprises SiO₂ in the hybrid bonding structure, the inter-layer capacitance is expressed as:

$$C_{si{o}_2}={\displaystyle \frac{\pi {\epsilon }_0{\epsilon }_{IMD}{H}_{IMD}}{\ln \left(\frac{P}{D_{TSV}}+\sqrt{{\left(\frac{P}{D_{TSV}}\right)}^2-1}\right)}}$$

(16)

where H_IMD denotes the height of IMD, and P represents the pitch between TSV.

The RDL capacitance [14,15], including fringe field contributions from both the IMD layer and air, was modeled using the parallel stripline formulation:

$$C_{RDL}={\epsilon }_0\left[{\epsilon }_{air}{\displaystyle \frac{K^{\prime }(k_0)}{K(k_0)}}+{\epsilon }_{IMD}{\displaystyle \frac{K^{\prime }(k_1)}{K(k_1)}}\right]$$

(17)

$$k_0=\sqrt{1-{\left({\displaystyle \frac{W_{RDL}}{S_{RDL}}}\right)}^2}$$

(18)

$$k_1=\sqrt{1-{\left({\displaystyle \frac{\sinh \left(\frac{\pi W_{RDL}}{2H_{IMD}}\right)}{\sinh \left(\frac{\pi S_{RDL}}{2H_{IMD}}\right)}}\right)}^2}$$

(19)

in these equations, K denotes the complete elliptic integral of the first kind, K’(k₀) represents the derivative of K with respect to k₀, S_RDL is the cross-sectional area of the RDL, and H_SiO2 is the height of the IMD layer.

As no MIS structure exists between the RDL and the silicon substrate, only the parasitic capacitance between the RDL layer and the substrate needs to be considered. The conformal mapping method was employed to determine this capacitance:

$$C_{RDL \mathrm{to} Sub}={\epsilon }_0{\epsilon }_{IMD}{\displaystyle \frac{W_{RDL}}{H_{IMD}}}+{\epsilon }_0{\epsilon }_{IMD}{\displaystyle \frac{K(k_{[VP]})}{K^{\prime }(k_{[VP]})}}$$

(20)

$$k_{[VP]}=\sqrt{1-{\left({\displaystyle \frac{H_{IMD}}{H_{IMD}+H_{RDL}}}\right)}^2}$$

(21)

where k_[VP] is the modulus of the complete elliptic integral of the first kind K.

As signals propagate along the RDL, electromagnetic fields penetrate the silicon substrate; consequently, the associated parasitic capacitance and conductance must be considered. The parasitic capacitance and conductance resulting from RDL penetration into silicon are expressed as:

$$C_{RDL \mathrm{to} Si}={\epsilon }_0{\epsilon }_{eff}{\displaystyle \frac{H_{RDL}}{H_{eff}}}$$

(22)

$$G_{RDL \mathrm{to} Si}={\delta }_{eff}{\displaystyle \frac{H_{RDL}}{H_{eff}}}$$

(23)

$${\epsilon }_{eff}={\displaystyle \frac{{\epsilon }_{si}+1}{2}}+{\displaystyle \frac{{\epsilon }_{si}-1}{2\sqrt{1+10\frac{H_{IMD}+H_{Si}}{W_{RDL}}}}}$$

(24)

$${\delta }_{eff}={\displaystyle \frac{{\delta }_{Si}}{2}}+{\displaystyle \frac{{\delta }_{Si}}{2\sqrt{1+10\frac{H_{IMD}+H_{Si}}{D_{RDL}}}}}$$

(25)

$$H_{eff}={\displaystyle \frac{H_{IMD}}{2\pi }}\ln \left({\displaystyle \frac{8(H_{IMD}+H_{Si})}{H_{RDL}}}+{\displaystyle \frac{H_{RDL}}{4(H_{IMD}+H_{Si})}}\right)$$

(26)

where ε_eff is the effective permittivity calculated by Equation (24), δ_eff is the effective loss tangent by Equation (25), and H_eff is the effective dielectric thickness defined in Equation (26).

The parasitic conductance of the silicon substrate is expressed as:

$$G_{si}=C_{si}{\displaystyle \frac{{\sigma }_{si}}{{\epsilon }_0{\epsilon }_{si}}}$$

(27)

where C_si is the equivalent capacitance of silicon and σ_si is the conductivity of silicon.

The extracted RLGC parameters, calculated using MATLAB based on the aforementioned formulas, together with the geometric dimensions and material properties, are summarized in

Table 3. MATLAB calculation results.

Symbol	Description	Value
RTSV	TSV equivalent resistance	10.411 mΩ
RRDL	RDL equivalent resistance	1.681 mΩ
Rpad	Equivalent resistance at bonding layer	0.227 mΩ
LTSV	TSV equivalent inductance	14.274 pH
LRDL	RDL equivalent inductance	1.449 pH
Lpad	Equivalent inductance at bonding layer	0.657 pH
Cox	Equivalent capacitance of bonding layer	27.225 fF
Cpad	Equivalent capacitance between interface and silicon	2.712 fF
Cdep	Depletion layer capacitance	114.626 fF
CSi	Silicon equivalent capacitance	0.186 fF
CSiO2	IMD layer equivalent capacitance	2.712 fF
CRDL	RDL equivalent capacitance	0.035 fF
CRDL to Si	Equivalent capacitance penetrating into silicon	0.343 fF
CRDL to Sub	Equivalent capacitance between RDL and silicon	0.243 fF
GSi	Silicon equivalent conductance	17.952 μS
GRDL to Si	Equivalent conductance penetrating into silicon	7.143 μS

.

For the two-layer hybrid bonding stack, a Cu–Cu interconnect structure was employed at the bonding interface, where the equivalent circuit was implemented as a series connection of upper and lower TSV in Figure 3a. The corresponding circuit model was subsequently constructed in ADS, as presented in Figure 3b.

3. Results

3.1. Two-Layer Stacking

Figure 4 presents the comparison between the equivalent circuit and FEM simulation results. The comparison focuses on return loss (S₁₁), insertion loss (S₂₁), near-end crosstalk (S₃₁), and far-end crosstalk (S₄₁). FEM results serve as the benchmark. The equivalent circuit exhibits relative errors of 4.6%, 2.8%, 3.8%, and 4.3%. These results demonstrate that the proposed method maintains relative errors below 5% within 40 GHz utilizing the extracted RLGC parameters.

3.2. 3 to 5-Layer Stacking

To validate model scalability, the layer count was extended to five layers, with results shown in Figure 5. The relative errors for all S-parameters increase with the layer count. Specifically, the relative errors for S₁₁ in 3, 4, and 5-layer structures are 6.3%, 8.7%, and 9.2%, respectively. The maximum error for S₂₁ occurs at 40 GHz, with error rates of 5.4%, 6.2%, and 6.9% for the 3, 4, and 5-layer configurations, respectively. The maximum error rates for S₃₁ are 3.6%, 4.2%, and 4.8%, while those for S₄₁ are 6.5%, 7.6%, and 8.8%. Notably, the equivalent circuit model exhibits the highest prediction accuracy for S₃₁ and the largest deviation for S₁₁.

It should be noted that the current validation relies exclusively on FEM simulation results. While FEM provides a well-established benchmark for electromagnetic characterization in interconnect modeling, experimental validation with measured S-parameter data remains essential to further confirm the practical credibility of the proposed model under real-world fabrication and operating conditions.

3.3. Simulation Time

Figure 6 compares the computational time between FEM and the equivalent circuit approach for different layer counts. The results revealed that the FEM solution time increased substantially with the number of stack layers. In contrast, the equivalent circuit method reduces computation time from several minutes to seconds while maintaining engineering accuracy.

4. Conclusions

Electromagnetic parameters of TSVs and RDLs are extracted from hybrid bonding structures. Based on these parameters, a lumped-distributed equivalent circuit model is constructed. This model incorporates parasitic effects from both RDL layers and MIS structures. The model achieves simulation errors within 5% for S-parameters of double-layer stacks over the 0–40 GHz frequency range. For 5-layer configurations, the minimum error is observed for S₃₁ (4.8%), while the maximum error occurs for S₁₁ (9.2%), with all S-parameter errors increasing with layer count. Compared with existing models, this study extends hybrid bonding models to multi-layer stack structures. It comprehensively accounts for parasitic effects from RDL layers and MIS structures. This addresses a gap in equivalent circuit modeling for hybrid bonding stacks. The proposed model reduces computation time from several minutes to mere seconds compared to 3D full-wave simulations, significantly enhancing simulation efficiency.

The proposed model does not account for inter-layer transmission coupling effects. Furthermore, the truncation of MATLAB calculation results to three decimal places introduces numerical inaccuracies. These inaccuracies affect the extracted RLGC parameters and lead to deviations in the equivalent circuit simulation results. Future work will focus on the following aspects: (1) incorporating inter-layer coupling effects to enhance modeling accuracy for multi-layer stack configurations; (2) extending the model validation to frequencies above 100 GHz; and (3) experimental validation using measured data to quantify the discrepancies between finite element simulation and equivalent circuit modeling results, thereby addressing the current limitation of relying solely on simulation data.