Advanced Etching Technologies for Three-Dimensional Integrated Chips

Dear Colleagues,

Three-dimensional (3D) integrated chips represent a critical pathway toward overcoming the scaling limits of conventional planar integrated circuits. By enabling vertical integration and heterogeneous stacking, 3D architectures offer significant advantages in performance, power efficiency, and functional density. Advanced etching technologies are essential for fabricating 3D chips, as they determine the quality, reliability, and scalability of high-aspect-ratio structures and complex three-dimensional features.

The continuous evolution of through-silicon vias (TSVs), monolithic 3D integration, and heterogeneous integration places increasingly stringent demands on etching processes, including precise profile control, high selectivity, low damage, and compatibility with backend-of-line (BEOL) processes. Meanwhile, emerging approaches such as atomic layer etching (ALE), cryogenic plasma etching, and data-driven process optimization are creating new opportunities for next-generation 3D chip manufacturing.

In this Special Issue, we aim to collect original research and review articles that report recent advances in etching technologies for 3D integrated chips, covering process development, understanding of mechanisms, modeling, diagnostics, and integration challenges. Contributions addressing both fundamental studies and industrially relevant solutions are strongly encouraged.

Dr. Bo Liu
Dr. Danny Reuter
Guest Editors

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