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Micromachines
Special Issues
Advanced Interconnect and Packaging, 3rd Edition
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Advanced Interconnect and Packaging, 3rd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: 31 October 2025 | Viewed by 4477

Special Issue Editors

Prof. Dr. Wensheng Zhao

E-Mail Website
Guest Editor
School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
Interests: interconnect; packaging; TSV; 3-D IC
Special Issues, Collections and Topics in MDPI journals
Dr. Dawei Wang

E-Mail Website
Guest Editor
School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
Interests: advanced packaging; multiphysics modeling and simulation; reliability analysis

Special Issue Information

Dear Colleagues,

Unlike transistors, the continuous downscaling of the feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and the degradation of the concomitant performance. At nanoscale technology nodes, interconnect delay and reliability are the major bottlenecks faced by modern integrated circuits. In order to resolve these interconnect problems, various technologies such as airgap, nanocarbon, optical, and through-silicon via (TSV) have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to enhance the integration density. More importantly, 3D integration and packaging also offer the most promising platform via which to implement “More-than-Moore” technologies, providing heterogenous materials and technologies on a single chip.

This Special Issue seeks to showcase research papers, communications, and review articles on novel developments in advanced interconnect and packaging, namely the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies.

We look forward to receiving your submissions!

Prof. Dr. Wensheng Zhao
Dr. Dawei Wang
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • interconnect
    • on-chip interconnect
    • through-silicon via (TSV)
    • transmission line
  • advanced packaging
  • 3D integrated circuits and microsystems
  • antenna in packaging (AiP)
  • integrated passive device (IPD)

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Related Special Issues

Published Papers (3 papers)

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Research

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18 pages, 5570 KiB  
Article
SPICE-Compatible Degradation Modeling Framework for TDDB and LER Effects in Advanced Packaging BEOL Based on Ion Migration Mechanism
by Shao-Chun Zhang, Sen-Sen Li, Ying Ji, Ning Yang, Yuan-Hao Shan, Li Hong, Hao-Gang Wang, Wen-Sheng Zhao and Da-Wei Wang
Micromachines 2025, 16(7), 766; https://doi.org/10.3390/mi16070766 - 29 Jun 2025
Viewed by 308
Abstract
The time-dependent dielectric breakdown (TDDB) degradation mechanism, governed by the synergistic interaction of multiphysics fields, plays a pivotal role in the performance degradation and eventual failure of semiconductor devices and advanced packaging back-end-of-line (BEOL) structures. This work specifically focuses on the dielectric breakdown [...] Read more.
The time-dependent dielectric breakdown (TDDB) degradation mechanism, governed by the synergistic interaction of multiphysics fields, plays a pivotal role in the performance degradation and eventual failure of semiconductor devices and advanced packaging back-end-of-line (BEOL) structures. This work specifically focuses on the dielectric breakdown mechanism driven by metal ion migration within inter-metal dielectric layers, a primary contributor to TDDB degradation. A SPICE-compatible modeling approach is developed to accurately capture the dynamics of this ion migration-induced degradation. The proposed model is rooted in the fundamental physics of metal ion migration and the evolution of conductive filaments (CFs) within the dielectric layer under operational stress conditions. By precisely characterizing the degradation behavior induced by TDDB, a SPICE-compatible degradation model is developed. This model facilitates accurate predictions of resistance changes across a range of operational conditions and lifetime, encompassing variations in stress voltages, temperatures, and structural parameters. The predictive capability and accuracy of the model are validated by comparing its calculated results with numerical ones, thereby confirming its applicability. Furthermore, building upon the established degradation model, the impact of line-edge roughness (LER) is incorporated through a process variation model based on the power spectral density (PSD) function. This PSD-derived model provides a quantitative characterization of LER-induced fluctuations in critical device dimensions, enabling a more realistic representation of process-related variability. By integrating this stochastic variability model into the degradation framework, the resulting lifetime prediction model effectively captures reliability variations arising from real-world fabrication non-uniformities. Validation against simulation data demonstrates that the inclusion of LER effects significantly improves the accuracy of predicted lifetime curves, yielding closer alignment with observed device behavior under accelerated stress conditions. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
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11 pages, 2741 KiB  
Article
Double-Sided Fabrication of Low-Leakage-Current Through-Silicon Vias (TSVs) with High-Step-Coverage Liner/Barrier Layers
by Baoyan Yang, Houjun Sun, Kaiqiang Zhu and Xinghua Wang
Micromachines 2025, 16(7), 750; https://doi.org/10.3390/mi16070750 - 25 Jun 2025
Viewed by 354
Abstract
In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer [...] Read more.
In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer formation, and double-sided Cu electroplating. This method enhances the TSV stability by eliminating Cu contamination issues during chemical–mechanical polishing (CMP), which are a common challenge in traditional blind via fabrication processes. Additionally, the liner and barrier layer/seed layer achieve a high step coverage exceeding 80%, ensuring excellent conformality and structural integrity. For electroplating, a multi-stage bi-directional electroplating technique is introduced to enable void-free Cu filling in TSVs. The fabricated TSVs exhibit an ultra-low leakage current of 135 fA at 20 V, demonstrating their potential for advancing 3D integration technologies in heterogeneous integration. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
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Review

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21 pages, 18248 KiB  
Review
Electronic Chip Package and Co-Packaged Optics (CPO) Technology for Modern AI Era: A Review
by Guoliang Chen, Guiqi Wang, Zhenzhen Wang and Lijun Wang
Micromachines 2025, 16(4), 431; https://doi.org/10.3390/mi16040431 - 2 Apr 2025
Viewed by 3215
Abstract
With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore’s Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced [...] Read more.
With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore’s Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps’ reliability, through-silicon vias’ (TSVs) and redistribution layers’ (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
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