Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
6.0
3.0
Journals
Micromachines
Special Issues
Advanced Interconnect and Packaging, 3rd Edition
share announcement

Advanced Interconnect and Packaging, 3rd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: 30 April 2026 | Viewed by 17574

Special Issue Editors

Prof. Dr. Wensheng Zhao

E-Mail Website
Guest Editor
School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
Interests: interconnect; packaging; TSV; 3-D IC
Special Issues, Collections and Topics in MDPI journals
Dr. Dawei Wang

E-Mail Website
Guest Editor
School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
Interests: advanced packaging; multiphysics modeling and simulation; reliability analysis

Special Issue Information

Dear Colleagues,

Unlike transistors, the continuous downscaling of the feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and the degradation of the concomitant performance. At nanoscale technology nodes, interconnect delay and reliability are the major bottlenecks faced by modern integrated circuits. In order to resolve these interconnect problems, various technologies such as airgap, nanocarbon, optical, and through-silicon via (TSV) have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to enhance the integration density. More importantly, 3D integration and packaging also offer the most promising platform via which to implement “More-than-Moore” technologies, providing heterogenous materials and technologies on a single chip.

This Special Issue seeks to showcase research papers, communications, and review articles on novel developments in advanced interconnect and packaging, namely the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies.

We look forward to receiving your submissions!

Prof. Dr. Wensheng Zhao
Dr. Dawei Wang
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • interconnect
    • on-chip interconnect
    • through-silicon via (TSV)
    • transmission line
  • advanced packaging
  • 3D integrated circuits and microsystems
  • antenna in packaging (AiP)
  • integrated passive device (IPD)

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • Reprint: MDPI Books provides the opportunity to republish successful Special Issues in book format, both online and in print.

Further information on MDPI's Special Issue policies can be found here.

Related Special Issues

Published Papers (6 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

Jump to: Review

12 pages, 1810 KB  
Article
Study on Stress Distribution and Its Impact on Reliability of SiO2-Based Inorganic Chiplet Gap Filling
by Ziyang Ding, Shaowei Liu, Chen Lin, Tianze Zheng, Lihui Xu, Qiuhan Hu, Tailong Shi and Liyi Li
Micromachines 2025, 16(12), 1310; https://doi.org/10.3390/mi16121310 - 22 Nov 2025
Viewed by 397
Abstract
Inorganic gap filling technology is an effective method to improve reliability and heterogeneous integration density in 2.5D and 3D integration. It uses plasma-enhanced chemical vapor deposition (PECVD) to deposit silicon dioxide (SiO2) filler layers in gaps between chiplets. This technology is [...] Read more.
Inorganic gap filling technology is an effective method to improve reliability and heterogeneous integration density in 2.5D and 3D integration. It uses plasma-enhanced chemical vapor deposition (PECVD) to deposit silicon dioxide (SiO2) filler layers in gaps between chiplets. This technology is used to replace the Epoxy Mold Compound (EMC) commonly used in traditional packaging. However, as an inorganic filling material, SiO2 poses reliability challenges such as cracking and peeling during or after deposition. Furthermore, there lacks quantitative characterization and modeling of the microscale mechanical properties, thermal stress distribution, and fracture failure risk in the filler layer. By combining nanoindentation technology with three-point bending tests, this study reports a comprehensive characterization route for quantitative characterization of mechanical behavior of the filler. A finite element method (FEM) model was also established to predict the thermomechanical reliability of the gap filling process. Raman spectroscopy measured data confirm the model’s reliable predictive ability. The results reveal the impact of filler thickness on the stress. The microscale SiO2 mechanical characterization method and the thermal stress and fracture risk FEM prediction model in this study not only address the limitations of traditional testing and simulation but also provide support for process optimization and structural design of gap filling in high-density 2.5D/3D packaging. This work promotes the understanding of inorganic filling process reliability in chiplet integration. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
►▼ Show Figures

Figure 1

14 pages, 3515 KB  
Article
Post-Bonding Crack-Induced Di-Cantilever Bending (PBC-DCB): A Novel Method for Quantitative Evaluation of Bonding Strength for Wafer-to-Wafer and Die-to-Wafer Hybrid Bonding
by Tianze Zheng, Yuan Xu, Cong Mei, Yingjie Chen, Liu Chang, Gangli Yang, Qiuhan Hu, Tailong Shi, Yuan Yuan, Zongguang Yu and Liyi Li
Micromachines 2025, 16(12), 1304; https://doi.org/10.3390/mi16121304 - 21 Nov 2025
Viewed by 401
Abstract
To address the challenge of characterizing bonding strength in hybrid bonding, this paper proposes a method based on post-bonding crack-induced di-cantilever bending (PBC-DCB). The commonly used industrial blade insertion (BI) method only measures the edge strength of wafer-to-wafer samples via bevel geometry, failing [...] Read more.
To address the challenge of characterizing bonding strength in hybrid bonding, this paper proposes a method based on post-bonding crack-induced di-cantilever bending (PBC-DCB). The commonly used industrial blade insertion (BI) method only measures the edge strength of wafer-to-wafer samples via bevel geometry, failing to characterize the wafer center or die-to-wafer samples (as they lack a bevel) and exhibiting limited accuracy due to irregular crack edges. This study develops a di-cantilever beam test initiated by a specially prepared post-bonding notch. By deriving the relationship between load–displacement and bonding strength based on fracture mechanics and optimizing sample preparation and testing parameters, quantitative measurement of interface fracture strength is achieved. Experimental results show the method has a deviation < 5% from BI with better repeatability, verifying its reliability. It successfully distinguishes bonding strength between wafer center and edge and reveals that SiCN dielectric layers have 17.34% higher strength and better uniformity than SiO2. This provides a reliable testing tool for hybrid bonding quality and process optimization, with broad prospects in industrial production and scientific research. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
►▼ Show Figures

Figure 1

18 pages, 5461 KB  
Article
Numerical Investigation of Crack Suppression Strategies in Ultra-Thin Glass Substrates for Advanced Packaging
by Xuan-Bach Le, Kee-Youn Yoo and Sung-Hoon Choa
Micromachines 2025, 16(11), 1256; https://doi.org/10.3390/mi16111256 - 1 Nov 2025
Viewed by 1107
Abstract
The mechanical reliability of glass substrates is a key challenge for their adoption in advanced semiconductor packaging. This study employs finite element analysis to systematically evaluate the risk of edge crack propagation in large glass panels during redistribution layer (RDL) fabrication. The influence [...] Read more.
The mechanical reliability of glass substrates is a key challenge for their adoption in advanced semiconductor packaging. This study employs finite element analysis to systematically evaluate the risk of edge crack propagation in large glass panels during redistribution layer (RDL) fabrication. The influence of critical factors—including crack location, number of RDLs, glass material and thickness, dielectric ABF properties, Cu content, and edge clearance—was examined. Results revealed that top-edge crack near the RDL/glass interface pose the highest failure risk due to elevated peeling stress and increased energy release rate (ERR). The risk of propagation intensifies with more RDLs and thinner glass, while high CTE (coefficients of thermal expansion) glasses such as D263, Gorilla, and ceramic glass markedly suppress crack growth compared with borofloat 33 and fused silica. Among ABF dielectrics, GZ-41 demonstrated superior crack resistance owing to its low CTE and moderate stiffness. Although higher Cu content slightly reduced ERR, its effect remained limited. Edge clearance strongly affects reliability, with ≥300 µm providing effective suppression of crack propagation. These findings provide quantitative design guidelines for glass interposer structures, emphasizing the optimization of dielectric material selection, glass substrate and thickness, and layout constraints such as edge clearance. The proposed methodology and results will contribute to establishing reliable strategies for deploying ultra-thin glass panels in advanced semiconductor packaging. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
►▼ Show Figures

Figure 1

18 pages, 5570 KB  
Article
SPICE-Compatible Degradation Modeling Framework for TDDB and LER Effects in Advanced Packaging BEOL Based on Ion Migration Mechanism
by Shao-Chun Zhang, Sen-Sen Li, Ying Ji, Ning Yang, Yuan-Hao Shan, Li Hong, Hao-Gang Wang, Wen-Sheng Zhao and Da-Wei Wang
Micromachines 2025, 16(7), 766; https://doi.org/10.3390/mi16070766 - 29 Jun 2025
Viewed by 3753
Abstract
The time-dependent dielectric breakdown (TDDB) degradation mechanism, governed by the synergistic interaction of multiphysics fields, plays a pivotal role in the performance degradation and eventual failure of semiconductor devices and advanced packaging back-end-of-line (BEOL) structures. This work specifically focuses on the dielectric breakdown [...] Read more.
The time-dependent dielectric breakdown (TDDB) degradation mechanism, governed by the synergistic interaction of multiphysics fields, plays a pivotal role in the performance degradation and eventual failure of semiconductor devices and advanced packaging back-end-of-line (BEOL) structures. This work specifically focuses on the dielectric breakdown mechanism driven by metal ion migration within inter-metal dielectric layers, a primary contributor to TDDB degradation. A SPICE-compatible modeling approach is developed to accurately capture the dynamics of this ion migration-induced degradation. The proposed model is rooted in the fundamental physics of metal ion migration and the evolution of conductive filaments (CFs) within the dielectric layer under operational stress conditions. By precisely characterizing the degradation behavior induced by TDDB, a SPICE-compatible degradation model is developed. This model facilitates accurate predictions of resistance changes across a range of operational conditions and lifetime, encompassing variations in stress voltages, temperatures, and structural parameters. The predictive capability and accuracy of the model are validated by comparing its calculated results with numerical ones, thereby confirming its applicability. Furthermore, building upon the established degradation model, the impact of line-edge roughness (LER) is incorporated through a process variation model based on the power spectral density (PSD) function. This PSD-derived model provides a quantitative characterization of LER-induced fluctuations in critical device dimensions, enabling a more realistic representation of process-related variability. By integrating this stochastic variability model into the degradation framework, the resulting lifetime prediction model effectively captures reliability variations arising from real-world fabrication non-uniformities. Validation against simulation data demonstrates that the inclusion of LER effects significantly improves the accuracy of predicted lifetime curves, yielding closer alignment with observed device behavior under accelerated stress conditions. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
►▼ Show Figures

Figure 1

11 pages, 2741 KB  
Article
Double-Sided Fabrication of Low-Leakage-Current Through-Silicon Vias (TSVs) with High-Step-Coverage Liner/Barrier Layers
by Baoyan Yang, Houjun Sun, Kaiqiang Zhu and Xinghua Wang
Micromachines 2025, 16(7), 750; https://doi.org/10.3390/mi16070750 - 25 Jun 2025
Cited by 1 | Viewed by 1871
Abstract
In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer [...] Read more.
In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer formation, and double-sided Cu electroplating. This method enhances the TSV stability by eliminating Cu contamination issues during chemical–mechanical polishing (CMP), which are a common challenge in traditional blind via fabrication processes. Additionally, the liner and barrier layer/seed layer achieve a high step coverage exceeding 80%, ensuring excellent conformality and structural integrity. For electroplating, a multi-stage bi-directional electroplating technique is introduced to enable void-free Cu filling in TSVs. The fabricated TSVs exhibit an ultra-low leakage current of 135 fA at 20 V, demonstrating their potential for advancing 3D integration technologies in heterogeneous integration. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
►▼ Show Figures

Figure 1

Review

Jump to: Research

21 pages, 18248 KB  
Review
Electronic Chip Package and Co-Packaged Optics (CPO) Technology for Modern AI Era: A Review
by Guoliang Chen, Guiqi Wang, Zhenzhen Wang and Lijun Wang
Micromachines 2025, 16(4), 431; https://doi.org/10.3390/mi16040431 - 2 Apr 2025
Cited by 3 | Viewed by 9149
Abstract
With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore’s Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced [...] Read more.
With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore’s Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps’ reliability, through-silicon vias’ (TSVs) and redistribution layers’ (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging, 3rd Edition)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-6
Back to TopTop