Search Results (877)

Grid-forming (GFM) inverters have recently seen wider adoption in microgrids and inverter-based-resource (IBR)-penetrated grids, and are primarily used to establish grid voltage under a wide array of conditions. In the existing literature, GFM control is almost exclusively applied using voltage-source inverters (VSIs). However, due to the inherent limitations of available semiconductor devices’ current ratings, inverter-side current must be limited in VSIs, particularly during grid-fault conditions. These limitations complicate the real-world application of GFM functionality in VSIs, and complex control methodologies and tuning parameters are required as a result. In the following study, GFM control is instead applied to a buck-type current-source inverter (CSI) using a combination of linear droop-control and finite-control-set (FCS) mode-predictive control (MPC) that will be referred to herein as hybrid model-predictive control (HMPC). The resulting inverter features a simple topology, inherent current limiting capabilities, and a relatively simple and intuitive control structure. Verification was performed on a 1MVA/630V system via MATLAB/Simulink, and the simulation results demonstrate strong performance in voltage establishment, power regulation, and low-voltage ride through under-grid-fault conditions, highlighting its potential as a competent alternative to VSIs in GFM applications, and lacking the inherent limitations and/or complexity of existing GFM control methodologies. Full article

Diamond, renowned for its exceptional electrical, physical, and chemical properties, including ultra-wide bandgap, superior hardness, high thermal conductivity, and unparalleled stability, serves as an ideal candidate for next-generation high-power and high-temperature electronic devices. Among diamond-based devices, Schottky barrier diodes (SBDs) have garnered significant attention due to their simple architecture and superior rectifying characteristics. This review systematically summarizes recent advances in diamond SBDs, focusing on both metal–semiconductor (MS) and metal–interlayer–semiconductor (MIS) configurations. For MS structures, we critically analyze the roles of single-layer metals (including noble metals, transition metals, and other metals) and multilayer metals in modulating Schottky barrier height (SBH) and enhancing thermal stability. However, the presence of interface-related issues such as high densities of surface states and Fermi level pinning often leads to poor control of the SBH, limiting device performance and reliability. To address these challenges and achieve high-quality metal/diamond interfaces, researchers have proposed various interface engineering strategies. In particular, the introduction of interfacial layers in MIS structures has emerged as a promising approach. For MIS architectures, functional interlayers—including high-k materials (Al₂O₃, HfO₂, SnO₂) and low-work-function materials (LaB₆, CeB₆)—are evaluated for their efficacy in interface passivation, barrier modulation, and electric field control. Terminal engineering strategies, such as field-plate designs and surface termination treatments, are also highlighted for their role in improving breakdown voltage. Furthermore, we emphasize the limitations in current parameter extraction from current–voltage (I–V) properties and call for a unified new method to accurately determine SBH. This comprehensive analysis provides critical insights into interface engineering strategies and evaluation protocols for high-performance diamond SBDs, paving the way for their reliable deployment in extreme conditions. Full article

The rapid development of high-power-density semiconductor devices has rendered conventional thermal management techniques inadequate for handling their extreme heat fluxes. This manuscript presents and implements an embedded microchannel cooling solution for such devices. By directly integrating micropillar arrays within the near-junction region of the substrate, efficient forced convection and flow boiling mechanisms are achieved. Finite element analysis was first employed to conduct thermo–fluid–structure simulations of micropillar arrays with different geometries. Subsequently, based on our simulation results, a complete multilayer microstructure fabrication process was developed and integrated, including critical steps such as deep reactive ion etching (DRIE), surface hydrophilic/hydrophobic functionalization, and gold–stannum (Au-Sn) eutectic bonding. Finally, an experimental test platform was established to systematically evaluate the thermal performance of the fabricated devices under heat fluxes of up to 1200 W/cm². Our experimental results demonstrate that this solution effectively maintains the device operating temperature at 46.7 °C, achieving a mere 27.9 K temperature rise and exhibiting exceptional thermal management capabilities. This manuscript provides a feasible, efficient technical pathway for addressing extreme heat dissipation challenges in next-generation electronic devices, while offering notable references in structural design, micro/nanofabrication, and experimental validation for related fields. Full article

With the rapid development of information technology and semiconductor technology, the iteration speed of electronic devices has accelerated in an unprecedented manner, and the market demand for miniaturized, highly integrated, and highly intelligent devices continues to rise. But when these electronic devices operate at high power, the electronic components generate a large amount of integrated heat. Due to the limitations of existing heat dissipation channels, the current heat dissipation performance of electronic packaging materials is struggling to meet practical needs, resulting in heat accumulation and high temperatures inside the equipment, seriously affecting operational stability. For electronic devices that require high energy density and fast signal transmission, improving the heat dissipation capability of electronic packaging materials can significantly enhance their application prospects. In order to improve the thermal conductivity of composite materials, hexagonal boron nitride (h-BN) was selected as the thermal filling material in this paper. The BMI resin was structurally modified through molecular structure design. The results showed that the micro-branched structure and h-BN synergistically improved the thermal conductivity and insulation performance of the composite material, with a thermal conductivity coefficient of 1.51 W/(m·K) and a significant improvement in insulation performance. The core mechanism is the optimization of the dispersion state of h-BN filler in the matrix resin through the free volume in the micro-branched structure, which improves the thermal conductivity of the composite material while maintaining high insulation. Full article

Thermal management is an area of study in electronics focused on managing temperature to improve reliability and efficiency. When temperatures are too high, cooling systems are activated to prevent overheating, which can lead to reliability issues. To monitor the temperatures, sensors are often placed on-chip near hotspot locations. These sensors should be very small to allow them to be placed among compact, high-activity circuits. Often, they are connected to a central control circuit located far away from the hot spot locations where more area is available. This paper proposes sensing units for a novel temperature sensing architecture in the TSMC 180 nm process. This architecture functions by approximating the current through the sensing unit at a reference voltage, which is used to approximate the temperature in the digital back end using fitting functions. Sensing units are selected based on how well its temperature–current relationship can be modeled, sensing unit area, and power consumption. Many sensing units will be experimented with at different reference voltages. These temperature–current curves will be modeled with various fitting functions. The sensing unit selected is a diode-connected p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a size of W = 400 nm, L = 180 nm. This sensing unit is exceptionally small compared to existing work because it does not rely on multiple devices at the sensing unit location to generate a PTAT or IPTAT signal like most work in this area. The temperature–current relationship of this device can also be modeled using a 2nd order polynomial, requiring a minimal number of trim temperatures. Its temperature error is small, and the power consumption is low. The range of currents for this sensing unit could be reasonably made on an IDAC. Full article

This paper presents the first hybrid supply modulator (HSM) designed for envelope tracking power amplifiers (ET-PAs) in base station applications. The focus is on a rail-to-rail Class-AB linear amplifier (LA) optimized for high-voltage and wide-bandwidth operation. The LA is designed using 130 nm BCD technology, utilizing Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistors for high-voltage operation and incorporating shielding MOSFETs to protect the low-voltage devices. The circuit utilizes dual power supply domains (5 V and 30 V) to improve power efficiency. The proposed LA achieves a bandwidth of 100 MHz and a slew rate of +1003/−852 V/$\mathsf{\mu }\mathrm{s}$, with a quiescent power consumption of 0.89 W. Transient simulations using a 50 MHz bandwidth 5G NR envelope input demonstrate that the proposed HSM achieves a power efficiency of 83%. Consequently, the proposed HSM supports high-output (100 W) wideband 5G NR transmission with enhanced efficiency. Full article

The development of an integrated circuit faces the challenge of the physical limit of Moore’s Law. One of the most important “Beyond Moore” challenges is the scaling down of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) versus their increasing static power consumption. This is because, at room temperature, the thermal emission transportation mechanism will cause a physical limitation on subthreshold swing (SS), which is fundamentally limited to a minimum value of 60 mV/decade for MOSFETs, and accompanied by an increase in off-state leakage current with the process of scaling down. Moreover, the impacts of short-channel effects on device performance also become an increasingly severe problem with channel length scaling down. Due to the band-to-band tunneling mechanism, Tunnel Field-Effect Transistors (TFETs) can reach a far lower SS than MOSFETs. Recent research works indicated that TFETs are already becoming some of the promising candidates of conventional MOSFETs for ultra-low-power applications. This paper provides a review of some advances in materials and structures along the evolutionary process of TFETs. An in-depth discussion of both experimental works and simulation works is conducted. Furthermore, the performance of TFETs with different structures and materials is explored in detail as well, covering Si, Ge, III-V compounds and 2D materials, alongside different innovative device structures. Additionally, this work provides an outlook on the prospects of TFETs in future ultra-low-power electronics and biosensor applications. Full article

As a promising n-type semiconductor thermoelectric material, ZnO has great potential in the high-temperature working temperature range due to its advantages of abundant sources, low cost, high thermal stability, and good chemical stability, as well as being pollution-free. Sr-doped ZnO-based thermoelectric materials were prepared using the methods of room-temperature powder synthesis and high-temperature block synthesis. The phase composition, crystal structure, and thermoelectric performances of ZnO samples with different Sr doping levels were analyzed using XRD, material simulation software and thermoelectric testing devices, and the optimal doping concentrations were obtained. The results show that Sr doping could cause the Zn-O bond to become shorter; in addition, the hybridization between Zn and O atoms would become stronger, and the Sr atom would modify the density of states near the Fermi level, which could significantly increase the carrier concentration, electrical conductivity, and corresponding power factor. Sr doping could cause lattice distortion, enhance the phonon scattering effect, and decrease the lattice thermal conductivity and thermal conductivity. Sr doping can achieve the effect of improving electrical transport performance and decreasing thermal transport performance. The ZT value increased to ~0.418 at 873 K, which is ~4.2 times the highest ZT of the undoped ZnO sample. The Vickers hardness was increased to ~351.1 HV, which is 45% higher than the pristine ZnO. Full article

CdS nanowires have garnered considerable attention lately for their promising potential in next-generation nanolaser devices, attributed to their relatively high stability and exceptional emission efficiency within the Ⅱ–Ⅵ semiconductor family. In this study, tin-doped CdS nanowires with varying dimensions were synthesized, and the underlying mechanisms responsible for the formation of micro-cavities within these nanowires were systematically explored through scanning electron microscopy (SEM) analysis and photoluminescence mapping. The results show that a very distinct hexagonal-shaped micro-cavity is observed on the cross-section of CdS nanowires, and the size of the micro-cavity is determined by the radius of the nanowire. Additionally, through the use of angle-resolved micro-fluorescence Fourier imaging technology, it is found that under high excitation density conditions, the micro-cavity mode is more prominent at higher collection angles, which is consistent with the mode of the wall-pass cavity micro-cavity. Finally, the formation of the full reflection spectrum of the micro-cavity mode is confirmed through the wavelength shift and intensity shift phenomena related to the excitation power. These results further deepen our understanding of the micro-cavity modes in tin-doped cadmium sulfide nanowires, which may be of great significance for the application of these nanowires in new optical devices. Full article

Tracking the state of the health of electrical insulation in high-power electric machines has always been a topic of great interest due to the high cost of downtime associated with unexpected failures. Over the years, there have been continuous efforts to develop and improve upon methods for testing and categorizing the health and expected lifetime of stator insulation. Methods such as partial discharge, surge, and dissipation factor testing are common examples. With the increasing use of high-specific-power electric machines in new applications such as traction and wind power generation, coupled with the increasing use of wide-bandgap semiconductor device-based inverters, some traditional methods for insulation health tracking may need adjustments or be combined with newer methods to remain accurate and useful. This paper outlines a review of the traditional insulation health tracking methods and newer methods and improvements that have been proposed to address the concerns and shortcomings of traditional methods. Full article

III-Nitride semiconductors (BN, AlN, GaN, and InN) exhibit exceptional electronic and mechanical properties that render them indispensable for high-performance optoelectronic, power, and high-frequency device applications. This study implements first-principles Density Functional Theory (DFT) calculations to elucidate the influence of hydrostatic pressure on the electronic, elastic, and mechanical properties of these materials in the wurtzite crystallographic configuration. Our computational analysis demonstrates that the bandgap energy exhibits a positive pressure coefficient for GaN, AlN, and InN, while BN manifests a negative pressure coefficient consistent with its indirect-bandgap characteristics. The elastic constants and derived mechanical properties reveal material-specific responses to applied pressure, with BN maintaining superior stiffness across the pressure range investigated, while InN exhibits the highest ductility among the studied compounds. GaN and AlN demonstrate intermediate mechanical robustness, positioning them as optimal candidates for pressure-sensitive applications. Furthermore, the observed nonlinear trends in elastic moduli under pressure reveal anisotropic mechanical responses during compression, a phenomenon critical for the rational design of strain-engineered devices. The computational results provide quantitative insights into the pressure-dependent behavior of III-N semiconductors, facilitating their strategic implementation and optimization for high-performance applications in extreme environmental conditions, including high-power electronics, deep-space exploration systems, and high-pressure optoelectronic devices. Full article

In this study, we introduce a high-resolution, high-speed thermal imaging technique using Raman spectroscopy to simultaneously measure the temperature of a substrate and a channel. By modifying the Raman spectrometer, we achieved a measurement speed faster than commercial spectrometers. This system demonstrated a sub-micron spatial resolution and the ability to measure the temperatures of the Si substrate and GaN channel simultaneously. During high-current operation, we observed significant self-heating in the GaN channel, with hotspots 100 °C higher than the surroundings, while the Si substrate showed an even temperature distribution. The ability to detect hotspots can help secure the reliability of devices through early failure analysis and can also be used for improvement research to reduce hotspots. These findings highlight the potential of this technique for early defect inspection and device improvement research. This study provides a novel and effective method for measuring the sub-micron resolution temperature distribution in devices, which can be applied to various semiconductor devices, including SiC-based power devices. Full article

Gallium oxide (Ga₂O₃), as a wide-bandgap semiconductor material, is highly expected to find extensive applications in optoelectronic devices, high-power electronics, gas sensors, etc. However, the photoelectric properties of Ga₂O₃ still need to be improved before its devices become commercially viable. As is well known, doping is an effective method to modulate the various properties of semiconductor materials. In this study, Zn–N co-doped Ga₂O₃ films with various doping concentrations were grown in situ on sapphire substrates by atomic layer deposition (ALD) at 250 °C, followed by post-annealing at 900 °C. The post-annealed undoped Ga₂O₃ film showed a highly preferential orientation, whereas with the increase in Zn doping concentration, the preferential orientation of Ga₂O₃ films was deteriorated, turning it into an amorphous state. The surface roughness of the Ga₂O₃ thin films is largely affected by doping. As a result of post-annealing, the bandgaps of the Ga₂O₃ films can be modulated from 4.69 eV to 5.41 eV by controlling the Zn–N co-doping concentrations. When deposited under optimum conditions, high-quality Zn–N co-doped Ga₂O₃ films showed higher transmittance, a larger bandgap, and fewer defects compared with undoped ones. Full article

In this study, we present a comprehensive numerical investigation of alternating-current electrothermal (ACET) pumping strategies tailored for energy-efficient microfluidic applications. Using coupled electrokinetic and thermal multiphysics simulations in narrow microchannels, we systematically explore the effects of channel geometry, electrode asymmetry and external heating on flow performance and thermal management. A rigorous mesh convergence study confirms velocity deviations below ±0.006 µm/s across the entire operating envelope, ensuring reliable prediction of ACET-driven flows. We demonstrate that increasing channel height from 100 µm to 500 µm reduces peak temperatures by up to 79 K at a constant 2 W heat input, highlighting the critical role of channel dimensions in convective heat dissipation. Introducing a localized external heat source beneath asymmetric electrode pairs enhances convective circulations, while doubling the fluid’s electrical conductivity yields a ~29% increase in net flow rate. From these results, we derive practical design guidelines—combining asymmetric electrode layouts, tailored channel heights, and external heat bias—to realize self-regulating, low-power microfluidic pumps. Such devices hold significant promises for on-chip semiconductor cooling, lab-on-a-chip assays and real-time thermal control in high-performance microelectronic and analytical systems. Full article

Semiconductor device fabrication is conducted through highly precise manufacturing processes. An essential component of the semiconductor package is the lead frame on which the silicon dies are assembled. Impurities such as oxides or organic matter on the surfaces have an impact on the process yield. Plasma cleaning is a vital process in semiconductor manufacturing, employed to enhance production yield through precise and efficient surface preparation essential for device fabrication. This paper explores the various facets of plasma cleaning, with a particular emphasis on its application in the cleaning of lead frames used in semiconductor packaging. To provide comprehensive context, this paper also reviews the critical role of plasma in advanced and emerging packaging technologies. This study investigates the fundamental physics governing plasma generation, the design of plasma systems, and the composition of the plasma medium. A central focus of this work is the comparative analysis of different plasma systems in terms of their effectiveness in removing organic contaminants and oxide residues from substrate surfaces. By utilizing reactive species generated within the plasma—such as oxygen radicals, hydrogen ions, and other chemically active constituents—these systems enable a non-contact, damage-free cleaning method that offers significant advantages over conventional wet chemical processes. Additionally, the role of non-reactive species, such as argon, in sputtering processes for surface preparation is examined. Sputtering is the ejection of individual atoms from a target surface due to momentum transfer from an energetic particle (usually an ion). Sputtering is therefore a physical process driven by momentum transfer. Energetic ions, such as argon (Ar⁺), are accelerated from the plasma to bombard a target surface. Upon impact, these ions transfer sufficient kinetic energy to atoms within the material’s lattice to overcome their surface binding energy, resulting in their physical ejection. This paper also provides a comparative assessment of various plasma sources, including direct current, dielectric barrier discharge, radio frequency, and microwave-based systems, evaluating their suitability and efficiency for lead frame cleaning applications. Furthermore, it addresses critical parameters affecting plasma cleaning performance, such as gas chemistry, power input, pressure regulation, and substrate handling techniques. The ultimate aim of this paper is to provide a concise yet comprehensive resource that equips technical personnel with the essential knowledge required to make informed decisions regarding plasma cleaning technologies and their implementation in semiconductor manufacturing. This paper provides various tables which provide the reader with comparative assessments of the various plasma sources and gases used. Scoring mechanisms are also introduced and utilized in this paper. The scores achieved by both the sources and the plasma gases are then summarized in this paper’s conclusions. Full article