Search Results (1,318)

For high-voltage signal detection applications, an auto-zero and chopper operational amplifier (OPA) is proposed in this paper. With the auto-zero and chopper technique, the OPA adopts an eight-channel Ping-Pong mechanism to reduce the high-frequency ripple and glitch generated by chopper modulation. The main transconductor effectively suppresses low-frequency noise and offset by combining input coarse and output fine auto-zero. A common-mode voltage tracking circuit is presented to ensure constant gate-source and gate-substrate voltages of the chopper, which reduces the charge injection caused by threshold voltage drift of their transistors and improves output signal resolution. The OPA is implemented using CMOS 180 nm BCD process. The post-simulation results show that the unit gain bandwidth (UGB) is 2.5 MHz and common-mode rejection ratio (CMRR) is 137 dB when the power supply voltage is 5–55 V. The noise power spectral density (PSD) is 6.6 nV/√Hz, and the offset is about 47 µV. The overall circuit consumes current of 960 µA. Full article

Thermal management is an area of study in electronics focused on managing temperature to improve reliability and efficiency. When temperatures are too high, cooling systems are activated to prevent overheating, which can lead to reliability issues. To monitor the temperatures, sensors are often placed on-chip near hotspot locations. These sensors should be very small to allow them to be placed among compact, high-activity circuits. Often, they are connected to a central control circuit located far away from the hot spot locations where more area is available. This paper proposes sensing units for a novel temperature sensing architecture in the TSMC 180 nm process. This architecture functions by approximating the current through the sensing unit at a reference voltage, which is used to approximate the temperature in the digital back end using fitting functions. Sensing units are selected based on how well its temperature–current relationship can be modeled, sensing unit area, and power consumption. Many sensing units will be experimented with at different reference voltages. These temperature–current curves will be modeled with various fitting functions. The sensing unit selected is a diode-connected p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a size of W = 400 nm, L = 180 nm. This sensing unit is exceptionally small compared to existing work because it does not rely on multiple devices at the sensing unit location to generate a PTAT or IPTAT signal like most work in this area. The temperature–current relationship of this device can also be modeled using a 2nd order polynomial, requiring a minimal number of trim temperatures. Its temperature error is small, and the power consumption is low. The range of currents for this sensing unit could be reasonably made on an IDAC. Full article

This paper presents the first hybrid supply modulator (HSM) designed for envelope tracking power amplifiers (ET-PAs) in base station applications. The focus is on a rail-to-rail Class-AB linear amplifier (LA) optimized for high-voltage and wide-bandwidth operation. The LA is designed using 130 nm BCD technology, utilizing Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistors for high-voltage operation and incorporating shielding MOSFETs to protect the low-voltage devices. The circuit utilizes dual power supply domains (5 V and 30 V) to improve power efficiency. The proposed LA achieves a bandwidth of 100 MHz and a slew rate of +1003/−852 V/$\mathsf{\mu }\mathrm{s}$, with a quiescent power consumption of 0.89 W. Transient simulations using a 50 MHz bandwidth 5G NR envelope input demonstrate that the proposed HSM achieves a power efficiency of 83%. Consequently, the proposed HSM supports high-output (100 W) wideband 5G NR transmission with enhanced efficiency. Full article

The development of an integrated circuit faces the challenge of the physical limit of Moore’s Law. One of the most important “Beyond Moore” challenges is the scaling down of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) versus their increasing static power consumption. This is because, at room temperature, the thermal emission transportation mechanism will cause a physical limitation on subthreshold swing (SS), which is fundamentally limited to a minimum value of 60 mV/decade for MOSFETs, and accompanied by an increase in off-state leakage current with the process of scaling down. Moreover, the impacts of short-channel effects on device performance also become an increasingly severe problem with channel length scaling down. Due to the band-to-band tunneling mechanism, Tunnel Field-Effect Transistors (TFETs) can reach a far lower SS than MOSFETs. Recent research works indicated that TFETs are already becoming some of the promising candidates of conventional MOSFETs for ultra-low-power applications. This paper provides a review of some advances in materials and structures along the evolutionary process of TFETs. An in-depth discussion of both experimental works and simulation works is conducted. Furthermore, the performance of TFETs with different structures and materials is explored in detail as well, covering Si, Ge, III-V compounds and 2D materials, alongside different innovative device structures. Additionally, this work provides an outlook on the prospects of TFETs in future ultra-low-power electronics and biosensor applications. Full article

Aiming at the problems of low withstand voltage and poor RF performance of traditional HEMT devices, a new AlGaN/GaN high electron mobility transistor device with a π-gate (NπGS HEMT) is designed in this paper. The new structure incorporates a π-gate design along with a PN-junction field plate and an AlGaN back-barrier layer. The device is modeled and simulated in Silvaco TCAD 2015 software and compared with traditional t-gate HEMT devices. The results show that the NπGS HEMT has a significant improvement in various characteristics. The new structure has a higher peak transconductance of 336 mS·mm⁻¹, which is 13% higher than that of the traditional HEMT structure. In terms of output characteristics, the new structure has a higher saturation drain current of 0.188 A/mm. The new structure improves the RF performance of the device with a higher maximum cutoff frequency of about 839 GHz. The device also has a better performance in terms of voltage withstand, exhibiting a higher breakdown voltage of 1817 V. These results show that the proposed new structure could be useful for future research on high voltage withstand and high RF HEMT devices. Full article

This paper presents a complete workflow for the evaluation of GaN transistors in voltage source inverters. With the associated high switching speed of transistors based on GaN, it is important to consider some critical points in the design phase as well as in the measurement setup in order to be able to utilise and verify the advantages of GaN properly. For this reason, the presented circuit board’s design focuses on a minimised power loop inductance. Simulation models, an analytical approach and measurement results with the aim of determining this inductance are compared with each other. A good compliance results between the presented methods. Additionally, the description of a test bench is given, which enables the performance of the opposition method. This setup allows the measurement of the designed H-bridge’s arising losses and the GaN-transistor’s switching behaviour. In comparison to the conventional double pulse method, this approach enables results that are more accurate for determining losses. Full article

Indium-based oxide semiconductors have been commercialized because of their excellent electrical properties, but the high cost, limited availability, and environmental toxicity of indium necessitate the development of alternative materials. Among the most promising candidates, zinc–tin oxide (ZTO) is an indium-free oxide semiconductor with considerable potential, but its relatively low carrier mobility and inherent limitations in thin-film quality demand further performance enhancements. This paper proposes a new approach to overcome these challenges by incorporating single-walled carbon nanotubes (SWNTs) as conductive fillers into the ZTO matrix and using a layer-by-layer multiple coating process to construct nanocomposite thin films. As a result, ZTO/SWNTs (0.07 wt.%) thin-film transistors (TFTs) fabricated with three coating cycles exhibited a high saturation mobility of 18.72 cm²/V·s, a threshold voltage of 0.84 V, and a subthreshold swing of 0.51 V/dec. These values represent an approximately four-fold improvement in mobility compared to ZTO TFT, showing that the multiple-coating-based nanocomposite strategy can effectively overcome the fundamental limitations. This study confirms the feasibility of achieving high-performance oxide semiconductor transistors without indium, providing a sustainable pathway for next-generation flexible electronics and display technologies. Full article

Gallium nitride (GaN) enhancement-mode high-electron-mobility transistors ( E-HEMTs) deliver superior performance compared to traditional silicon (Si) and silicon carbide (SiC) counterparts. Their faster switching speeds, lower on-state resistances, and higher operating frequencies enable more efficient and compact power converters. However, their integration into high-power applications is limited by critical reliability concerns, particularly regarding their short-circuit (SC) withstand capability and overvoltage (OV) resilience. GaN devices typically exhibit SC withstand times of only a few hundred nanoseconds, needing ultrafast protection circuits, which conventional desaturation (DESAT) methods cannot adequately provide. Furthermore, their high switching transients increase the risk of false activation events. The lack of avalanche capability and the dynamic nature of GaN breakdown voltage exacerbate issues related to OV stress during fault conditions. Although SC-related behaviour in GaN devices has been previously studied, a focused and comprehensive review of protection strategies tailored to GaN technology remains lacking. This paper fills that gap by providing an in-depth analysis of SC and OV failure phenomena, coupled with a critical evaluation of current and next-generation protection schemes suitable for GaN-based high-power converters. Full article

Gallium nitride high-electron-mobility transistors (GaN HEMTs) are critical for high-power applications like AI power supplies and robotics but face reliability challenges due to increased dynamic ON-resistance (R_{DS_ON}) from electrical and thermomechanical stresses. This paper presents a novel self-calibrating temperature-sensitive electrical parameter (TSEP) model that uses gate leakage current (I_G) to estimate junction temperature with high accuracy, uniquely addressing aging effects overlooked in prior studies. By integrating I_G, aging-induced degradation, and failure-in-time (FIT) models, the approach achieves a junction temperature estimation error of less than 1%. Long-term hard-switching tests confirm its effectiveness, with calibrated R_{DS_ON} measurements enabling precise remaining useful life (RUL) predictions. This methodology significantly improves GaN HEMT reliability assessment, enhancing their performance in resilient power electronics systems. Full article

The advancement of Internet of Things (IoT) technology has enabled battery-powered devices to be deployed across a wide range of applications; however, it also introduces challenges such as high energy consumption and security vulnerabilities. To address these issues, adiabatic logic circuits offer a promising solution for achieving energy efficiency and enhancing the security of IoT devices. Adiabatic logic circuits are well suited for energy harvesting systems, especially in applications such as sensor nodes, RFID tags, and other IoT implementations. In these systems, the harvested bipolar sinusoidal RF power is directly used as the power supply for the adiabatic logic circuit. However, adiabatic circuits require a peak detector to provide bulk biasing for pMOS transistors. To meet this requirement, a diode-connected MOS transistor-based voltage doubler circuit is used to convert the sinusoidal input into a usable DC signal. In this paper, we propose a novel adiabatic logic design that maintains low power consumption while optimizing energy and current fluctuations across various input transitions. By ensuring uniform and complementary current flow in each transition within the logic circuit’s functional blocks, the design reduces energy variation and enhances resistance against power analysis attacks. Evaluation under different clock frequencies and load capacitances demonstrates that the proposed adiabatic logic circuit exhibits lower fluctuation and improved security, particularly at load capacitances of 50 fF and 100 fF. The results show that the proposed circuit achieves lower power dissipation compared to conventional designs. As an application example, we implemented an ultrasonic transmitter circuit within a LoRaWAN network at the end-node sensor level, which serves as both a communication protocol and system architecture for long-range communication systems. Full article

Many novel microwave devices have been developed based on the left-handed (LH) structure. This paper studies three CMOS standing-wave oscillators (SWOs) using an LH LC network. The first SWO is a class-B VCO, and the second SWO is a class-C SWO. The SWOs are implemented with the TSMC 0.18 μm 1P6M CMOS process technology. The SWOs utilize two units of an LH LC resonator, and the LC resonator is shunted with a pair of cross-coupled transistors to compensate for the loss in the LC resonator. The first and second SWOs utilize two O-shaped inductors to form a unit cell with capacitors. The third SWO utilizes an eight-shaped inductor and an orthogonal transformer to conserve the die area and suppress the magnetic coupling noise. The die area of the third oscillator is 0.986 × 0.756 mm². The SWO can generate differential signals in the frequency range of 8.3 GHz–9.3 GHz (10.83%), and its measured figure of merit (FOM) is −188.6 dBc/Hz at a 1 MHz offset frequency. Full article

This paper presents a co-design approach for a microwave amplifier–phase shifter that integrates an arbitrary termination impedance reflection-type phase shifter as the input matching network of a microwave transistor. Since the proposed reflection-type phase shifter input matching network is capable of transforming both real and/or complex impedances to a system impedance of 50 Ω, the co-design approach can directly match the optimum source impedance of the microwave transistor to 50 Ω through a reflection-type phase shifter input matching network. To validate the proposed method, prototypes of microwave amplifier–phase shifters with different input matching networks configurations are designed, fabricated, and measured with a center frequency of 2.45 GHz. The experimental results demonstrate that the proposed co-design microwave amplifier–phase shifter achieves improved electrical performances compared to the conventional approach, where a 50-to-50 Ω termination impedance phase shifter is cascaded with a 50-to-50 Ω termination impedance conventional microwave amplifier. Measurement results demonstrate that the gains of a standalone conventional microwave amplifier, a cascaded phase shifter with a conventional microwave amplifier, and the proposed co-design microwave amplifier–phase shifter are 14.13 dB, 13.28 dB, and 13.74 dB, while the 1 dB compression points are 25.72 dBm, 24.77 dBm, and 25.26 dBm, respectively. Within the 200 MHz bandwidth, the proposed co-design microwave amplifier–phase shifter exhibits a maximum phase shift range of 185.62° and a phase deviation error of ±4.3°. The circuit size of the co-designed microwave amplifier–phase shifter is 38.5% smaller than the conventional cascaded phase shifter with a conventional microwave amplifier. Full article

This paper proposes a dual-mode CMOS analog front-end (AFE) circuit for short-wave infrared (SWIR) image sensors, which integrates a hybrid readout circuit (ROIC) and a 12-bit two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC dynamically switches between buffered-direct-injection (BDI) and direct-injection (DI) modes, thus balancing injection efficiency against power consumption. While the DI structure offers simplicity and low power, it suffers from unstable biasing and reduced injection efficiency under high background currents. Conversely, the BDI structure enhances injection efficiency and bias stability via an input buffer but incurs higher power consumption. To address this trade-off, a dual-mode injection architecture with mode-switching transistors is implemented. Mode selection is executed in-pixel via a low-leakage transmission gate and coordinated by the column timing controller, enabling low-current pixels to operate in low-noise BDI mode, whereas high-current pixels revert to the low-power DI mode. The TS-SS ADC employs a four-terminal comparator and dynamic reference voltage compensation to mitigate charge leakage and offset, which improves signal-to-noise ratio (SNR) and linearity. The prototype occupies 2.1 mm × 2.88 mm in a 0.18 µm CMOS process and serves a 64 × 64 array. The AFE achieves a dynamic range of 75.58 dB, noise of 249.42 μV, and 81.04 mW power consumption. Full article

As semiconductor devices approach the sub-10 nm technology node, the self-heating effect (SHE) induced by confined geometries (e.g., FinFETs and nanosheet FETs) has emerged as a critical bottleneck affecting both performance and reliability. This challenge has prompted extensive research efforts to develop advanced characterization methodologies to investigate this effect and its corresponding influence on the device’s reliability issues. In this paper, we propose reflection-based ultra-fast measurement techniques for the continuous monitoring of the self-heating effect in advanced MOSFETs. With this approach, the self-heating effect-induced degradation of transistor drain current and the real-time temperature change can be continuously captured using a digital phosphor oscilloscope on a nanosecond scale. The thermal time constant of 17 ns and the thermal resistance of 34,000 K/W have been extracted for the short channel transistors used in this study with the help of this new characterization method. This reflection-based method is useful for the fast extraction of the thermal time constant and thermal resistance and for the continuous monitoring of current degradation as well as the real-time temperature. Therefore, this new characterization method is beneficial for the evaluation of the self-heating effect in advanced ultra-scaled MOSFETs. Full article

In space, high-energy particle radiation poses a serious threat to the data stability and reliability of SRAM. Existing radiation-tolerant techniques, such as Triple Modular Redundancy (TMR) and Error Correction Code (ECC), have disadvantages such as large area, high power consumption, and additional delay, making them unsuitable for small satellite systems. To overcome these limitations, this paper proposes a 16-transistor-based radiation-tolerant SRAM cell, WRTU-16T, which applies a read-decoupled structure and a charge-sharing suppression mechanism. The proposed structure effectively isolates the storage node from external disturbances and improves the recovery capability for single-event inversion (SEU) and multiple-node inversion (SEMNU) by reducing charge loss. WRTU-16T shows superior performance in terms of write delay, charge recovery capability (Qc), hold power, and word line write threshold voltage (WWTV) compared to existing radiation-tolerant SRAM designs. The integrated circuit is implemented using a 90 nm CMOS process and has an operating voltage of 1V. Full article