Search Results (96)

Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device characteristics, and, to study this effect, this work investigates the impact of RITs on the DC/AC/RF characteristic fluctuations of FinFETs. Under high gate bias, the device screening effect suppresses large fluctuations induced by RITs. In relation to different densities of interface traps (D_it), fluctuations of short-channel effects, including potential barriers and current densities, are analyzed. Bulk FinFETs exhibit entirely different variability, despite having the same number of RITs. Potential barriers are significantly altered when devices with RITs are located near the source end. An analysis and a discussion of RIT-fluctuated gate capacitances, transconductances, cut-off, and 3-dB frequencies are provided. Under high D_it conditions, we observe ~146% variation in off-state current, ~26% in threshold voltage, and large fluctuations of ~107% and ~131% in gain and cut-off frequency, respectively. The effects of the random position of RITs on both AC and RF characteristic fluctuations are also discussed and designed in three different scenarios. Across all densities of interface traps, the device with RITs near the drain end exhibits relatively minimal fluctuations in gate capacitance, voltage gain, cut-off, and 3-dB frequencies. Full article

In this study, AlGaN/GaN heterostructure field-effect transistors (HFETs) with an AlN cap layer and a GaN cap layer were fabricated. The devices were of different sizes. Capacitance–voltage (C-V) and current–voltage (I-V) curves were measured. Based on two-dimensional (2D) scattering theory, electron mobility corresponding to polarization Coulomb field (PCF) scattering and other primary scattering mechanisms was quantitatively determined. The influence of the AlN cap layer on PCF scattering in AlGaN/GaN HFETs was studied. It was found that the AlN cap layer suppresses the inverse piezoelectric effect (IPE) in the AlGaN barrier layer because of its greater polarization and larger Young’s modulus, thereby reducing the generation of additional polarization charge (APC) under the gate. In addition, the 2D electron gas (2DEG) density (n_2DEG) under the gate of the samples with an AlN cap layer is higher. Both factors help reduce PCF scattering intensity. Moreover, mobility analysis of samples with different gate–drain spacings (L_GD) showed that PCF scattering is less affected by L_GD variations in devices with AlN cap layers. This study offers new insights into the structural optimization of AlGaN/GaN HFETs. Full article

This study examines the performance of a GaN HEMT with a 150 nm gate length, fabricated on silicon carbide, across various operational modes, including direct current (DC), radio frequency (RF), and small-signal parameters. The evaluation of DC, RF, and small-signal performance under diverse bias conditions remains a relatively unexplored area of study for this specific technology. The DC characteristics revealed relatively little I_ds at zero gate and drain voltages, and the current grew as V_gs increased. Essential measurements include I_dss at 109 mA and I_dssm at 26 mA, while the peak g_m was 62 mS. Because transconductance is sensitive to variations in V_gs and V_ds, it shows “Vth _roll-off,” where Vth decreases as V_ds increases. The transfer characteristics corroborated this trend, illustrating the impact of drain-induced barrier lowering (DIBL) on threshold voltage (Vth) values, which spanned from −5.06 V to −5.71 V across varying drain-source voltages (V_ds). The equivalent-circuit technique revealed substantial non-linear behaviors in capacitances such as C_gs and C_gd concerning V_gs and V_ds, while also identifying extrinsic factors including parasitic capacitances and resistances. Series resistances (R_gs and R_gd) decreased as V_gs increased, thereby enhancing device conductivity. As V_gs approached neutrality, particularly at elevated V_ds levels, the intrinsic transconductance (g_mo) and time constants (τ_gm, τ_gs, and τ_gd) exhibited enhanced performance. f_t and f_max, which are essential for high-frequency applications, rose with decreasing V_gs and increasing V_ds. When V_gs approached −3 V, the S₂₁ and Y₂₁ readings demonstrated improved signal transmission, with peak S₂₁ values of approximately 11.2 dB. The stability factor (K), which increased with V_ds, highlighted the device’s operational limits. The robust correlation between simulation and experimental data validated the equivalent-circuit model, which is essential for enhancing design and creating RF circuits. Further examination of bias conditions would enhance understanding of the device’s performance. Full article

In this study, we propose a bidirectional chemical sensor platform based on a reconfigurable ion-sensitive field-effect transistor (R-ISFET) architecture. The device incorporates Ni-silicide Schottky barrier source/drain (S/D) contacts, enabling ambipolar conduction and bidirectional turn-on behavior for both p-type and n-type configurations. Channel polarity is dynamically controlled via the program gate (PG), while the control gate (CG) suppresses leakage current, enhancing operational stability and energy efficiency. A dual-control-gate (DCG) structure enhances capacitive coupling, enabling sensitivity beyond the Nernst limit without external amplification. The extended-gate (EG) architecture physically separates the transistor and sensing regions, improving durability and long-term reliability. Electrical characteristics were evaluated through transfer and output curves, and carrier transport mechanisms were analyzed using band diagrams. Sensor performance—including sensitivity, hysteresis, and drift—was assessed under various pH conditions and external noise up to 5 V_pp (i.e., peak-to-peak voltage). The n-type configuration exhibited high mobility and fast response, while the p-type configuration demonstrated excellent noise immunity and low drift. Both modes showed consistent sensitivity trends, confirming the feasibility of complementary sensing. These results indicate that the proposed R-ISFET sensor enables selective mode switching for high sensitivity and robust operation, offering strong potential for next-generation biosensing and chemical detection. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

In this study, a novel silicon carbide (SiC) double-trench MOSFET (DT-MOS) combined Schottky barrier diode (SBD) and MOS-channel diode (MCD) is proposed and investigated using TCAD simulations. The integrated MCD helps inactivate the parasitic body diode when the device is utilized as a freewheeling diode, eliminating bipolar degradation. The adjustment of SBD position provides an alternative path for reverse conduction and mitigates the electric field distribution near the bottom source trench region. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate the proposed structure with both SBD and MCD has advantages in switching and breakdown characteristics. Full article

A dual Al₂O₃ MIS gate structure is proposed to enhance the DC and RF performance of enhancement-mode GaN high-electron mobility transistors (HEMTs). As a result, the proposed MOS-HEMT with a dual recessed MIS gate structure offers 84% improvements in cutoff frequency (f_T) and 92% improvements in maximum oscillation frequency (f_max) compared to conventional HEMTs (from 7.1 GHz to 13.1 GHz and 17.5 GHz to 33.6 GHz, respectively). As for direct-current characteristics, a remarkable reduction in off-state gate leakage current and a 26% enhancement in the maximum saturation drain current (from 519 mA·mm⁻¹ to 658 A·mm⁻¹) are manifested in HEMTs with new structures. The maximum transconductance (g_m) is also raised from 209 mS·mm⁻¹ to 246 mS·mm⁻¹. Correspondingly, almost unchanged gate–source capacitance curves and gate–drain capacitance curves are also discussed to explain the electrical characteristic mechanism. These results indicate the superiority of using a dual Al₂O₃ MIS gate structure in GaN-based HEMTs to promote the RF and DC performance, providing a reference for further development in a miniwatt antenna amplifier and sub-6G frequencies of operation. Full article

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article

To address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure. In the off-state, the SGO structure effectively suppresses GIDL by reducing the electric field intensity at the channel/drain interface while simultaneously decreasing gate capacitance to reduce static power consumption. Based on an accurate device model, a systematic investigation was conducted into the effects of varying the thickness and length of the SGO structure on TFET performance, enabling the optimization of the SGO design. The simulation results demonstrate that, compared to normal MS TFETs, the SGO MS TFET reduces the off-state GIDL current ($I_{\mathrm{off}}$) from $4.6\times {10}^{-7}$ A to $2.6\times {10}^{-11}$ A, achieving a maximum improvement of 4.22 orders of magnitude in the on-state-to-off-state current ratio ($I_{\mathrm{on}}/I_{\mathrm{off}}$) and a 28% reduction in subthreshold swing (SS). Furthermore, compared to lightly doped drain (LDD) MS TFETs, the SGO MS TFET achieves a 32% reduction in total gate capacitance and a 23% enhancement in carrier mobility at the channel/drain interface. This study demonstrates that SGO provides an effective solution for GIDL suppression. Full article

Gel electrolyte-gated organic electrochemical transistors (OECTs) are promising bioelectronic devices known for their high transconductance, low operating voltage, and integration with biological systems. Despite extensive research on the performance of OECTs, a precise model defining the dependence of OECT performance on gel electrolytes is still lacking. In this work, we refine the device model to comprehensively account for the electrical double layer (EDL)’s capacitance of the gel electrolyte. Both experimental data and theoretical calculations indicate that the maximum transconductance of the OECT is contingent upon ion concentration, drain voltage, and scan rate, highlighting a strong correlation between the transconductance and the hydrogel electrolyte. Overall, this model serves as a theoretical tool for improving the performance of OECTs, enabling the further development of bioelectronic devices. Full article

Frequency-response analysis is critical in circuit design. Frequency response encodes crucial information, like gain, accuracy, bandwidth, response time, phase shift, stability, and more. Unfortunately, existing methods are either algebraic and obscure or approximations with inaccuracies. So applying them to more complex circuits is often arduous or unreliable. This paper proposes recursive shunt-circuit transformations: a simple, rigorous, and insightful analytical method for conceptualizing and designing electronic circuits. The method asserts that (a) each equivalent capacitance shunts away its parallel resistance past its RC frequency. This (b) decreases the gain (induces a pole) and (c) changes the circuit. (d) The next dominant capacitance shunts its parallel resistance past the next pole and so on until all remaining capacitances shunt their parallel resistances past the poles they establish. The method also asserts that (e) bypass capacitances increase gain (induce zeros) and (f) cross-amp capacitances couple stages and poles. By applying this method and concepts, designers can (i) simplify an arbitrarily complex circuit into simpler coupled/decoupled stages and (ii) determine and manage poles and zeros with insight. This method was applied to design and analyze single- and multi- stage amplifier circuits and results were benchmarked against traditional methods and NGSPICE simulations, demonstrating its accuracy and broad applicability. Full article

In this paper, a new label-free DNA nanosensor based on a top-gated (TG) metal–ferroelectric–metal (MFM) graphene nanoribbon field-effect transistor (TG-MFM GNRFET) is proposed through a simulation approach. The DNA sensing principle is founded on the dielectric modulation concept. The computational method employed to evaluate the proposed nanobiosensor relies on the coupled solutions of a rigorous quantum simulation with the Landau–Khalatnikov equation, considering ballistic transport conditions. The investigation analyzes the effects of DNA molecules on nanodevice behavior, encompassing potential distribution, ferroelectric-induced gate voltage amplification, transfer characteristics, subthreshold swing, and current ratio. It has been observed that the feature of ferroelectric-induced gate voltage amplification using the integrated MFM structure can significantly enhance the biosensor’s sensitivity to DNA molecules, whether in terms of threshold voltage shift or drain current variation. Additionally, we propose the current ratio as a sensing metric due to its ability to consider all DNA-induced modulations of electrical parameters, specifically the increase in on-state current and the decrease in off-state current and subthreshold swing. The obtained results indicate that the proposed negative-capacitance GNRFET-based DNA nanosensor could be considered an intriguing option for advanced point-of-care testing. Full article

This study proposes an AlGaN/GaN current aperture vertical electron transistor (CAVET) featuring a double superjunction (SJ) to enhance breakdown voltage (BV) and investigates its electrical characteristics via technology computer-aided design (TCAD) Silvaco Atlas simulation. An additional p-pillar was formed beneath the gate current blocking layer to create a lateral depletion region that provided a high off-state breakdown voltage. To address the tradeoff between the drain current and off-state breakdown voltage, the key design parameters were carefully optimized. The proposed device exhibited a higher off-state breakdown voltage (2933 V) than the device with a single SJ (2786 V), although the specific on-resistance of the proposed method (1.29 mΩ·cm⁻²) was slightly higher than that of the single SJ device (1.17 mΩ·cm⁻²). In addition, the reverse transfer capacitance was improved by 15.6% in the proposed device. Full article

A silicon carbide (SiC) SGT MOSFET featuring a “一”-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts. One is to optimize the electric field distribution of the device, and the other is to expand the current conduction path. Based on the improved PSR and grounded split gate (SG), the device remarkably improves the conduction characteristics, gate oxide reliability, and frequency response. Moreover, the integrated sidewall Schottky barrier diode (SBD) prevents the inherent body diode from being activated and improves the reverse recovery characteristics. As a result, the gate-drain capacitance, gate charge, and reverse recovery charge (Q_rr) of the SPDT-MOS are 81.2%, 41.2%, and 90.71% lower than those of the DTMOS, respectively. Compared to the double shielding (DS-MOS), the SPDT-MOS exhibits a 20% reduction in on-resistance and an 8.1% increase in breakdown voltage. Full article

Various high-k dielectrics have been proposed for AlGaN/GaN MOSHEMTs for gate leakage and drain-current collapse suppression. Hafnium oxide (HfO₂) is particularly interesting because of its large bandgap, high dielectric constant, and ferroelectricity under specific phase and doping conditions. However, defects and surface scattering caused by HfO₂ dissimilarity and degraded HfO₂/GaN interface quality still leave the challenge of reducing the SS and R_on. In this study, we investigated the effects of the first spike-annealed HfO₂ (6 nm) layer, compared with the conventional ALD-HfO₂ (6 nm) layer in the HfO₂ bilayer gate dielectric structure on AlGaN/GaN HEMTs. Both devices exhibit negligible hysteresis and near-ideal (~60 mV/dec) subthreshold slopes of more than three orders of magnitude. The device with the first annealed HfO₂ layer exhibited a reduced R_on with notably less gate bias dependency and enhanced output current. On the other hand, the capacitance–voltage and conductance methods revealed that the border and interface trap densities of the device were inferior to those of the conventional HfO₂ layer. The trade-off between enhanced electrical performance and oxide traps is discussed based on these results. Full article