Advanced Nano-Semiconductor Devices: Design, Modeling and Next-Generation AI Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 20 December 2025 | Viewed by 108

Special Issue Editor

State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: nano-MOSFET; tunnel field effect transistors; junctionless field effect transistors; CIS pixels; ROIC for sensors; PLL/ADC

Special Issue Information

Dear Colleagues,

Advanced nano-semiconductor devices play a crucial role in cutting-edge fields such as quantum computing, the Internet of Things, and next-generation artificial intelligence (AI). As the size of features on chips approaches 5 nanometers and smaller, traditional silicon-based devices are gradually reaching the ceiling of their physical performance. This predicament, instead, has become a catalyst for technological innovation, spurring the explosive development of novel device architectures and technologies for regulating quantum effects.

This Special Issue is open to scientific researchers around the world. We invite you to share the latest achievements in the areas of the design, modeling, and application of advanced nano-semiconductor devices. We look forward to presenting the wisdom of the academic community and jointly exploring the technological frontiers.

Dr. Bin Wang
Guest Editor

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Keywords

  • nano-semiconductor devices
  • modeling and simulation
  • reliability design
  • novel concepts for device structure design
  • quantum effects and quantum devices
  • IoT and AI applications

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Published Papers (1 paper)

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Research

11 pages, 1195 KiB  
Article
The Impact of Single-Event Radiation on Latch-Up Effect in High-Temperature CMOS Devices and Its Mechanism
by Bin Wang, Jianguo Cui, Ling Lv and Longsheng Wu
Micromachines 2025, 16(7), 783; https://doi.org/10.3390/mi16070783 (registering DOI) - 30 Jun 2025
Abstract
This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect [...] Read more.
This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm2/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm2/mg at 300 K, dropping to 6 MeV cm2/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 104 A/μm at 300 K to 4.65 × 10−5 A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K. Full article
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