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Micromachines
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Advanced Nano-Semiconductor Devices: Design, Modeling and Next-Generation AI Applications
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Advanced Nano-Semiconductor Devices: Design, Modeling and Next-Generation AI Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 20 December 2025 | Viewed by 2531

Special Issue Editor

Dr. Bin Wang

E-Mail Website
Guest Editor
State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: nano-MOSFET; tunnel field effect transistors; junctionless field effect transistors; CIS pixels; ROIC for sensors; PLL/ADC

Special Issue Information

Dear Colleagues,

Advanced nano-semiconductor devices play a crucial role in cutting-edge fields such as quantum computing, the Internet of Things, and next-generation artificial intelligence (AI). As the size of features on chips approaches 5 nanometers and smaller, traditional silicon-based devices are gradually reaching the ceiling of their physical performance. This predicament, instead, has become a catalyst for technological innovation, spurring the explosive development of novel device architectures and technologies for regulating quantum effects.

This Special Issue is open to scientific researchers around the world. We invite you to share the latest achievements in the areas of the design, modeling, and application of advanced nano-semiconductor devices. We look forward to presenting the wisdom of the academic community and jointly exploring the technological frontiers.

Dr. Bin Wang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • nano-semiconductor devices
  • modeling and simulation
  • reliability design
  • novel concepts for device structure design
  • quantum effects and quantum devices
  • IoT and AI applications

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Published Papers (3 papers)

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Research

16 pages, 3651 KB  
Article
Investigation on High-Temperature and High-Field Reliability of NMOS Devices Fabricated Using 28 nm Technology After Heavy-Ion Irradiation
by Yanrong Cao, Zhixian Zhang, Longtao Zhang, Miaofen Li, Shuo Su, Weiwei Zhang, Youli Xu, Dingqi Huang, Le Liu, Ling Lv and Xiaohua Ma
Micromachines 2025, 16(11), 1216; https://doi.org/10.3390/mi16111216 - 25 Oct 2025
Viewed by 479
Abstract
This paper investigates the degradation of 28 nm technology NMOS devices under high-temperature and high-field conditions following heavy-ion irradiation. The effects of stress time, stress magnitude, temperature, device structural dimensions, and heavy-ion radiation fluence on device degradation were analyzed. The results indicate that [...] Read more.
This paper investigates the degradation of 28 nm technology NMOS devices under high-temperature and high-field conditions following heavy-ion irradiation. The effects of stress time, stress magnitude, temperature, device structural dimensions, and heavy-ion radiation fluence on device degradation were analyzed. The results indicate that under positive gate bias stress, the threshold voltage of NMOS devices exhibits a continuous positive shift. Increased stress time, higher stress magnitude, elevated temperature, and reduced device structural dimensions all aggravate device degradation. The combined effects of electrical stress and radiation lead to a degradation that initially decreases and then increases. This is because the trap charges generated in the gate oxide layer by radiation are positive charges at low fluence, compensating for the negative charges generated under electrical stress, thereby reducing degradation. However, at high fluence, the negative interface trap charges increase, while radiation also generates positive charges in the shallow trench isolation (STI) region. These two factors collectively contribute to increased device degradation. Full article
(This article belongs to the Special Issue Advanced Nano-Semiconductor Devices: Design, Modeling and Next-Generation AI Applications)
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12 pages, 1760 KB  
Article
Effect of AlN Cap Layer on Polarization Coulomb Field Scattering in AlGaN/GaN Heterostructure Field Effect Transistor
by Qianding Cheng, Ming Yang, Zhiliang Gao, Ruojue Wang, Jihao He, Feng Yan, Xu Tang, Weihong Zhang, Zijun Hu and Jingguo Mu
Micromachines 2025, 16(10), 1093; https://doi.org/10.3390/mi16101093 - 26 Sep 2025
Viewed by 371
Abstract
In this study, AlGaN/GaN heterostructure field-effect transistors (HFETs) with an AlN cap layer and a GaN cap layer were fabricated. The devices were of different sizes. Capacitance–voltage (C-V) and current–voltage (I-V) curves were measured. Based on two-dimensional (2D) scattering [...] Read more.
In this study, AlGaN/GaN heterostructure field-effect transistors (HFETs) with an AlN cap layer and a GaN cap layer were fabricated. The devices were of different sizes. Capacitance–voltage (C-V) and current–voltage (I-V) curves were measured. Based on two-dimensional (2D) scattering theory, electron mobility corresponding to polarization Coulomb field (PCF) scattering and other primary scattering mechanisms was quantitatively determined. The influence of the AlN cap layer on PCF scattering in AlGaN/GaN HFETs was studied. It was found that the AlN cap layer suppresses the inverse piezoelectric effect (IPE) in the AlGaN barrier layer because of its greater polarization and larger Young’s modulus, thereby reducing the generation of additional polarization charge (APC) under the gate. In addition, the 2D electron gas (2DEG) density (n2DEG) under the gate of the samples with an AlN cap layer is higher. Both factors help reduce PCF scattering intensity. Moreover, mobility analysis of samples with different gate–drain spacings (LGD) showed that PCF scattering is less affected by LGD variations in devices with AlN cap layers. This study offers new insights into the structural optimization of AlGaN/GaN HFETs. Full article
(This article belongs to the Special Issue Advanced Nano-Semiconductor Devices: Design, Modeling and Next-Generation AI Applications)
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10 pages, 7781 KB  
Article
The Impact of Single-Event Radiation on Latch-Up Effect in High-Temperature CMOS Devices and Its Mechanism
by Bin Wang, Jianguo Cui, Ling Lv and Longsheng Wu
Micromachines 2025, 16(7), 783; https://doi.org/10.3390/mi16070783 - 30 Jun 2025
Viewed by 1347
Abstract
This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect [...] Read more.
This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm2/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm2/mg at 300 K, dropping to 6 MeV cm2/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 10−4 A/μm at 300 K to 4.65 × 10−5 A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K. Full article
(This article belongs to the Special Issue Advanced Nano-Semiconductor Devices: Design, Modeling and Next-Generation AI Applications)
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