Search Results (154)

The interfacial adhesion strength of fine lines for flip-chip ball grid array (FCBGA) substrates is highly dependent on the surface desmear process during substrate manufacturing. However, the extremely narrow window for optimal desmear processes limits the improvement of the adhesion strength of fine lines. Herein, a polydopamine-modified epoxy build-up film substrate was fabricated to increase chemical bonding action and broaden the process window. The chemical structure, surface roughness, morphology, surface chemical state, and adhesion strength of the modified substrate were characterized. The results showed that the adhesion strength of the substrates increased from 2.2 N/cm to 4.1 N/cm under suboptimal process conditions. Meanwhile, the effect of the polydopamine deposition time on the adhesion strength of the copper-deposited epoxy resin composite films at the interfaces was systematically investigated; furthermore, the mechanisms and reasons for the increased adhesion strength and interfacial adhesion failure for the copper-deposited epoxy resin composite build-up film substrates were revealed. This work will provide guidance in both theory and experiment to enhance the interfacial adhesion force for advanced substrates in the future. Full article

Total internal reflection (TIR) loss is a critical bottleneck limiting light extraction in AlGaN-based deep-ultraviolet (DUV) light-emitting diodes (LEDs), primarily due to the large refractive-index contrast at the light-emitting interface. Here, pyramid-shaped dielectric metasurfaces are designed and fabricated at the sapphire/air interface of flip-chip AlGaN-based DUV LEDs using a scalable nanoimprinting process. The metasurface functions as a light outcoupling layer that modifies the interfacial momentum-matching condition and redistributes photon propagation directions. Experimental results and theoretical simulations show that metasurfaces with different feature sizes enhance light extraction through distinct mechanisms. The subwavelength pyramid nanoarray perturbs the local optical field and provides additional in-plane momentum components, facilitating the coupling of high-angle photons into radiative channels, whereas the larger pyramid void structure mainly promotes photon extraction through geometrical redirection, tilted output interfaces, and dry-etching-induced rough surface scattering. As a result, an average light output power (LOP) enhancement of over 8% is achieved for AlGaN-based DUV LEDs emitting at approximately 275 nm. This work demonstrates a low-cost, scalable, and effective strategy for enhancing the LEE of DUV LEDs, with promising potential for high-efficiency ultraviolet optoelectronic application. Full article

This paper presents a flipped-voltage-follower low-dropout regulator (FVF-LDO) for power supply rejection enhancement and low-power operation in CMOS transimpedance amplifiers for optical receiver applications. The proposed FVF-LDO ensures high stability and reliable regulation over a wide range of load conditions by employing a flipped-voltage follower for fast local feedback and improved power supply rejection, while a super-source follower enhances the transient response through increased current-driving capability. A bandgap reference with a 3-bit trimming DAC is adopted to compensate process variations and support stable LDO operations, achieving a temperature coefficient of 19.6 ppm/°C over a wide range of −25 °C to 125 °C. The FVF-LDO exhibits a 101 mV undershoot under a 100 µA-to-10 mA load step with a 100 ns edge time. When applied to an optoelectronic inverter-based active-feedback transimpedance amplifier (TIA), the regulated supply improves the power supply rejection ratio (PSRR) from −6 dB to −38.3 dB. The proposed optoelectronic TIA realized in a 180 nm CMOS process achieves 67 dBΩ transimpedance gain, 869 MHz bandwidth, 66 dB dynamic range, 6.68 pA/√Hz input-referred noise current spectral density, and 4.68 mW power consumption from a single 1.8 V supply. The proposed TIA chip occupies a core area of 940 × 162 µm². Full article

This paper presents a hardware-efficient field-programmable gate array (FPGA) implementation of a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes in very small aperture terminal (VSAT) satellite communication systems. The decoder is described in C++ and synthesized using the Xilinx Vitis high-level synthesis (HLS) 2025 (AMD Xilinx, San Jose, CA, USA) tool, and then packaged and integrated as an intellectual property (IP) core within the Vivado Design Suite 2024 (AMD Xilinx, San Jose, CA, USA), enabling rapid prototyping and portability across FPGA platforms. Unlike conventional normalized min-sum (NMS) and two-dimensional normalized min-sum (2D-NMS) architectures, the proposed 2D-CNMS scheme employs dyadic, multiplier-free normalization combined with two-level magnitude correction, achieving near sum-product performance with reduced complexity and latency. The design is implemented on a Zynq UltraScale+ multiprocessor system-on-chip (MPSoC) (AMD Xilinx, San Jose, CA, USA) and supports real-time operation with a throughput of 29–41 Mbps at 100 MHz, while using only 9.6–22.4 k look-up tables (LUTs), 2.1–5.9 k flip-flops (FFs), and no digital signal processing (DSP) slices or block random-access memories (BRAMs). Bit-error-rate (BER) simulations over an additive white Gaussian noise (AWGN) channel show no error floor down to ${10}^{-8}$. These results demonstrate that the proposed HLS-based 2D-CNMS IP core provides a resource-efficient, high-performance LDPC decoding solution as compared with existing LDPC implementation approaches. This LDPC solution targets performance enhancement in wireless communication systems and has been deployed on a multi-frequency time-division multiple-access (MF-TDMA) satellite link to assess its overall behavior, demonstrating improved performance with reduced resource usage. Full article

Edge detection is a key building block in real-time image-processing applications such as drone-based infrastructure inspection, autonomous navigation, and remote sensing. However, its computational cost remains a challenge for resource-constrained embedded systems. This work presents a hardware-accelerated edge detection architecture based on a homogeneous 2D-mesh Network-on-Chip (NoC) integrating systolic arrays to efficiently perform the convolution operations required by the Sobel filter. The proposed architecture was first developed and validated as a 3 × 3 mesh prototype on FPGA (Xilinx Zynq-7000, Zynq-7010, XC7Z010-CLG400A, Zybo board, utilizing 26,112 LUTs, 24,851 flip-flops, and 162 DSP blocks), achieving a throughput of 8.8 Gb/s with a power consumption of 0.79 W at 100 MHz. Building upon this validated prototype, a reduced 2 × 2 node cluster with 14-bit word width was subsequently synthesized at the physical level as a proof-of-concept using the OpenLane RTL-to-GDSII open-source flow targeting the SkyWater 130 nm PDK (sky130A). Post-layout analysis confirms the manufacturability of the design, with a total power consumption of 378 mW and compliance with timing constraints, demonstrating the feasibility of mapping the proposed architecture to silicon and its suitability for drone-based infrastructure monitoring applications. Full article

The need for unpredictable sequences of bits is common in many important security applications. These sequences can only be generated by true random number generators (TRNGs). Apart from the natural analog domain for TRNGs, this type of generator is also required as a digital-based solution, particularly leveraging field-programmable gate array (FPGA) platforms. Despite the number of existing FPGA-based implementations, new solutions that use different types of entropy sources, utilize fewer FPGA resources, or ensure higher throughput are still being sought. This paper presents an architecture of a simple TRNG targeted for implementation in FPGAs. As a source of entropy, the TRNG exploits jitter in capacitive oscillators and metastability in flip-flops. The capacitive oscillators, in turn, use the input–output cells of an FPGA chip and unconnected external pins and cyclically charge and discharge the parasitic capacitance associated with these pins. The TRNG needs a small number of FPGA resources, namely 13 look-up tables (LUTs), 12 flip-flops, and 3 unused pins. Its throughput is approximately 12.5 Mbit/s for AMD/Xilinx Artix-7 FPGA family chips. The presented TRNG passes all the NIST statistical tests for a wide range of operating conditions. Full article

You Only Look Once (YOLO) is a convolutional neural network-based object detection algorithm widely used in real-time vision applications. However, its high computational demand leads to significant power consumption and cost when deployed in graphics processing units. Field-programmable gate arrays offer a low-power alternative. However, their efficient implementation requires architecture-level optimization tailored to limited device resources. This study presents an optimized YOLOv2 accelerator for the Zynq-7000 system-on-chip (SoC). The design employs 16-bit integer quantization, a filter reuse structure, an input feature map reuse scheme using a line buffer, and tiling parameter optimization for the convolution and max pooling layers to maximize resource efficiency. In addition, a stall-based control mechanism is introduced to prevent structural hazards in the pipeline. The proposed accelerator was implemented on the Zynq-7000 SoC board, and a system-level evaluation confirmed a negligible accuracy drop of only 0.2% compared with the 32-bit floating-point baseline. Compared with previous YOLO accelerators on the same SoC, the design achieved up to 26% and 15% reductions in flip-flop and digital signal processor usage, respectively. This result demonstrates feasible deployment on XC7Z020 with DSP 57.27% and FF 16.55% utilization. Full article

Random number generators play a critical role in ensuring information security, supporting encrypted communications, and preventing data leakage. However, the random number generators widely used in hardware are faced with potential threats such as environmental disturbances and fault injection attacks. Especially in automotive-grade environments, chips encounter threat scenarios involving multidimensional fault injection, which may lead to functional failures or malicious exploitation, endangering the security of the entire system. This paper focuses on a Counter Mode Deterministic Random Bit Generator (CTR-DRBG) based on the AES-128 algorithm and implements a hardware prototype system compliant with the NIST SP 800-22 standard on an FPGA platform. Centering on typical fault modes such as temperature disturbances, voltage glitches, electromagnetic interference, and bit flips, single-dimensional and multidimensional fault injection and simulated fault injection experiments were designed and conducted. The impact characteristics and sensitivities of electromagnetic faults, voltage faults, and temperature faults regarding the output sequences of random numbers were systematically evaluated. The experimental results show that this type of random number generator exhibits modular-level differential vulnerability under physical disturbances, especially in the data transmission processes of encryption paths and critical registers, which demonstrate higher sensitivity to flip-type faults. This research provides a feasible analysis framework and practical basis for the security assessment and fault-tolerant design of random number generators, possessing certain engineering applicability and theoretical reference value. Full article

Here, we introduce a novel method for the real-time spatial monitoring of I/O interconnection nets in flip-flop packages. Resistance changes in 39 I/O nets are observed simultaneously to produce a spatial profile of the relative degradations of the solder ball joints, interconnection lines, and transistor gates. Location-specific TTF profiles are generated from the degradation data to show the impact of the I/O nets in the context of their placement on the chip. The system succeeds in formulating a clear trend of resistance increase even in relatively mild constant temperature stress conditions. Test results of four temperatures from 80 °C to 120 °C show a dominant degradation pattern strongly influenced by BTI aging demonstrating an acute vulnerability in the pass gates to voltage and temperature stress. The proposed compact spatial monitor solution can be integrated into virtually all chip orientations. The outcome of this study can assist in foreseeing system vulnerabilities in a large spectrum of packaging and advanced packaging orientations in field applications. Full article

The increasing integration and miniaturization of electronic devices place serious pressure on packaging technologies to ensure long-term reliability. Polymer underfill encapsulation is a key process for reducing thermomechanical stress in modern assemblies. A systematic analysis that frames its diverse methods as solutions to the fundamental trade-off between the final polymer composite’s thermomechanical performance and its liquid-state processability is lacking from the literature. The novelty of this review lies in establishing a decision-making framework that connects specific application requirements to the underlying material science and process limitations. This article analyzes and compares different underfill techniques through a systematic literature review, from conventional capillary flow to advanced wafer-level underfills. Our findings show that this core trade-off leads to three distinct strategies: (1) Maximum reliability: This is achieved with highly filled, post-applied composites, offering excellent thermomechanical properties at the cost of slow, viscosity-driven manufacturing speeds. (2) High productivity: This is realized through integrated, pre-applied processes that simplify manufacturing but impose significant constraints on the polymer chemistry and filler content. (3) Targeted reinforcement for board-level packages: At the localized positions applied, ductile polymers often enhance mechanical shock resistance. This review concludes that the optimal underfill choice is not universal but is a complex, application-driven decision balancing the cured material’s performance against the processing demands of the polymer system. Full article

We propose a hybrid-integrated III–V-silicon optical-phased-array (OPA) based on passive alignment flip–chip bonding technology and provide new solutions for LiDAR. To achieve a large range of vertical beam steering in a hybrid-integrated OPA, a multi-lines OPA in a single chip is introduced. The system allows parallel hybrid integration of multiple dies onto a single wafer, achieving a multi-fold improvement in tuning efficiency. In order to increase the range of horizontal beam steering, we propose a half-wavelength pitch waveguide emitter with non-uniform width to reduce the crosstalk, which can remove the higher-order grating lobes in free space. In this work, we simulate OPA individually for four-lines and eight-lines. As a result, we simultaneously achieved a beam steering with nearly ±90° (horizontal) × 17.2° (vertical, when four-line OPA) or 39.6° (vertical, when eight-line OPA) field of view (FOV) and a high tuning efficiency with 1.13°/nm (when eight-line OPA). Full article

The GaN-based green miniaturized light-emitting diode (mini-LED) is a key component for the realization of full-color display. Optimized passivation layers can alleviate the trapping of carriers by sidewall defects and are regarded as an effective way to improve the external quantum efficiency (EQE) efficiency of mini-LEDs. Since AlN has a closer lattice match to GaN compared to other heterogeneous passivation materials, we boosted the EQE of GaN-based green flip-chip mini-LEDs through the deposition of a lattice-compatible AlN passivation layer through atomic layer deposition (ALD) and a SiO₂ passivation layer through plasma-enhanced chemical vapor deposition (PECVD). Benefiting from reduced sidewall nonradiative recombination, the EQE of the green flip-chip mini-LED with a composite ALD-AlN/PECVD-SiO₂ passivation layer reached 34.14% at 5 mA, which is 34.6% higher than that of the green flip-chip mini-LED with a single PECVD-SiO₂ passivation layer. The results provide guidance for the realization of high-performance mini-LEDs by selecting lattice-compatible passivation layers. Full article

Compared to the traditional flip-chip bonded focal plane array, in high-density vertically integrated photodiode (HDVIP) focal plane technology, the thickness of the mercury cadmium telluride (MCT or Hg_1−xCd_xTe) layer serves as a more critical parameter. This parameter not only influences the efficiency of photon energy absorption but also defines the pn junction area, thereby affecting the magnitude of the dark current. Furthermore, it significantly impacts the manufacturability of via-hole etching and formation processes. This paper investigated the photonic crystal resonances and coherent perfect absorption (CPA) effect of a thin MCT layer in HDVIP by using COMSOL Multiphysics^® 4.3b and optimized the structure of the loop-hole photodiode device. The CPA, which is formed by this structure, achieves high absorption of illumination in a very thin MCT film. It is demonstrated that an absorption rate of infrared radiation of more than 95% with a wavelength during the 8 µm–10 µm range can be achieved in Hg_1−xCd_xTe (x = 0.225) with a thickness of only 1.5 µm–3 µm. The benefit of thinner MCT film is that it decreases the dark current of pn junction and reduces the technical difficulty of etching and metallization of the loop-hole photodiode. Full article

Compact, broadband, multi-channel RF chips with low loss and high integration are required for high-performance phased-array systems. Presented in this paper is a four-channel, multifunction RF chip operating in the 5–18 GHz frequency range that integrates broadband phase shifting, amplitude control, power amplification, and switching functions. The chip is designed to have flip-chip bonding and stacked gold bumps to enable the compact 3D integration of the GaAs pHEMT and Si-CMOS. To ensure high-density interconnects with minimal parasitic effects, a fan-in redistribution process is implemented. The RF front-end part of this chip, fabricated through a 0.15 µm GaAs pHEMT process, integrates 6-bit digital phase shifters, 6-bit digital attenuators, low-noise amplifiers (LNAs), power amplifiers (PAs), and single-pole double-throw (SPDT) switches. To enhance multi-channel isolation and reduce crosstalk between RF chips and digital circuits, high isolation techniques, including a ground-coupled shield layer in the fan-in process and on-chip shield cavities, are utilized, which achieve isolation levels greater than 41 dB between adjacent RF channels. The measurement results demonstrate a reception gain of 0 dB with ±0.6 dB flatness, an NF below 11 dB, and transmit gain of more than 10 dB, with a VSWR of below 1.6 over the entire 5–18 GHz frequency band. The 6-bit phase shifter achieves a root mean square (RMS) phase error below 2.5° with an amplitude variation of less than 0.8 dB, while the 6-bit attenuator exhibits an RMS attenuation error of below 0.5 dB and a phase variation of less than 7°. The RF and digital chips are heterogeneously integrated using flip-chip and fan-in technology, resulting in a compact chip size of 6.2 × 6.2 × 0.33 mm³. These results validate that this is a compact, high-performance solution for advanced phased-array radar applications. Full article

Artificial retinal devices require a high-density electrode array and mechanical flexibility to effectively stimulate retinal cells. However, designing such devices presents significant challenges, including the need to conform to the curvature of the eyeball and cover a large area using a single platform. To address these issues, we developed a parylene-based multi-module retinal device (MMRD) integrating a complementary metal-oxide semiconductor (CMOS) system. The proposed device is designed for suprachoroidal transretinal stimulation, with each module comprising a parylene-C thin-film substrate, a CMOS chip, and a ceramic substrate housing seven platinum electrodes. The smart CMOS system significantly reduces wiring complexity, enhancing the device’s practicality. To improve fabrication reliability, we optimized the encapsulation process, introduced multiple silane coupling modifications, and utilized polyvinyl alcohol (PVA) for easier detachment in flip-chip bonding. This study demonstrates the fabrication and evaluation of the MMRD through in vitro and in vivo experiments. The device successfully generated the expected current stimulation waveforms in both settings, highlighting its potential as a promising candidate for future artificial vision applications. Full article