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Electronics
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Safeguarding Systems: Approaches to Resolving Hardware Security Challenges
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Safeguarding Systems: Approaches to Resolving Hardware Security Challenges

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 15 July 2025 | Viewed by 1856

Special Issue Editors

Dr. Jiaji He

E-Mail Website
Guest Editor
School of Microelectronics, Tianjin University, Tianjin 300072, China
Interests: hardware security; side-channel security; formal verification
Special Issues, Collections and Topics in MDPI journals
Dr. Pengfei Qiu

E-Mail Website
Guest Editor
Key Laboratory of Trustworthy Distributed Computing and Service, Beijing University of Posts and Telecommunications (BUPT), Ministry of Education, Beijing 100876, China
Interests: hardware security; hardware vulnerability mining; physical unclonable function; secure architecture design
Special Issues, Collections and Topics in MDPI journals
Dr. Yijun Cui

E-Mail Website
Guest Editor
College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics, Nanjing 211106, China
Interests: hardware security; post-quantum cryptographic

Special Issue Information

Dear Colleagues,

Hardware security focuses on research related to integrated circuits and corresponding hardware with physical and logical threats. There exist common security challenges, including physical attacks, supply chain vulnerabilities, firmware flaws, architecture imperfections, etc. There are still emerging security and privacy threats, e.g., blockchain security, cryptocurrency security, privacy-enhancing architecture, etc. This Special Issue aims to facilitate the rapid growth of hardware security research and development and also focuses on academic and industrial research on all topics related to hardware security and trust. Topics of interest to this Special Issue include, but are not limited to, the following:

  • Security analysis engines;
  • Security-aware CAD tools;
  • VLSI verification for security and trust;
  • Automatic side-channel vulnerability assessment;
  • Security equivalence checking;
  • Formal method-based security verification;
  • Automatic hardware vulnerability mining method;
  • New hardware vulnerability or attack;
  • Hardware-assisted computer security;
  • Secure hardware design;
  • AI-based hardware security analysis.

Dr. Jiaji He
Dr. Pengfei Qiu
Dr. Yijun Cui
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • hardware security
  • security verification
  • security analysis

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Published Papers (2 papers)

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Research

18 pages, 8795 KiB  
Article
A Weak-PUF-Assisted Strong PUF with Inherent Security Using Metastability Implemented on FPGAs
by Jiaji He, Guoqian Song, Qizhi Zhang, Xiaoxiang Wang, Yanjiang Liu, Yao Li, Mao Ye and Yiqiang Zhao
Electronics 2025, 14(5), 1007; https://doi.org/10.3390/electronics14051007 - 2 Mar 2025
Viewed by 674
Abstract
Physical unclonable functions (PUFs) are emerging as highly promising lightweight hardware security primitives that offer novel information security solutions. PUFs capitalize on the intrinsic physical variations within circuits to generate unpredictable responses. Nevertheless, diverse PUF types often encounter difficulties in concurrently fulfilling multiple [...] Read more.
Physical unclonable functions (PUFs) are emerging as highly promising lightweight hardware security primitives that offer novel information security solutions. PUFs capitalize on the intrinsic physical variations within circuits to generate unpredictable responses. Nevertheless, diverse PUF types often encounter difficulties in concurrently fulfilling multiple performance requisites. As is well known, strong PUFs possess significantly larger challenge–response pair (CRP) set sizes. However, they are vulnerable to machine learning (ML) attacks. Conversely, weak PUFs generate responses with superior randomness, yet their CRP sets are inadequate to satisfy the demands of practical applications. This paper presents a newly devised double-latch PUF (DL-PUF) to address this issue. This design significantly enhances both the CRP set size and security performance. The available CRPs of the DL-PUF design can reach up to 264, and its robust security features are also demonstrated in this paper. We have implemented this design on twelve 45 nm Xilinx Spartan 6 XC6SLX25 FPGAs. The experimental results indicate that our proposed DL-PUF performs well in terms of reliability, uniqueness, uniformity, and randomness. Additionally, three machine learning algorithms were employed to conduct comprehensive tests on the DL-PUF. The results reveal its excellent resilience against machine learning attacks. Full article
(This article belongs to the Special Issue Safeguarding Systems: Approaches to Resolving Hardware Security Challenges)
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27 pages, 1081 KiB  
Article
ConBOOM: A Configurable CPU Microarchitecture for Speculative Covert Channel Mitigation
by Zhewen Zhang, Yao Liu, Yuhan She, Abdurrashid Ibrahim Sanka, Patrick S. Y. Hung and Ray C. C. Cheung
Electronics 2025, 14(5), 850; https://doi.org/10.3390/electronics14050850 - 21 Feb 2025
Viewed by 958
Abstract
Speculative execution attacks are serious security problems that cause information leakage in computer systems by building speculative covert channels. Hardware defenses mitigate speculative covert channels through microarchitectural changes. However, two main limitations become the major bottleneck in existing hardware defenses. High-security hardware defenses, [...] Read more.
Speculative execution attacks are serious security problems that cause information leakage in computer systems by building speculative covert channels. Hardware defenses mitigate speculative covert channels through microarchitectural changes. However, two main limitations become the major bottleneck in existing hardware defenses. High-security hardware defenses, such as eager delay, can effectively mitigate both known and unknown covert channels. However, these defenses incur high performance overhead due to the long-fixed delayed execution applied in all potential attack scenarios. In contrast, hardware defenses with low performance overhead are faster and can mitigate known covert channels, but lack sufficient security to mitigate unknown covert channels. The limitations indicate that it is difficult to achieve better security and performance of a processor against speculative execution attacks using a single defense method. In this paper, we propose ConBOOM, a configurable central processing unit (CPU) microarchitecture that provides optimized switchable hardware defensive modes, including the high-security eager delay mode and two proposed performance-optimized modes based on the anticipated attack scenarios. The defensive modes allow for flexibility in mitigating different speculative execution attacks with better performance, unlike the existing defenses having fixed performance overhead for all attack scenarios. The ConBOOM modes can be switched without modifying the hardware, and switching ConBOOM to the suitable mode for the anticipated attack scenario is achieved through the provided software configuration interface. We implemented ConBOOM on Berkeley’s RISC-V out-of-order processor core (SonicBOOM). Furthermore, we evaluated ConBOOM on the VCU118 FPGA platform. Compared to the existing representative work with the fixed performance overhead of 39.1%, ConBOOM has the lower performance overhead ranging between 15.1% and 39.1% to mitigate different attack scenarios. ConBOOM provides more defensive flexibility with negligible hardware resource overhead about 2.0% and good security. Full article
(This article belongs to the Special Issue Safeguarding Systems: Approaches to Resolving Hardware Security Challenges)
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