Search Results (138)

This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions. Full article

High-flow nasal cannula (HFNC) therapy is frequently described as a positive pressure modality, yet this classification lacks mechanistic support. This critical narrative review integrates experimental, computational, and clinical evidence to examine the established physiological mechanisms underlying HFNC, with emphasis on precise terminology. The study clarifies that labeling HFNC as “positive pressure” is conceptually inaccurate, as the system delivers transient, flow-dependent pressures characteristic of open-circuit administration. Evidence is synthesized to quantify the relative contributions of nasopharyngeal dead-space clearance versus emergent pressure generation. Unlike CPAP, HFNC produces pressures ranging from 0.2 to 13.5 cmH₂O, determined by airway geometry, leak magnitude, and mouth position. Fluid dynamic modeling using Bernoulli and Darcy–Weisbach equations demonstrates oscillatory rather than sustained pressures, with magnitudes linked to nasopharyngeal Reynolds numbers (2400–6000) and turbulent energy dissipation (30–60%). Clinical efficacy persists despite variable pressures, reflecting synergistic mechanisms: inspiratory flow matching (40–50% reduction in work of breathing), dead-space clearance (CO₂ reduction, r = −0.77, p < 0.05), emergent pressure effects (10–20%), and thermal humidification (10–20%). Electrical impedance tomography reveals heterogeneous alveolar recruitment, with high-potential (54%) and low-potential (46%) phenotypes. Based on these mechanistic insights, this review proposes the term “emergent hydrodynamic pressure” to accurately describe HFNC’s transient, flow-dependent pressures. This terminology differentiates HFNC from conventional positive pressure systems and aligns language with the principles of fluid dynamics and respiratory physiology. Full article

A novel four-in-one (4-in-series) MicroLED-in-Package (MiP4) architecture is demonstrated for the first time, integrating four sub-85 µm blue micro-LED (µ-LED) dies on a transparent glass substrate through a redistribution-layer (RDL) interconnection process. The MiP4 device operates natively at 16 V, eliminating the need for step-down converters and simplifying high-voltage backlight driving circuits. The transparent glass carrier enables efficient light extraction, excellent thermal dissipation, and uniform emission. Electrical and optical characterization of dual- (B2), triple- (B3), and quad-chip (B4) devices shows ideal voltage scalability (8 V, 12 V, 16 V) and stable emission at 450 ± 2 nm with minimal FWHM broadening (22–29 nm). Compared with a commercial LED, the MiP4 delivers 1.8× higher optical power (~41.8 mW) despite its active area being only ~1/70 that of the reference device (20,000 µm² vs. 1,350,000 µm²), yielding a dramatically enhanced luminous flux density of 64 lm/mm² at 50 mA. Furthermore, pulse-driven measurements under 2%, 5%, and 10% duty cycles verify excellent thermal stability and minimal spectral shift (<1 nm), confirming the device’s robustness and energy efficiency. This first-of-its-kind 4-in-1 high-voltage glass-based µ-LED package provides a scalable and manufacturable route toward next-generation ultra-thin, high-brightness Mini-LED backlight and optical communication systems. Full article

The rapid development of Internet of Things (IoT) devices has raised challenges in hardware security, as these devices often transmit sensitive data. Physically Unclonable Functions (PUFs) provide a promising approach to address such security concerns. However, high power consumption limits the efficiency of PUFs and reduces battery life in IoT devices, making low-power operation essential while generating secure keys. Adiabatic logic offers a method to reduce energy dissipation in CMOS circuits. By combining these concepts, adiabatic-based PUFs utilize both CMOS process variations and adiabatic logic principles to achieve low-power operation while maintaining high security. In this paper, a low-power 6-transistor (6T) adiabatic PUF circuit is designed and evaluated through simulation using 0.18 μm CMOS process. The simulation is performed under three body-bias conditions, where the PMOS transistor body is connected to Vdd, Vpc, or the source, and the results show that the proposed PUF achieves high key metrics including reliability and uniqueness close to their ideal values. In addition, it achieves an energy dissipation of 15.10 fJ/Cb-cycle per bit, reducing energy dissipation by over 60% compared to the conventional quasi-adiabatic design. Furthermore, by reducing the number of transistors compared to the conventional ultra-low-power design, the proposed circuit achieves a smaller implementation area. Full article

This paper addresses the issue that traditional magnetorheological (MR) dampers have limited improvements in magnetic field utilization and damping channel length in confined spaces. It proposes an annular MR damper with an annular cylinder for propeller shafting. The piston head forms damping gaps with the cylinder’s inner and outer walls. This doubles the damping channel length without increasing axial size. The paper explains its working principle, completes the magnetic circuit design and damping force modeling, and utilizes COMSOL 5.6 Multiphysics to construct a magneto-fluid coupling model for analysis. Results show that, under 10 mm amplitude, 1 Hz sinusoidal excitation, and 2.0 A current, the damper outputs a damping force of 67.65 kN, with a damping adjustable coefficient of 10.87. Its force-displacement curve has a full hysteresis loop, showing excellent energy dissipation. The study proves the annular structure boosts the damper’s performance, offering a new way to achieve high damping force and a wide dynamic range in a compact space. Full article

This paper presents a reconfigurable switching circuit and control methodology for mitigating power losses in photovoltaic (PV) systems under partial shading. The proposed hardware uses a simplified network of power MOSFETs and diodes to enable dynamic reconfiguration between series and parallel connections, improving energy yield with minimal conduction losses. Unlike conventional approaches that require irradiance measurements or extensive sensing, the control algorithm uses only per-module voltage and a single-current measurement to detect shading events in real time. A novel switching strategy reduces the number of actively controlled transistors, simplifying the control circuitry and reducing power dissipation. Both simulation and experimental results validate the method. Simulations of a 4-module PV system showed maximum power point (MPP) increases from 900 W to over 1100 W and from 460 W to 900 W, with full recovery to 1500 W after shading removal. Experimental verification on a 3-module setup under controlled shading yielded similar improvements: MPP increased from 38.4 W to 45.6 W and from 38.4 W to 45.8 W. These results demonstrate rapid adaptability, effective mismatch loss reduction, and maximisation of available power, making the proposed design a practical and low-overhead solution for commercial PV systems with non-uniform irradiance. Full article

In this paper, superconducting fault current limiter (SFCL) operation in the presence of a long-duration fault is presented. The SFCL device utilizes second-generation high-temperature superconducting (2G HTS) tapes, which exhibit zero resistance under normal operating conditions. When the current exceeds the critical threshold specific to the superconducting tape, then it undergoes a transition to a resistive state—a phenomenon known as quenching. As a consequence, this leads to introducing impedance into the circuit, effectively limiting the magnitude of the fault current. Additionally, this transition dissipates electrical energy as heat within the material. The generated energy corresponds to the product of the voltage drop across the quenched region and the current flowing through it during the fault duration. In specific configurations of the power system, it is expected that the SFCL should limit the fault current for an extended period of time. In such a situation, a certain amount of energy will be generated, and it must be verified that the tape loses its properties or parameters (e.g., lowering the critical current value) or is destroyed. Therefore, experimental tests of the tapes were conducted for various short-circuit current, voltage drop, and short-circuit duration values to assess the effect of the amount of generated energy on the 2G HTS tape. Additionally, recommendations are presented on how to protect the SFCL during long-lasting short circuits. Full article

This paper presents a novel ultrafast DC circuit breaker concept based on a railgun actuator, designed for ultrafast charging stations operating at 800 $\mathrm{V}$ and delivering up to 640 $\mathrm{k}$$\mathrm{W}$. The proposed breaker achieves contact opening speeds exceeding 190 $\mathrm{m}$/$\mathrm{s}$, enabling fault current interruption within 200 $\mathrm{\mu }\mathrm{s}$ and limiting the peak fault current to 2200 $\mathrm{A}$. This performance significantly reduces breaker stress compared with conventional mechanical solutions. System-level simulations demonstrate a dramatic reduction in energy dissipation during faults—from 11,000 J with a conventional fast breaker to just 250 $\mathrm{J}$ using the proposed design. A 3D finite element method model of the railgun actuator confirms the feasibility of achieving a 15 $\mathrm{m}$$\mathrm{m}$ stroke in 150 $\mathrm{\mu }\mathrm{s}$. The evolution of current density and magnetic field is analyzed, highlighting the influence of skin and velocity skin effects. Results confirm that the proposed solution acts both as a circuit breaker and a fault current limiter, enhancing safety, reliability, and durability in high-power DC systems. Full article

Discrete Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (SiC MOSFETs) are characterized by their lower parasitic parameters and single-chip design, enabling them to achieve even faster switching speeds. However, the rapid rate of change in voltage (dv/dt) and current (di/dt) can lead to overshoot and oscillation in both voltage and current, ultimately limiting the performance of high-frequency operations. To address this issue, this paper presents a high-switching-frequency motor controller that utilizes discrete SiC MOSFETs. To achieve a high switching frequency for the controller while minimizing current oscillation and voltage overshoot, a novel electronic system architecture is proposed. Additionally, a passive driving circuit is designed to suppress gate oscillation without the need for additional control circuits. A new printed circuit board (PCB) laminate stack featuring low parasitic inductance, high current conduction capacity, and efficient heat dissipation is also developed using advanced wiring technology and a specialized heat dissipation structure. Compared to traditional methods, the proposed circuit and bus design features a simpler structure, a higher power density, and achieves a 13% reduction in current overshoot, along with a 15.7% decrease in switching loss. The silicon carbide (SiC) controller developed from this research has successfully undergone double-pulse and power testing. The results indicate that the designed controller can operate reliably over extended periods at a switching frequency of 50 kHz, achieving a maximum efficiency of 98.2% and a power density of 9 kW/kg (10 kW/L). The switching frequency and quality density achieved by the controller have not been observed in previous studies. This controller is suitable for use in the development of new energy electrical systems. Full article

Under the background of “dual-carbon” strategy and global energy transition, the metallurgical industry, which accounts for 15–20% of industrial energy consumption, urgently needs to reduce the energy consumption and emission of DC power supply of electric furnaces. Aiming at the existing 400–800 V/≥3000 A industrial-frequency transformer-rectifier system with low efficiency, large volume, heat dissipation difficulties and other bottlenecks, this thesis proposes and realizes a high-frequency integrated DC power supply scheme for high-power electric furnaces: high-frequency transformer core and rectifier circuit are deeply integrated, which breaks through and reduces the volume of the system by more than 40%, and significantly reduces the iron consumption; multiple cores and three windings in parallel are used for the system. The topology of multiple cores and three windings in parallel enables several independent secondary stages to share the large current of 3000 A level uniformly, eliminating the local overheating and current imbalance; the combination of high-frequency rectification and phase-shift control strategy enhances the input power factor to more than 0.95 and cuts down the grid-side harmonics remarkably. The authors have completed the design of 100 kW prototype, magneto-electric joint simulation, thermal structure coupling analysis, control algorithm development and field comparison test, and the results show that the program compared with the traditional industrial-frequency system efficiency increased by 12–15%, the system temperature rise reduced by 20 K, electrode voltage increased by 10–15%, the input power of furnace increased by 12%, and the harmonic index meets the requirements of the traditional industrial-frequency system. The results show that the efficiency of this scheme is 12–15% higher than the traditional IF system, the temperature rise in the system is 20 K lower, the voltage at the electrode end is 10–15% higher, the input power of the furnace is increased by 12%, and the harmonic indexes meet the requirements of GB/T 14549, which verifies the value of the scheme for realizing high efficiency, miniaturization, and reliable DC power supply in metallurgy. Full article

The advancement of Internet of Things (IoT) technology has enabled battery-powered devices to be deployed across a wide range of applications; however, it also introduces challenges such as high energy consumption and security vulnerabilities. To address these issues, adiabatic logic circuits offer a promising solution for achieving energy efficiency and enhancing the security of IoT devices. Adiabatic logic circuits are well suited for energy harvesting systems, especially in applications such as sensor nodes, RFID tags, and other IoT implementations. In these systems, the harvested bipolar sinusoidal RF power is directly used as the power supply for the adiabatic logic circuit. However, adiabatic circuits require a peak detector to provide bulk biasing for pMOS transistors. To meet this requirement, a diode-connected MOS transistor-based voltage doubler circuit is used to convert the sinusoidal input into a usable DC signal. In this paper, we propose a novel adiabatic logic design that maintains low power consumption while optimizing energy and current fluctuations across various input transitions. By ensuring uniform and complementary current flow in each transition within the logic circuit’s functional blocks, the design reduces energy variation and enhances resistance against power analysis attacks. Evaluation under different clock frequencies and load capacitances demonstrates that the proposed adiabatic logic circuit exhibits lower fluctuation and improved security, particularly at load capacitances of 50 fF and 100 fF. The results show that the proposed circuit achieves lower power dissipation compared to conventional designs. As an application example, we implemented an ultrasonic transmitter circuit within a LoRaWAN network at the end-node sensor level, which serves as both a communication protocol and system architecture for long-range communication systems. Full article

Quantum-dot cellular automata (QCA) offer a high-performance, low-power alternative to traditional VLSI technology for nanocomputing. However, the existing metal-dot QCA-based parity generators and checker circuits suffer from increased energy dissipation, larger area consumption, and complex multilayered layouts, limiting their practical feasibility. This work designs a 3-bit parity generator and 4-bit checker to address these challenges using an optimized modified majority voter-based Ex-OR gate in QCA. A single-layered layout was simulated in QCADesigner 2.0.3, avoiding crossovers to reduce fabrication complexity. Energy analysis using QCADesigner-E reveals 34.4 meV energy consumption, achieving 31% energy efficiency and 75% area efficiency in the context of QCA costs compared to recent designs. The proposed circuit highlights the unique potential of QCA as a scalable, energy-efficient solution for high-density next-generation computing systems. Full article

To address the challenges of prolonged current isolation times and high dependency on varistors in traditional flexible short-circuit fault isolation schemes for DC systems, this paper proposes a rapid fault isolation circuit design based on an adaptive solid-state circuit breaker (SSCB). By introducing an adaptive current-limiting branch topology, the proposed solution reduces the risk of system oscillations induced by current-limiting inductors during normal operation and minimizes steady-state losses in the breaker. Upon fault occurrence, the current-limiting inductor is automatically activated to effectively suppress the transient current rise rate. An energy dissipation circuit (EDC) featuring a resistor as the primary energy absorber and an auxiliary varistor (MOV) for voltage clamping, alongside a snubber circuit, provides an independent path for inductor energy release after faults. This design significantly alleviates the impact of MOV capacity constraints on the fault isolation process compared to traditional schemes where the MOV is the primary energy sink. The proposed topology employs a symmetrical bridge structure compatible with both pole-to-pole and pole-to-ground fault scenarios. Parameter optimization ensures the IGBT voltage withstand capability and energy dissipation efficiency. Simulation and experimental results demonstrate that this scheme achieves fault isolation within 0.1 ms, reduces the maximum fault current-to-rated current ratio to 5.8, and exhibits significantly shorter isolation times compared to conventional approaches. This provides an effective solution for segment switches and tie switches in millisecond-level self-healing systems for both low-voltage (LVDC, e.g., 750 V/1500 V DC) and medium-voltage (MVDC, e.g., 10–35 kV DC) smart DC distribution grids, particularly in applications demanding ultra-fast fault isolation such as data centers, electric vehicle (EV) fast-charging parks, and shipboard power systems. Full article

This review systematically examines recent advances in self-powered wireless sensing technologies based on triboelectric nanogenerators (TENGs), focusing on innovative methods that leverage breakdown discharge effects to achieve high-precision and long-distance signal transmission. These methods offer novel technical pathways and theoretical frameworks for next-generation wireless sensing systems. To address the core limitations of conventional wireless sensors, such as a restricted transmission range, high power consumption, and suboptimal integration, this analysis elucidates the mechanism of the generation of high-frequency electromagnetic waves through localized electric field ionization induced by breakdown discharge. Key research directions are synthesized to enhance TENG-based sensing capabilities, including novel device architectures, the optimization of RLC circuit models, the integration of machine learning algorithms, and power management strategies. While current breakdown discharge sensors face challenges such as energy dissipation, multimodal coupling complexity, and signal interpretation barriers, future breakthroughs in material engineering and structural design are anticipated to drive advancements in efficiency, miniaturization, and intelligent functionality in this field. Full article

This paper proposes a flattened power electronic design approach to enhance both power density and thermal management performance. As essential components in electrified energy conversion, evaluations of power converters are strongly based on their power density. Achieving a compact design typically requires a well-optimized printed circuit board (PCB) layout, optimal component design and selection, and an efficient thermal management system. During high-power operation, significant power losses can lead to substantial heat generation. Without effective thermal mitigation, this heat buildup may result in excessive temperature rises or even system failure. To address this challenge, this paper developed a flattened power converter design methodology to increase the effective heat-dissipation area without expanding the total volume consumption. This proposed design improves thermal performance and, in turn, enhances overall power density. A three-phase inverter prototype is developed and tested to demonstrate the effectiveness of the proposed method. Full article