Electro-Physical Model of Amorphous Silicon Junction Field-Effect Transistors for Energy-Efficient Sensor Interfaces in Lab-on-Chip Platforms

Abstract

This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions.

1. Introduction

Hydrogenated amorphous silicon (a-Si:H) [1,2,3,4,5,6] has found wide applications in several fields, for example photovoltaics [7,8,9,10,11]. Indeed, its low deposition temperature (below 250 °C) enables deposition on various substrates, such as plastic, metal, and glass. Moreover, its high absorption coefficient in the visible spectrum (ranging from 10⁶ to 10⁴ cm⁻¹ for blue and red wavelengths, respectively) allows for the use of thin film layers. Another important application field of a-Si:H devices is in flat panel displays (FPDs) [12,13,14,15], where thin film transistors (TFTs) are used as switching elements thanks to the wide energy gap (approximately 1.75 eV), which results in an extremely low dark current [16] and in a very high ON/OFF ratio.

An emerging field where a-Si:H devices are finding application is the development of lab-on-chip (LoC) systems, which has emerged as a transformative tool in fields such as biomedical diagnostics, environmental monitoring, and biochemical analysis, allowing for rapid, low-volume sample processing directly on a microfluidic chip [17,18,19,20,21,22,23,24,25].

One of the major challenges in enhancing LoC performance is achieving low limits of detection (LODs), relying not only on highly sensitive sensors but also on low-noise, specific electronics to amplify and process the weak signals generated by the integrated sensors [26,27,28,29,30,31]. However, as LoC platforms evolve to meet these high performance-demanding requirements, the complexity of external control electronics often increases [32,33,34,35]. Each added function or amplification stage increases power consumption, size, and overall device complexity, which can significantly limit applications where portability and low power consumption are essential, such as wearable sensors or portable diagnostic tools [36,37,38,39,40,41,42,43,44,45,46,47,48,49].

One promising solution to reduce this complexity involves embedding signal processing capabilities onto the LoC platform [50,51,52]. By integrating simple yet effective analog circuits on-chip, sensor signals can undergo preamplification and initial processing before reaching external control electronics. This local signal enhancement reduces dependency on external electronics, therefore simplifying control circuitry and potentially improving energy efficiency [53,54,55]. This approach addresses the growing demand for resource-efficient architectures that enable data processing at the edge, particularly in systems designed for low-power sensing scenarios.

In this context, a-Si:H offers unique advantages for integrating analog electronics into LoC devices. Photo- and temperature sensors [56], relaying on a stacked structure of p-type/intrinsic/n-type layers, have been utilized by different research groups for detecting biomarkers in plants [57], viruses through DNA/RNA amplification [58] and volatile compounds in water [59]. These applications demonstrate the versatility of a-Si:H thin-film electronics in supporting compact and multifunctional sensor interfaces, as also discussed in recent TFT reviews for biomedical sensing and diagnostics [60,61,62].

The amorphous silicon junction field-effect transistor (a-Si:H JFET) is another p-i-n-based configuration which has been proposed as an analog electronic device for preamplifying and processing signals directly within LoC platforms [63]. More specifically, the JFET is intended to enable transistor-level analog interface circuits (front-end/readout stages) integrated with the transducers, rather than being the sensing element itself. Therefore, by integrating this device alongside integrated thin-film sensors, LoC devices could achieve low LOD and high sensitivity, while minimizing the need for complex external circuitry. Furthermore, integration can support the development of co-engineered sensor interfaces where physical modeling and electronic behavior are jointly optimized, enabling future smart sensor platforms.

The operation of an amorphous silicon JFET is similar to that of the corresponding crystalline silicon device. It is based on the modulation of the depletion region of a doped layer induced by an electric field applied to the gate electrode. The modeling of crystalline silicon (c-Si) JFET is well known [64,65]. This paper is focused on the modeling of a-Si:H devices, whose behavior is strongly related to the presence of defects in the forbidden gap. These defects are mainly dangling bonds that act as recombination centers. Moreover, in a-Si:H-doped layers, the number of defects is increased by several orders of magnitude with respect to an intrinsic layer due to the low doping efficiency of dopant atoms. Therefore, the model based only on c-Si materials can not be valid anymore.

Within this framework, this study presents the development of an electro-physical model of the a-Si:H JFET across its various operation regions. The research encompasses device fabrication, characterization, and analytical modeling that accurately simulates the JFET’s experimental behavior. In a previous study [63], we have already introduced an analytical model aimed at providing a simplified representation of the electrical characteristics of JFETs. It was based on simplified assumptions that facilitated the mathematical analysis. Specifically, the model assumed the following: (a) the absence of defects within the a-Si:H layers; (b) electronic defect-free interfaces; (c) uniform doping across the p-type and n-type regions. These simplifications do not fully account for the complexities in real a-Si:H JFETs, where the presence of defect density in the bulk and at the interfaces significantly influence the device behavior. With the model developed in the present work, we provide a reliable framework for simulating the performance of a-Si:H JFETs, facilitating the design and optimization of LoC devices. This modeling approach also enables integration into simulation workflows for edge-compatible electronic devices and supports future platforms requiring low-power and adaptive signal processing capabilities.

It is worth noting that the a-Si:H JFET here investigated is not introduced as a performance-driven replacement of CMOS front-ends or other thin-film transistor technologies. Rather, its relevance for LoC platforms stems from technology-driven advantages, including low-temperature processing and compatibility with non-conventional substrates, as well as straightforward monolithic integration with a-Si:H thin-film sensors within the same fabrication flow. Moreover, unlike MOS-based solutions, the JFET operation does not rely on a gate dielectric stack, which simplifies integration in stacks primarily optimized for sensing layers. In this context, the main contribution of this work is the availability of a validated electro-physical compact model enabling circuit-level design and simulation of JFET-based interface blocks, which has been missing for this device class.

2. Experimental Details

A 3D schematic view of the JFET structure is shown in Figure 1. It consists of three primary layers: the p-doped, intrinsic and n-doped regions of amorphous silicon. This last layer acts as the device channel.

In a JFET with this structure, the p-doped layer interacts with the n-doped region to form the gate-drain and gate-source junctions. The application of a negative gate-source voltage ($V_{GS}$) reverse-biases these diodes, causing the depletion regions around the p-i and i-n junctions to expand into the p-doped and n-doped layers, respectively, and to narrow the conductive channel. As $V_{GS}$ becomes more negative, the depletion regions extend further, reducing the width of the conductive path between source and drain. When $V_{GS}$ reaches sufficiently high negative values, the channel can become fully depleted, drastically limiting the drain current.

In this study, the thickness of the intrinsic and n-doped layers, as well as the doping concentration of the latter, were chosen as the main variables to investigate their impact on the device performance. By contrast, the thickness and doping concentration of the p-doped layer were kept constant, as they were found to have minimal effect on the JFET functionality. To systematically analyze these parameters, 15 different configurations were fabricated, each containing a linear array of 12 identical JFETs. The n-layer thickness was varied between 30 nm, 40 nm, and 50 nm, the intrinsic layer thickness between 100 nm, 150 nm, and 200 nm, and the ratio of phosphine (PH₃) to silane (SiH₄) in the PECVD gas mixture was set to 0.1%, 0.25%, and 0.4%. The configurations were grouped as follows:

• Reference Configuration: Intrinsic layer thickness ($W_i$) of 150 nm and PH₃/SiH₄ doping at 0.25%.
• Variation in Intrinsic Layer: $W_i$ set to 100 nm and 200 nm, with PH₃/SiH₄ at 0.25%.
• Variation in Doping Concentration: PH₃/SiH₄ ratio adjusted to 0.1% and 0.4%, with $W_i$ fixed at 150 nm.

Each of these five primary configurations (hereafter referred to as ‘families’) was produced with the three different n-layer thicknesses, resulting in a total of 15 distinct device structures for analysis. These configurations provide a comprehensive basis for evaluating the impact of fabrication parameters on JFET performance.

2.1. Devices Fabrication

The fabrication of the amorphous silicon JFETs was made on glass substrates, with each fabrication run featuring 12 identical JFETs. This number allowed us to have a statistical behavior of the devices. The process began with a thorough cleaning of the glass substrates using a piranha solution (a 3:1 mixture of sulfuric acid and hydrogen peroxide) to ensure optimal adhesion and a contamination-free surface for the subsequent deposition steps.

The gate electrode was formed by depositing a 30/150/30 nm-thick chromium/alumi-num/chromium (Cr/Al/Cr) stack onto the substrate using thermal evaporation. The chromium layers ensure adhesion and oxidation resistance for the aluminum. Standard UV photolithography was then used to pattern this electrode, followed by wet etching to define the gate structure.

As mentioned in the introduction, the p-type, intrinsic, and n-type regions were grown by plasma-enhanced chemical vapor deposition (PECVD) at temperatures around 200 °C [66] and radio-frequency power density of 27.4 mW/cm².

The channel area was delimited using a lift-off process. A layer of photoresist was deposited by spin coating, patterned and subsequently removed from the drain and source regions. Then, a layer of chromium was thermally evaporated to form the source and drain contacts, and excess metal over the channel was removed along with the photoresist. This process precisely defined the contact regions and prevented the formation of chromium silicide on top of the channel [66].

Subsequently, via holes were created using a negative photoresist (SU-8) to enable inter-layer connections, and finally the drain and source electrodes were deposited by sputtering a 200 nm-thick titanium-tungsten (Ti-W) alloy. Each of the 15 configurations was fabricated following the same process, ensuring consistency and reproducibility across different parameter sets.

2.2. Devices Characterization

To evaluate the electrical performance of the fabricated JFETs, measurements were carried out using a probe station equipped with two Source Measure Units (SMUs, Keithley 236) to precisely acquire the device’s electrical responses. The two SMUs were connected between drain/source and gate/source terminals to measure drain ($I_D$) and gate current ($I_G$), respectively. Channel conductance and channel current were extracted from these measurements. Moreover, all measurements were performed at room temperature (25 °C) in a controlled laboratory environment.

2.2.1. Channel Conductance Measurements

In this measurement, a low drain-source voltage ($V_{DS}$) ranging from 0 to 6 mV was applied to ensure a nearly uniform-shaped channel between the drain and source contacts. The gate-source voltage $V_{GS}$ was varied from −2 V to 0 V in steps of 0.25 V.

To determine the channel current $I_{CH}$, it is essential to account for the reverse currents of the diodes between the drain and gate, and between the source and gate. These leakage currents, denoted as $I_{DG}$ (drain-gate leakage) and $I_{SG}$ (source-gate leakage), contribute to the total gate current $I_G$. A schematic cross-section of the device structure, illustrating the channel, gate, and leakage currents, is shown in Figure 2 to aid in understanding these components.

Given the symmetrical structure of the JFET and the very low voltage applied to the drain, the leakage currents are approximately equal. As a result, $I_{DG}$≈$I_G/2$, and the channel current $I_{CH}$ can be calculated using the following expression:

$$I_{CH}=I_D-{\displaystyle \frac{I_G}{2}}.$$

(1)

An example of the $I_{CH}$-$V_{DS}$ characteristics at low $V_{DS}$ is visible in Figure 3a, demonstrating the current linear dependence on $V_{DS}$ for the different values of $V_{GS}$. From these measurements, the channel conductance ($G_{CH}$) is extracted by considering the slope of the linear fit applied to the measured curves. Figure 3b shows $G_{CH}$ plotted as a function of $V_{GS}$. For both graphs, error bars refer to measurements performed on 9 different JFETs. A very similar trend was observed for all the other JFET configurations.

2.2.2. Channel and Gate Current Measurements

In these measurements, $V_{DS}$ was swept from 0 to 4 V in steps of 0.5 V to cover the device’s operation in both the linear and saturation regions. As in the previous measurements, $V_{GS}$ was varied from −2 V to 0 V in steps of 0.25 V.

For $V_{DS}$ values higher than zero, the drain-gate diode is always biased at higher voltages than the source-gate diode, leading to $I_G$ ≈ $I_{DG}$. Indeed, despite being reverse-biased, diodes in amorphous silicon exhibit an exponential behavior also in reverse bias conditions [67]. Consequently, the $I_{CH}$ is determined as:

$$I_{CH}=I_D-I_G.$$

(2)

Figure 4 presents the typical output characteristics of one of the fabricated devices, depicting the $I_{CH}$ dependence on $V_{DS}$.

The combination of channel conductance measurements in the triode region at very low $V_{DS}$ (below 10 mV) and the channel currents measurements reported in Figure 4 provides the basis for developing an empirical model that accurately describes the behavior of a-Si:H JFETs, as will be illustrated in detail in the next sections.

In addition to channel current modeling, the measured gate currents will also be used to develop an analytical description of the reverse leakage through the gate-drain and gate-source junctions. This extension aims to complete the electro-physical model by accounting for leakage effects that become non-negligible in specific bias conditions.

3. Model Definition

To construct a compact electro-physical model tailored to the proposed a-Si:H JFET technology and suitable for circuit-level use, a limited set of baseline assumptions will be introduced in the following subsections. These assumptions are consistent with standard depletion-based treatments adopted in field-effect devices and allow closed-form analytical relations to be derived. In particular, the channel modulation will be described through an effective depletion approach assuming abrupt junctions and uniform (effective) doping profiles in the conductive region, with the corresponding parameters extracted from the measured characteristics. These assumptions are reasonable in our technology because the stack is formed by sequential layer depositions in dedicated chambers, yielding interfaces that are close to abrupt (aside from possible limited interdiffusion) and doping levels that can be considered approximately uniform within each deposited layer [56,63]. Moreover, defect-related phenomena inherent to a-Si:H will not be treated through an explicit defect-state distribution; rather, their net impact will be incorporated into extracted effective parameters and empirical coefficients used to reproduce the experimental trends within the validated bias range.

3.1. Modeling of Depletion Region

To accurately model the channel current $I_{CH}$ in our amorphous silicon JFETs, we began by analyzing how the channel thickness ($t_c$) varies with the gate-source voltage when $V_{DS}$ is very close to 0 V. Under this condition, the drop voltage across the channel can be considered uniform and equal to $V_{GS}$. Moreover, $t_c$ is directly proportional to $G_{CH}$, as expressed by the following equation:

$$G_{CH}={\displaystyle \frac{q{\mu }_n{N}_{D}W}{L}}\times t_c,$$

(3)

where q is the elementary charge, ${\mu }_n$ the electron mobility in the n-layer, $N_D$ the doping concentration, and W and L are the channel width and length, respectively. Equation (3) follows the standard drift-transport expression for a uniformly doped conductive region, where the conductance is proportional to the product of carrier density, mobility, and effective cross-sectional area under low-field conditions [64]. In the present model, the effective conductive cross-section is represented by $W\times t_c$, consistently with the conductance-extraction approach adopted at small $V_{DS}$.

Subsequently, we segmented the behavior of $t_c$ as a function of $V_{GS}$ into three distinct regions:

• Linear Region: In this region, where the depleted area is far from the channel, the channel thickness can be expressed as:

  $$t_c\left(V_{GS}\right)=A-B\times (\phi -V_{GS})=t_n-{\displaystyle \frac{{ϵ}_s}{q{N}_D{W}_i}}(\phi -V_{GS}),$$

  (4)

  where $t_n$ is the n-layer thickness, ${ϵ}_s$ is the permittivity, q is the elementary charge, $N_D$ is the doping concentration, $W_i$ is the intrinsic layer thickness, and $\phi$ is the built-in potential of the p-i-n junction. Moreover, the compact form $t_c=A-B(\varphi -V_{GS})$ is used for readability, with $A\equiv t_n$ and $B\equiv {\epsilon }_s/\left(q{N}_D{W}_i\right)$. This behavior aligns with the predictions of the analytical model developed in [63], when a first-order Taylor expansion to linearly approximate the channel thickness behavior is introduced.
• Exponential Region: For high negative values of $V_{GS}$, near the threshold voltage, the device approaches the off-state, and $t_c$ exhibits an exponential relationship with $V_{GS}$, as described by:

  $$t_c\left(V_{GS}\right)=C\times e^{-D(\phi -V_{GS})},$$

  (5)

  where C and D are parameters that depend on $t_c$, $W_i$, and $N_D$.
• Transition Region: For intermediate values of $t_c$, where the linear approximation is no longer valid, but the channel has not yet entered the exponential regime, a third-order polynomial approximation is employed to bridge the linear and exponential behaviors. This approach ensures continuity and differentiability of $t_c$ between the regions. The polynomial is expressed as:

  $$t_c\left(V_{GS}\right)=a{(\phi -V_{GS})}^3+b{(\phi -V_{GS})}^2+c(\phi -V_{GS})+d,$$

  (6)

  where a, b, c, and d are coefficients chosen to guarantee that $t_c$ is continuous and differentiable at the region boundaries.

The fitting values for $\phi$, D, and C were determined by using the experimental data from the fabricated devices:

• Built-in Potential (φ): To better align the model with experimental data, we introduced an effective built-in potential ${\phi }_{\mathrm{eff}}$ instead of using the nominal value. This is defined as:

  $$\phi ={\phi }_{\mathrm{eff}}+R\times W_i.$$

  (7)
  This adjustment acts as a mathematical tool to improve the fit with experimental data. Therefore, $\phi$ does not directly imply a specific physical meaning, it serves effectively as a fitting parameter to refine our model of JFET operation.
• Parameter D: The exponential decay factor D is directly related to the depletion characteristics, depending on the intrinsic and n-type properties. It is defined as:

  $$D=\alpha \times {\displaystyle \frac{{ϵ}_s}{q{N}_D{W}_i}},$$

  (8)

  where $\alpha$ serves as a scaling factor to match the empirical data. This expression captures the inverse dependence on $N_D$ and $W_i$. Moreover, the inclusion of ${ϵ}_s$ and q ensures a formulation consistent with the one used in the linear region, maintaining continuity and coherence of the model (D = $\alpha \times B$).
• Parameter C: The value of C, representing the initial channel thickness in the exponential regime (i.e., when $V_{GS}$ = $\phi$), was determined empirically. We observed that C depends on both $W_i$ and the n-layer thickness $t_n$, and we modeled it as:

  $$C=e^{\alpha \times t_n+\beta +{\displaystyle \frac{\gamma }{W_i}}},$$

  (9)

  where $\alpha$, $\beta$, and $\gamma$ are fitting constants obtained from the experimental measurements. Notably, $\alpha$ is the same scaling factor used in the expression for D, ensuring coherence in how these parameters impact the model across different working regions.

To accurately determine the coefficients a, b, c, and d in the Transition Region, we imposed boundary conditions for both continuity and differentiability of $t_c\left(V_{GS}\right)$ at the linear-to-transition and transition-to-exponential boundaries. These conditions ensure a seamless connection between the polynomial and the adjacent regions. Specifically, we solved the following system of equations at the linear-to-transition boundary:

$$\left\{\begin{array}{c}{t}_c\left(V_{GS}\right){|}_{\mathrm{linear}}=t_c\left(V_{GS}\right){|}_{\mathrm{transition}}\hfill \\ {\displaystyle \frac{d}{d{V}_{GS}}}{t}_c\left(V_{GS}\right){|}_{\mathrm{linear}}={\displaystyle \frac{d}{d{V}_{GS}}}{t}_c\left(V_{GS}\right){|}_{\mathrm{transition}}\hfill \end{array}\right.$$

(10)

Similarly, at the transition-to-exponential boundary, the conditions were:

$$\left\{\begin{array}{c}{t}_c\left(V_{GS}\right){|}_{\mathrm{transition}}=t_c\left(V_{GS}\right){|}_{\mathrm{exponential}}\hfill \\ {\displaystyle \frac{d}{d{V}_{GS}}}{t}_c\left(V_{GS}\right){|}_{\mathrm{transition}}={\displaystyle \frac{d}{d{V}_{GS}}}{t}_c\left(V_{GS}\right){|}_{\mathrm{exponential}}\hfill \end{array}\right.$$

(11)

By solving these equations, the coefficients a, b, c, and d were uniquely determined, ensuring a consistent and smooth fit across all operational regions.

To define the boundaries between the regions, we introduced two threshold parameters, $t_{\mathrm{tran}}$ and $t_{\exp }$, which represent the values of $t_c$ at the transition points. These thresholds were empirically determined through fitting to best align with experimental data. The parameters $t_{\mathrm{tran}}$ and $t_{\exp }$ thus serve as markers to delineate the operational regions and guarantee the accuracy of the model.

To demonstrate the effectiveness of our model, we present in Figure 5 a fitting of the experimentally measured $G_{CH}$ using the model parameters derived through this process.

These fittings demonstrate the model’s capability to accurately describe the device behavior. The numerical values for the fitting parameters are listed in

Table 1. Extracted Parameters for the Electro-Physical Model.

Parameter	Value	Description/Role in the Model
R	$1.47 \times {10}^7\mathrm{V}/\mathrm{m}$	Linear correction coefficient used in Equation (7) to define the $W_i$-dependent effective built-in potential.
${\phi }_{\mathrm{eff}}$	1.96 V	Effective built-in potential baseline used in Equation (7) to set the depletion/bias reference in the model.
$\alpha$	$2.9 \times {10}^8{\mathrm{m}}^{-1}$	Scaling factor controlling the transition between linear and exponential trends (Equations (8) and (9)).
$\beta$	−21.66	Constant in Equation (9) shaping the amplitude of the transition term $C(W_i,t_n)$.
$\gamma$	$6.29 \times {10}^{-7}\mathrm{m}$	Constant in Equation (9) shaping the dependence of the transition term on $W_i$.
$t_{\mathrm{tran}}$	$25 \times {10}^{-9}\mathrm{m}$	Thickness threshold identifying the onset of the transition regime (linear → transition).
$t_{\exp }$	$0.5 \times {10}^{-9}\mathrm{m}$	Thickness threshold identifying the onset of the exponential regime (transition → exponential).

. These include R, ${\phi }_{\mathrm{eff}}$, $\alpha$, $\beta$, $\gamma$, $t_{\mathrm{tran}}$, and $t_{\exp }$, while the extracted values of $N_D$ and ${\mu }_n$ will be discussed later.

3.2. Drain Current Equations

In order to determine the channel current, we first defined the differential channel resistance $dR\left(x\right)$ at position x along the channel, where x = 0 corresponds to the source position, and x = L represents the drain position. Due to the potential drop caused by the drain current, the local channel thickness varies with position, therefore we have:

$$dR\left(x\right)={\displaystyle \frac{dx}{q{\mu }_n{N}_D{t}_c\left(x\right)W}},$$

(12)

where ${\mu }_n$ is the electron mobility, $N_D$ is the doping concentration, $t_c\left(x\right)$ is the local channel thickness, and W is the channel width [68]. By applying the Ohm’s law, the voltage drop across the channel at position x, $dV\left(x\right)$, is related to the current as:

$$dV\left(x\right)=d{v}_{DS}=I_{CH}\times dR\left(x\right).$$

(13)

Here, $V\left(x\right)$ denotes the local channel potential referenced to the source, with $V\left(0\right)=0$ and $V\left(L\right)=V_{DS}$; accordingly, the integration variable $v_{DS}$ represents the local potential $V\left(x\right)$.

By integrating along the channel, we obtain the following equation:

$$q{\mu }_n{N}_{D}W{\int }_0^{V_{DS}}{t}_c(V_{GS},v_{DS})d{v}_{DS}=I_{CH}{\int }_0^{L}dx,$$

(14)

which emphasizes that the channel thickness $t_c$ depends on both the applied gate-source voltage and the potential drop between the drain and source. Specifically, the analytical expression for $t_c$ can be derived by replacing $V_{GS}$ with $V_{GS}-V\left(x\right)$ in Equations (4)–(6). Thus, the channel current can be expressed as:

$$I_{CH}={\displaystyle \frac{q{\mu }_n{N}_{D}W}{L}}{\int }_0^{V_{DS}}{t}_c(V_{GS}-v_{DS})d{v}_{DS}.$$

(15)

To evaluate the integral in this equation, we accounted for the $t_c$ expression in the different operational region (linear, transition, or exponential). Therefore, two threshold voltages ($V_{TH,tran}$ and $V_{TH,exp}$) are defined to represent the transition points. These threshold voltages, inferred from Equations (4) and (5), are given by:

$$\left\{\begin{array}{c}{V}_{TH,tran}=\phi -{\displaystyle \frac{A-t_{tran}}{B}},\hfill \\ V_{TH,exp}=\phi +{\displaystyle \frac{1}{D}}\ln \left({\displaystyle \frac{t_{exp}}{C}}\right).\hfill \end{array}\right.$$

(16)

With these definitions, the integral in Equation (15) can be solved, yielding different formulations depending on whether $V_{DS}$ is lower than $V_{GS}-V_{TH,tran}$, between $V_{GS}-V_{TH,tran}$ and $V_{GS}-V_{TH,exp}$, or greater than $V_{GS}-V_{TH,exp}$. The resulting expressions for the channel current in these cases are as follows:

• For $V_{DS}<V_{GS}-V_{TH,tran}$:

  $$I_{CH}={\displaystyle \frac{q{\mu }_n{N}_{D}W}{L}}{\int }_0^{\max (0,V_{DS})}{t}_c(V_{GS}-v_{DS}){|}_{\mathrm{lin}}d{v}_{DS}.$$

  (17)
• For $V_{GS}-V_{TH,tran}\le V_{DS}<V_{GS}-V_{TH,exp}$:

  $$\begin{array}{cc}\hfill I_{CH}={\displaystyle \frac{q{\mu }_n{N}_{D}W}{L}}\times [& {\int }_0^{\max (0,V_{GS}-V_{TH,tran})}{t}_c(V_{GS}-v_{DS}){|}_{\mathrm{lin}}d{v}_{DS}\hfill \\ & +{\int }_{\max (0,V_{GS}-V_{TH,tran})}^{\max (0,V_{DS})}{t}_c(V_{GS}-v_{DS}){|}_{\mathrm{tran}}d{v}_{DS}].\hfill \end{array}$$

  (18)
• For $V_{DS}\ge V_{GS}-V_{TH,exp}$:

  $$\begin{array}{cc}\hfill I_{CH}={\displaystyle \frac{q{\mu }_n{N}_{D}W}{L}}\times [& {\int }_0^{\max (0,V_{GS}-V_{TH,tran})}{t}_c(V_{GS}-v_{DS}){|}_{\mathrm{lin}}d{v}_{DS}\hfill \\ & +{\int }_{\max (0,V_{GS}-V_{TH,tran})}^{\max (0,V_{GS}-V_{TH,exp})}{t}_c(V_{GS}-v_{DS}){|}_{\mathrm{tran}}d{v}_{DS}\hfill \\ & +{\int }_{\max (0,V_{GS}-V_{TH,exp})}^{\max (0,V_{DS})}{t}_c(V_{GS}-v_{DS}){|}_{\exp }d{v}_{DS}].\hfill \end{array}$$

  (19)

These integrals represent the channel current in the three operational regions and are essential for accurately modeling the device behavior across different operating regimes.

3.3. Performance of the Channel Current Model Across Fabricated Devices

To assess the accuracy and versatility of the developed channel current model, we tested its performance across all 15 fabricated JFETs. Fabrication and simulated parameters are listed in

Table 2. Fabrication and simulation parameters for the analyzed devices.

Family	Nominal ${\mathit{t}}_{\mathit{n}}$ [m]	Simulated ${\mathit{t}}_{\mathit{n}}$ [m]	${\mathit{W}}_{\mathit{i}}$ [m]	${\mathit{\mu }}_{\mathit{n}}$ [${\mathbf{m}}^2/\mathbf{V}·\mathbf{s}$]	${\mathit{N}}_{\mathit{D}}$ [${\mathbf{m}}^{-3}$]
Reference $W_i=150$ nm ${\mathrm{PH}}_3/{\mathrm{SiH}}_4=0.25\%$	$30 \times {10}^{-9}$	$31.8 \times {10}^{-9}$	$150 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
	$40 \times {10}^{-9}$	$41.3 \times {10}^{-9}$	$150 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
	$50 \times {10}^{-9}$	$47.7 \times {10}^{-9}$	$150 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
$W_i=100$ nm ${\mathrm{PH}}_3/{\mathrm{SiH}}_4=0.25\%$	$30 \times {10}^{-9}$	$29.4 \times {10}^{-9}$	$100 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
	$40 \times {10}^{-9}$	$38.7 \times {10}^{-9}$	$100 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
	$50 \times {10}^{-9}$	$47 \times {10}^{-9}$	$100 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
$W_i=200$ nm ${\mathrm{PH}}_3/{\mathrm{SiH}}_4=0.25\%$	$30 \times {10}^{-9}$	$29 \times {10}^{-9}$	$200 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
	$40 \times {10}^{-9}$	$36.4 \times {10}^{-9}$	$200 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
	$50 \times {10}^{-9}$	$49.1 \times {10}^{-9}$	$200 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$5.25 \times {10}^{23}$
$W_i=150$ nm ${\mathrm{PH}}_3/{\mathrm{SiH}}_4=0.1\%$	$30 \times {10}^{-9}$	$27 \times {10}^{-9}$	$150 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$4.25 \times {10}^{23}$
	$40 \times {10}^{-9}$	$41.1 \times {10}^{-9}$	$150 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$4.25 \times {10}^{23}$
	$50 \times {10}^{-9}$	$46.8 \times {10}^{-9}$	$150 \times {10}^{-9}$	$2.4 \times {10}^{-5}$	$4.25 \times {10}^{23}$
$W_i=150$ nm ${\mathrm{PH}}_3/{\mathrm{SiH}}_4=0.4\%$	$30 \times {10}^{-9}$	$26.5 \times {10}^{-9}$	$150 \times {10}^{-9}$	$1.44 \times {10}^{-5}$	$5.5 \times {10}^{23}$
	$40 \times {10}^{-9}$	$41.2 \times {10}^{-9}$	$150 \times {10}^{-9}$	$1.44 \times {10}^{-5}$	$5.5 \times {10}^{23}$
	$50 \times {10}^{-9}$	$50.2 \times {10}^{-9}$	$150 \times {10}^{-9}$	$1.44 \times {10}^{-5}$	$5.5 \times {10}^{23}$

.

The comparison between the experimental data and the model-predicted $I_{CH}$-$V_{DS}$ characteristics, shown in Figure 6, highlights the robustness of the model across all the investigated devices. In this table, nominal $t_n$ and $W_i$ refer to the values of the n-layer and intrinsic layer thickness, respectively, as extracted from the experimental growth rate of the PECVD system; simulated $t_n$ is the value of the n-layer thickness used to reproduce the experimental results, while $N_D$ and ${\mu }_n$ are the n-layer doping level and the electron mobility, as derived from the channel conductance fittings reported in Figure 6.

The results demonstrate excellent agreement between the model and experimental data for all devices. Both the linear and saturation regions of the $I_{CH}$-$V_{DS}$ curves are accurately reproduced, and the model effectively adapts to variations in the fabrication parameters. Moreover, the model’s ability to account for the exponential behavior of the channel thickness ($t_c$) at lower $t_n$ values ensures its accuracy even in the most challenging configurations. Notably, this agreement is achieved with a single, unique set of fitting parameters, as reported in Table 1.

As highlighted above, the fabrication parameters for the devices are summarized in Table 2. The simulated $t_n$ values slightly differ from the nominal values provided during fabrication. This adjustment accounts for variations in the deposition processes. The equations in the proposed model are more sensitive to $t_n$ than $W_i$, making it crucial to refine $t_n$ in order to accurately describe the device behavior. It is important to note that the experimental curves represent an average obtained from devices fabricated on the same substrate, accounting only for intra-chip variations. Inter-chip variability, which may arise from independent deposition runs, is not included in this study. In other terms, the simulated $t_n$ values should therefore be interpreted as effective run-specific values used to reproduce the measured batch behavior, rather than as a mismatch with the nominal design targets. Producing multiple samples from different runs would likely yield averages closer to the nominal values of $t_n$. However, achieving such extensive sampling would have required significantly more resources, beyond the scope of this work.

The electron mobility (${\mu }_n$) is consistent at $2.4\times {10}^{-5}{\mathrm{m}}^2/\mathrm{V}·\mathrm{s}$ for most families. However, for the PH₃/SiH₄ = 0.4% family, ${\mu }_n$ decreases to $1.44\times {10}^{-5}{\mathrm{m}}^2/\mathrm{V}·\mathrm{s}$. This reduction is attributed to ionized impurity scattering caused by the higher doping concentration ($N_D$). Furthermore, as reported in previous studies [69], excessive doping can lead to saturation or even a slight decrease in conductivity. This is due to an increased density of defects, including dangling bonds, which acts as recombination centers or traps, limiting carrier mobility. Additionally, the compensatory effects between active dopants and defects further reduce the free carrier density, particularly at higher doping levels. Finally, the increase in $N_D$ is notably smaller between the PH₃/SiH₄ = 0.25% and PH₃/SiH₄ = 0.4% families, compared to the increase between the PH₃/SiH₄ = 0.1% and PH₃/SiH₄ = 0.25% ones. This observation is consistent with the defect-related effects seen for ${\mu }_n$: as doping levels increase, the fraction of inactive dopants rises due to compensation by defects, reducing the efficiency of doping and resulting in diminishing returns in carrier concentration.

Overall, the electrical performance of the a-Si:H JFETs here studied is modest compared to conventional transistor technologies: as shown in Figure 6, drain currents remain in the sub-µA range (a maximum of several hundred nanoamps in the bias range studied) and, consequently, the extracted transconductance is relatively low [70]. In absolute terms, these devices operate significantly below the current levels typically achieved by crystalline silicon MOSFETs [71,72,73] and various TFT/OTFT technologies [74,75,76]. These typically operate from at least the tens-of-µA range up to mA-level currents depending on geometry and bias conditions. However, this “low current” should not be considered solely a disadvantage. On the contrary, it inherently enables very energy-efficient interface electronics: even with a $V_{DS}$ voltage of a few volts, power dissipation remains in the order of the microwatt, which is advantageous for input stages in resource-constrained LoC platforms. Being a depletion-type (normally conductive) transistor, it does not require large gate voltage variations for optimal operation, and, as we will see in the next section, gate leakage currents remain low under the considered bias conditions. Furthermore, the a-Si:H JFET does not require a gate dielectric layer, simplifying its fabrication and monolithic integration with thin-film sensors on unconventional substrates.

3.4. Gate Current Modeling

To complete the analytical description of the device behavior, we have modeled the gate current $I_G$, which flows through the reverse-biased junctions formed between the gate and the source/drain terminals. In our measurement configuration, the gate-drain diode is typically more reverse biased than the gate-source diode, thus dominating the total measured gate current. However, due to the geometrical symmetry of the device, the physical model described in this section applies equally to both junctions.

As first step, we have evaluated the effect of the n-layer thickness $t_n$ on the gate current. Across all five fabricated device families, no significant variations were observed when $t_n$ was changed, indicating that, as expected, the n-layer thickness does not influence the leakage mechanism.

Then, we have analyzed the dependence on the intrinsic layer thickness $W_i$, finding a systematic variation in both the magnitude and voltage dependence of the gate current. The experimental data confirmed an exponential dependence on the drain-gate voltage $V_{DG}$ [67], which was modeled using the following formulation:

$$I_G(V_{DG},W_i)=H\left(W_i\right)·e^{K\left(W_i\right)·V_{DG}}.$$

(20)

Both the prefactor H and the exponential coefficient K depend on $W_i$. The prefactor, which scales proportionally with the diode area, was found to follow a power-law dependence:

$$H\left(W_i\right)=L_D·W·H_0·W_i^n,$$

(21)

where $L_D$ = 300 µm is the diode length and W is the JFET width, while the fitting values of $H_0$ and n are $10.489·{10}^{19}$ A·${\mathrm{m}}^{-\left(\mathrm{n}+2\right)}$ and 3.731, respectively. The increasing trend of H with $W_i$ is well fitted by this expression within the experimental range, although its validity is not expected to extend to arbitrarily large $W_i$.

The voltage sensitivity of the gate current, represented by the exponential coefficient K, decreases with increasing $W_i$, consistent with the expected reduction of the average electric field across the junction. The dependence of K on $W_i$ was successfully modeled with the following expression:

$$K\left(W_i\right)=K_{\infty }-(K_{\infty }-K_0)·e^{-W_i/{\tau }_i},$$

(22)

where the fitting parameters are: $K_0$ = 2061.9 ${\mathrm{V}}^{-1}$, $K_{\infty }$ = 1.2 ${\mathrm{V}}^{-1}$, and ${\tau }_i$ = 12.32 nm. This formulation captures the rapid transition from high field sensitivity (thin intrinsic layer) to a low-field regime with constant slope.

The validity of the proposed model is confirmed in Figure 7, which shows the measured gate current as a function of $V_{DG}$ for the three representative values of $W_i$, alongside the corresponding fitted curves. The agreement across the entire voltage range highlights the accuracy of the analytical formulation and its ability to describe the experimental trends using a reduced set of parameters.

Finally, we investigated the influence of doping on the gate current by analyzing three families with different phosphine-to-silane gas ratios. As shown in Figure 8, the measured $I_G$-$V_{DG}$ characteristics remain nearly unchanged across all doping levels, confirming that the leakage current is not significantly affected by $N_D$. Moreover, the larger error bars found in samples with higher doping concentration are consistent with the aforementioned defect abundance that we have observed in the silane/phosphine ratio 0.4% sample. Indeed, increasing trap density generates statistical variability in the reverse leakage current, resulting in greater dispersion in the measured $I_G$ values.

In conclusion, results demonstrate that the reverse leakage is mostly affected by the intrinsic region, while the doping concentration and the thickness of the n-layer have negligible impact.

4. Conclusions

This work has presented a comprehensive electro-physical model for hydrogenated amorphous silicon Junction Field Effect Transistors. By combining experimental observations with analytical refinements, we have developed a robust framework that accurately describes the behavior of a-Si:H JFETs across a wide range of fabrication parameters. In particular, the JFET channel current has been modeled by separating the operating regimes and defining analytical expressions that depend on gate voltage, drain-source bias, and structural parameters such as the intrinsic layer thickness $W_i$, the n-layer thickness $t_n$, and the doping concentration $N_D$. Additionally, the gate leakage current has been described through an exponential formulation with physically meaningful dependencies, showing a clear correlation with $W_i$ and a negligible influence from both $t_n$ and $N_D$. This dual modeling approach ensures consistency across conduction and leakage mechanisms using a unified parameter framework.

The model exhibits excellent agreement with the measured device characteristics, achieved using a single set of fitting parameters. This highlights its reliability and adaptability.

A key advantage of the proposed model is its compatibility with simple simulation environments, as all the device’s working operation regions are expressed through analytical equations. Indeed, the channel current can be implemented as a voltage-controlled current source, directly evaluating the closed-form $I_{CH}(V_{GS},V_{DS})$ relations (including the regime transitions). In addition, the reverse leakage contribution can be represented with exponential diode-like elements, consistently with the analytical formulation adopted for $I_G$. Specifically, the developed model supports the design of JFET-based preamplification circuits directly on LoC platforms, facilitating the initial processing of sensor signals. This integration significantly reduces the complexity of external electronics, enhancing the efficiency of LoC and making them more suitable for portable and wearable applications. Furthermore, the proposed framework can support the development of edge-compatible and resource-efficient sensor interfaces, potentially enabling smart signal processing directly on the chip.

Future work will extend the presented model by adding the relevant charge-storage elements (e.g., bias-dependent junction/depletion capacitances) to enable transient simulations, and by developing a noise-aware circuit-level description for low-signal readout design. The model will also be coupled with representative sensor elements for complete sensor-cell simulations, and extended to account for temperature and other environmental factors dependence and long-term stability. These improvements aim to further refine the model’s predictive accuracy and validate its applicability to other materials and devices compatible with LoC technologies. At the same time, we are evaluating integration into co-design workflows for adaptive platforms, where accurate physical modeling contributes to the development of next-generation electronic sensors with embedded intelligence.