Single-Layer Parity Generator and Checker Design Using XOR Gate in Quantum-Dot Cellular Automata (QCA) ^†

Abstract

Quantum-dot cellular automata (QCA) offer a high-performance, low-power alternative to traditional VLSI technology for nanocomputing. However, the existing metal-dot QCA-based parity generators and checker circuits suffer from increased energy dissipation, larger area consumption, and complex multilayered layouts, limiting their practical feasibility. This work designs a 3-bit parity generator and 4-bit checker to address these challenges using an optimized modified majority voter-based Ex-OR gate in QCA. A single-layered layout was simulated in QCADesigner 2.0.3, avoiding crossovers to reduce fabrication complexity. Energy analysis using QCADesigner-E reveals 34.4 meV energy consumption, achieving 31% energy efficiency and 75% area efficiency in the context of QCA costs compared to recent designs. The proposed circuit highlights the unique potential of QCA as a scalable, energy-efficient solution for high-density next-generation computing systems.

1. Introduction

The search for alternatives to the scaling and shrinking issues of CMOS devices has intensified, as traditional transistor-based technology faces challenges such as increased leakage currents, higher power dissipation, and quantum effects at nanoscales [1,2]. The silicon-based semiconductor quantum-dot cellular automata (QCA) present a promising paradigm shift, leveraging the position of electrons within quantum dots to perform logic operations (binary states ‘0’ and ‘1’) in a quantum-equation-based computational model [3,4,5]. QCA operates using the Coulombic interaction between electrons in a cell of four quantum dots, typically with a cell size of 18 nm × 18 nm [4,5]. Binary states are represented with stable arrangements of electrons [3,5], as illustrated in Figure 1a. These binary states are generated through specific electron arrangements, in which two mobile electrons [5] occupy opposite diagonal positions to minimize repulsion [3,4]. A few basic blocks, such as QCA wires [6], inverters [7], and majority gates, help design any circuit in QCA. QCA wires enable signal transmission by facilitating polarization propagation between adjacent cells, ensuring data integrity. Figure 1b depicts the Landauer clocking of QCA cells, which is necessary for information propagation through a sinusoidal E-field [8] and controls circuit operation through four sequential phases: relax, switch, hold, and release [3,8]. This ensures a synchronized data flow through the wire in Figure 1c and prevents race conditions to reduce the latency of nano-circuits. The parity generator and checker circuits in QCA nanoprocessors ensure reliable data transmission and error detection using Ex-OR gates.

Motivated by the need for highly efficient and reliable error detection circuits in QCA-based computing, this work aims to enhance the performance of parity generator and checker circuits. While prior studies have explored conventional majority voter-based parity circuits, they often suffer from increased latency and area constraints. This work introduces a QCA parity generator and checker using a modified majority voter (MMV) [9,10], as per Figure 1d, that enhances efficiency and performance. This logic gate achieves significant reductions in energy consumption and area cost by reducing cell counts through implementing asymmetric cell placement and shared cell boundaries while maintaining logic functionality, and it minimizes clock zones by aligning the output cell with downstream logic, eliminating buffer zones, and reducing both energy and latency by one clock cycle and thereby reducing state-switching energy requirements [10].

The key contributions of this work include the following:

(I)

A novel QCA-based parity generator and checker circuit leveraging an optimized MMV design.

(II)

Improved efficiency in terms of area, delay, and energy dissipation compared to conventional designs.

(III)

A comparative analysis demonstrating the advantages of the proposed approach over existing state-of-the-art QCA parity circuits.

2. Related Works

Parity generator/checker circuits are essential building blocks in fault-tolerant systems. Therefore, many existing parity generator/checker layouts in QCA highlight their advantages and disadvantages. A few of these are discussed here.

Naz et al. introduced a 4-bit even parity checker [11] based on a fault-tolerant XOR gate. This checker, leveraging 414 cells, does not involve any parity generator circuit; the user gives input bits as arbitrary parity bits to be able to perform parity checks after 4 clock-delay. This work assessed energy details for the XOR design but overlooked the checker unit, which uses excessive logic gates to produce an output. The design in [12] uses 118 cells, covering 0.17 μm², with a delay of 1.25 clock cycles. Despite quantified energy dissipation and the use of crossovers, the design remains complex and lacks compactness when employing crossovers. In [13], V. K. Sharma suggested a highly compact and efficient design using only 18 cells with a minimal area of 0.01 μm² and a delay of 0.50 clock cycles. The simplicity is attributed to a single parity generator, excluding a checker unit. The design in [14] uses 98 cells, covering 0.09 μm², with a delay of 1.50 clock cycles. Though moderately efficient, its higher energy dissipation makes it suitable for specific applications. In [15], the circuit integrates 62 cells in a 0.08 μm² area, achieving a delay of 2.00 clock cycles. While it uses the highest logic gates, it suffers from performance due to energy inefficiencies. The circuit in [16] uses 55 cells, covers 0.09 μm², and involves a delay of 1.50 clock cycles with energy dissipation of ~16 meV. It shows moderate efficiency, balancing performance and resource utilization. The design in [17] balances size and performance, using 86 cells and covering 0.10 μm² with a delay of 1.50 clock cycles. However, energy dissipation data are missing, making it difficult to assess the circuit’s efficiency in nanocomputing. Based on the above discussion, earlier designs focus on robustness but suffer from issues related to energy dissipation and costs.

The proposed design balances area, energy efficiency, and scalability, overcoming the limitations of earlier works and setting a cost-effective benchmark for future research. Here are the key novelty points of your work beyond just cascading XOR gates for designing the parity block:

• Instead of conventional XOR cascades, the work employs a modified majority-voter (MMV)-based XOR gate, improving logic efficiency and reducing latency.
• The proposed design avoids multilayered crossovers, simplifies fabrication, and enhances layout feasibility and thermal stability for practical implementation.
• Compared to recent designs, the circuit achieves better energy efficiency, as validated using a specific tool.
• The design also achieves area efficiency, making it suitable for high-density computing applications.
• The optimized structure ensures a minimal delay overhead, improving the real-time reliability of QCA-based parity circuits. The methodology can be extended to design higher-bit parity generators and checkers while maintaining efficiency advantages.

3. Methods

A 3-bit even parity generator outputs a parity bit, PG_out, of 1 when the number of high inputs is odd, and 0 otherwise. The logic of the even parity generator can be logically expressed as follows:

$$\mathit{PG}\_\mathit{out}=\mathit{A} \oplus \mathit{B} \oplus \mathit{C}$$

(1)

where A, B, and C are the input bits.

Table 1. Even parity generator logic table.

A (Input)	B (Input)	C (Input)	PG_out (Output)
0	0	0	0
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	1

illustrates the corresponding logic table for the generator. For error detection, a parity checker verifies the parity of the received 4-bit message, consisting of three data bits and the parity bit PG_in. The receiver expects an even number of 1s in the message. Figure 2a represents the design schematic of the entire unit to illustrate the design strategy in the context of QCA nanocomputing, aiming to achieve novelty. If a discrepancy is found, the parity checker signals an error. The checker’s logic is expressed as follows:

$$\mathit{PC}=\mathit{P} \oplus \mathit{Q} \oplus \mathit{R} \oplus \mathit{PG}\_\mathit{in}$$

(2)

Here, P, Q, R, and PG_in represent the inputs, with the logic table detailed in

Table 2. Even parity checker logic table.

P (Input)	Q (Input)	R (Input)	PG_in (Input)	PC (Output)
0	0	0	0	0
0	0	0	1	1
0	0	1	0	1
0	0	1	1	0
0	1	0	0	1
0	1	0	1	0
0	1	1	0	0
0	1	1	1	1
1	0	0	0	1
1	0	0	1	0
1	0	1	0	0
1	0	1	1	1
1	1	0	0	0
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0

. The proposed QCA layout, as depicted in Figure 2b, which functions as an even parity generator and a parity checker, uses an efficient MMV-based Ex-OR gate for each circuit. The MMV-based Ex-OR gate enhances reliability and energy efficiency in parity operations. The use of this MMV in the proposed design does not restrict its applicability to specific QCA realizations, as it remains compatible with both clocking-based and energy-driven QCA models. Its compact design, by optimizing cell placement with strategic clocking, lowers switching energy and footprint. Efficient clocking ensures adiabatic operation with reduced kink energy compared to conventional majority gates. However, its technological validity depends on fabrication feasibility, robustness against defects, and scalability, which require further exploration in practical QCA implementations [10]. Using the QCADesigner 2.0.3 [18] tool, the proposed layout implements the parity generator and checker circuits with just three MMVs, achieving a 1.00 clock cycle delay. For the generator, an MMV-based TIEO (three-input exclusive OR) gate [10] processes inputs A, B, and C to produce PG_out. For the checker, two TIEO gates and one 2-input MMV-based Ex-OR gate handle inputs P, Q, R, and PG_in, and their outputs are combined to determine the final checker output PC without employing any crossover. It is a single-layer QCA layout consisting of 37 cells, requiring a total area of 0.05 µm², with each cell occupying 0.011 µm². This compact and efficient design demonstrates the potential of QCA technology for reliable, low-power data communication systems.

4. Results and Discussions

In the context of the proposed QCA parity generator/checker layout for the parity checker, the inputs P, Q, and R are used to verify the functionality of the parity-checking circuit along with the generated parity bit, PG_in. The specific cases of P = 1, Q = 0, and R = 0 are considered during simulation to test how the circuit responds to different input combinations and ensure that it correctly computes the parity based on these inputs. The parity checker is expected to determine the parity of the inputs and produce the correct output, PC, following Equations (1) and (2), as shown in Figure 3a. Another expected output is represented in Figure 3b, setting input combinations according to Table 2. These thorough tests are crucial to confirm the reliability and correctness of the circuit design.

In QCA circuits, the average output polarization (AOP) serves as a critical metric for evaluating signal integrity, calculated as the arithmetic mean of the maximum (+P_max) and minimum (−P_min) output polarization values [19] expressed in Equation (3).

$$\mathrm{AOP}= {\displaystyle \frac{|+{\mathrm{P}}_{\max }| + |{-\mathrm{P}}_{\min }|}{2}}$$

(3)

A high AOP (≥0.85) value indicates robust binary state representation, where +1.00 and −1.00 correspond to perfect logic ‘1’ and ‘0’ states, respectively. For the proposed design, QCA simulations (Figure 3) demonstrate an AOP of 0.953 for both outputs, simulating at a temperature range of 1 K to 4 K and confirming strong noise immunity. This outperforms the suggested layout, which involves optimized cell geometry and clock synchronization, which minimize polarization decay. The AOP metric is particularly vital for assessing thermal resilience, as it quantifies signal degradation under thermal fluctuations.

Energy dissipation analysis in QCA nanocomputing is crucial for evaluating circuit energy efficiency. The proposed circuit dissipates a total energy (TE) of 34.4 meV, simulated by the coherence vector simulation engine at a default clock frequency (T_C) of 0.25 THz per clock for adiabatic switching [20], with an average energy dissipation of 3.13 meV per cycle using the QCADesigner-E 2.2 [20] tool. This implies that the real-time circuit latency indicates the same in clock cycles divided by the simulation clock frequency calculated for the conventional Landauer clocking scheme of the QCA-based clock distribution network [8].

Costs in QCA are also key metrics for evaluating circuit efficiency [4]. The area-delay cost (AD cost) measures the trade-off between circuit size and speed, calculated as 0.05 units for the proposed circuit. The energy-delay cost (ED cost) assesses energy efficiency relative to operational speed, valued at 0.00033 units. The QCA-specific cost (QCA cost) combines design factors like logic gates count, crossovers and layer counts, and delay, which is 9 units for this design, calculated using Equations (4)–(6).

$$\mathit{AD} \mathit{cost}=\mathit{total} \mathit{area} \times {\mathit{delay}}^2$$

(4)

$$\mathit{ED} \mathit{cost}={\mathit{energy}}^2\times {\mathit{delay}}^2$$

(5)

$$\mathit{QCA} \mathit{cost}=\mathit{l}({\mathit{QM}}^2+\mathit{QI}+{\mathit{QC}}^2) \times {\mathit{delay}}^2$$

(6)

Here, the total area, energy, and delay are measured in μm², eV, and clock cycles, whereas l and QC indicate the number of layers and crossovers.

The introduced circuit was carefully designed to ensure both scalability and thermal stability within the operational constraints of single-layer non-molecular QCA architectures. The modular design approach allows for straightforward extension to higher bit-widths. All input/output nodes are strategically positioned at the periphery of the circuit layout for clean signal access while avoiding the routing congestion that typically complicates single-layer designs. Regarding thermal stability, while this methodology acknowledges the inherent cryogenic requirements of non-molecular QCA systems, this design incorporates robust clocking zones and optimized cell placement to maximize polarization retention, with the simulation results indicating reliable operation up to 4K when compared against experimental data from prior QCA realizations. The circuit’s thermal resilience is further enhanced by its minimized cross-wiring and balanced cell loading, which collectively reduce susceptibility to thermal noise. These architectural decisions address current scalability challenges and provide a foundation for potential integration with emerging room-temperature QCA technologies as material advancements progress.

5. Comparisons

The proposed scalable parity generator and checker circuit requires at least 18 fewer cells than the designs reported in

Table 3. Design parameters comparison table.

Works	Year	Cell Count	Total Area in μm2	Delay in Clock Cycle	#(QM + QI)	#QC	TEin meV	Costs
								AD Cost	ED Cost	QCA Cost
[11] *	2024	414	0.56	4.00	12 + 12	NA	NA	8.96	NA	2496.0
[12]	2024	118	0.17	1.25	9 + 2	3	207.60	0.26	0.0673	143.7
[13] *	2023	18	0.01	0.50	1 + 1	NA	NA	0.002	NA	0.5
[14]	2022	98	0.09	1.50	8 + 5	NA	26.53	0.20	0.0016	155.2
[15]	2022	62	0.08	2.00	10 + 1	NA	20.87	0.32	0.0017	404.0
[16]	2021	55	0.09	1.50	12 + 2	NA	NA	0.20	NA	328.5
[17]	2020	86	0.10	1.50	9 + 8	1	43.40	0.22	0.0042	202.5
Proposed	NA	37	0.05	1.00	3 + 0	NA	34.40	0.05	0.0011	9.0

* [11] has no parity generator unit, and [13] has no parity checker unit. #—count, QM—majority voter, QI—inverter, QC—crossover, and NA—not applicable.

, offering a 0.25 clock cycle reduction in delay compared to the best design in [12]. In terms of cost efficiency, the circuit is 31% more energy-delay cost-effective than [14] and 75% more area-delay cost-effective than the design in [16] due to its faster operational speed and optimized layout. Additionally, the proposed circuit demonstrates a 94% improvement in QCA-specific cost compared to the design in [12]. The designs in [11,13] are not directly comparable, as they do not have a parity generator and checker circuits, respectively.

6. Conclusions

The proposed QCA-based parity generator and checker offers a dual-functional, energy-efficient design for error detection in communication systems. Using an optimized MMV-based Ex-OR gate, the circuit achieves compactness, reduced energy dissipation, and enhanced reliability, making it suitable for low-power, high-performance, scalable nanocomputing. It shows 31% energy efficiency and 75% area efficiency compared to the latest QCA-based circuits. This single-layer crossover-free design eliminates complex multilayer interconnects and reduces fabrication challenges in both non-molecular and molecular QCA systems by simplifying layout alignment and minimizing signal interference during integration. Future work will focus on implementing this design in nano-circuits for real-world applications, and its methodology could be extended to advanced error-correcting mechanisms in the molecular QCA framework and other digital circuits in next-generation technologies.