Search Results (33)

This study demonstrates the fabrication of high-performance p-Cu₂O/n-β-Ga₂O₃ heterojunction barrier Schottky (JBS) diodes using copper as a low-work-function anode metal. By optimizing the Cu₂O spacing to 4 μm, the device achieves a turn-on voltage of 0.78 V, a breakdown voltage of 1700 V, and a specific on-resistance of 5.91 mΩ·cm², yielding a power figure of merit of 0.49 GW/cm². The JBS diode also exhibits stable electrical characteristics across the temperature range of 300–425 K. Under a 200 V reverse stress for 5000 s, the JBS diode shows only a 4.16% degradation in turn-on voltage and a 1.15-fold increase in dynamic specific on-resistance variation, highlighting its excellent resistance to stress-induced degradation. These results indicate that Cu₂O/Ga₂O₃ JBS diodes are promising candidates for next-generation high-efficiency and high-voltage power electronic applications. Full article

This paper presents the electrical characterization of the on-resistance (R_ON) of on-wafer 100 V p-GaN power High-Electron-Mobility Transistors (HEMTs). This study assesses device degradation in the context of a monolithically integrated half-bridge circuit, considering both Low-Side (LS) and High-Side (HS) configurations. Since on-wafer samples have been characterized, a custom experimental setup was developed to emulate stress conditions experienced by the devices in the half-bridge circuit. A periodic signal (T = 10 µs, T_ON = 2 µs) switching from the OFF to the ON state was applied for a cumulative duration of 1000 s. Different OFF-state stress conditions were applied by varying the gate-source OFF voltage (V_GS,OFF) between 0 V and −10 V. The on-resistance exhibited a positive drift over time for devices in either the LS or the HS configuration, with the latter showing a more pronounced degradation. Measurements at higher temperatures (up to 90 °C) were carried out to characterize the dynamics of the physical mechanism behind the degradation effects. We identified hole emission from C-related acceptor traps in the buffer as the main mechanism for the observed degradation, which is present in both the HS and the LS configurations. The additional degradation observed in the HS case was attributed to the back-gating effect, stemming from the non-null body-to-source voltage. Furthermore, we found that a more negative V_GS,OFF further increases R_ON degradation, likely related to the higher electric field near the gate contact, which enhances hole emission from C-related acceptor traps. Full article

Wide-Bandgap (WBG) semiconductors—silicon carbide (SiC) and gallium nitride (GaN)— enable high-power-density conversion, but performance is limited by where heat is generated and how it is removed. This review links device-level loss mechanisms (conduction and switching, including output-capacitance hysteresis and dynamic on-resistance) to structure-driven hot spots within the ultra-thin (tens of nanometers) two-dimensional electron gas (2DEG) channel of GaN HEMTs and to thermal boundary resistance at layer interfaces. We compare wire-bondless package concepts—double-sided cooling, embedded packaging, and interleaved planar layouts—and survey system-level cooling that shortens the conduction path and raises heat-transfer coefficients. The impact on reliability is discussed using temperature-sensitive electrical parameters (e.g., on-state VDS, threshold voltage, drain leakage, di/dt, and gate current) for real-time junction-temperature estimation and compact electro-thermal RC models for remaining-useful-life prediction. Evidence from recent literature points to interface resistance in GaN-on-SiC as a primary bottleneck, while near-junction cooling and advanced packages are effective mitigations. We argue for integrated co-design—devices, packaging, electromagnetic interference (EMI)-aware layout, and cooling—together with interface engineering and health monitoring to deliver reliable, high-density WBG systems. Full article

A radiation-hardened RCC (Ring Choke Converter) isolated power supply design is proposed, which provides an innovative solution to the challenge of providing stable power to the PWM controller in DC-DC converters under nuclear radiation environments. By optimizing circuit architecture and component selection, and incorporating transformer isolation and dynamic parameter compensation technology, the RCC maintains an 8.9 V output voltage after exposure to neutron irradiation of 3 × 10¹³ n/cm², significantly outperforming conventional designs with a failure threshold of 1 × 10¹³ n/cm². For the first time, the degradation mechanisms of VDMOS devices under neutron irradiation during switching operations are systematically revealed: a 32–36% reduction in threshold voltage (with the main power transistor dropping from 5 V to 3.4 V) and an increase in on-resistance. Based on these findings, a selection criterion for power transistors is established, enabling the power supply to achieve a 2 W output in extreme environments such as nuclear power plant monitoring and satellite systems. The results provide a comprehensive solution for radiation-hardened power electronics systems, covering device characteristic analysis to circuit optimization, with significant engineering application value. Full article

Vertical GaN P-i-N diodes exhibit excellent high-voltage performance, fast switching speed, and low conduction losses, making them highly attractive for power applications. However, their breakdown voltage is severely constrained by electric field crowding at device edges. Using silvaco tcad (2019) tools, this work systematically evaluates multiple edge termination techniques, including deep-etched mesa, beveled mesa, and field-plate configurations with both vertical and inclined mesa structures. We present an optimized multi-drift-layer GaN P-i-N diode incorporating field-plate termination and analyze its electrical performance in detail. This study covers forward conduction characteristics including on-state voltage, on-resistance, and their temperature dependence, reverse breakdown behavior examining voltage capability and electric field distribution under different temperatures, and switching performance addressing both forward recovery phenomena, i.e., voltage overshoot and carrier injection dynamics, and reverse recovery characteristics including peak current and recovery time. The comprehensive analysis offers practical design guidelines for developing high-performance GaN power devices. Full article

Gallium nitride high-electron-mobility transistors (GaN HEMTs) are critical for high-power applications like AI power supplies and robotics but face reliability challenges due to increased dynamic ON-resistance (R_{DS_ON}) from electrical and thermomechanical stresses. This paper presents a novel self-calibrating temperature-sensitive electrical parameter (TSEP) model that uses gate leakage current (I_G) to estimate junction temperature with high accuracy, uniquely addressing aging effects overlooked in prior studies. By integrating I_G, aging-induced degradation, and failure-in-time (FIT) models, the approach achieves a junction temperature estimation error of less than 1%. Long-term hard-switching tests confirm its effectiveness, with calibrated R_{DS_ON} measurements enabling precise remaining useful life (RUL) predictions. This methodology significantly improves GaN HEMT reliability assessment, enhancing their performance in resilient power electronics systems. Full article

Dynamic on-resistance (R_ON) of commercial GaN on Si normally off high-electron-mobility transistor (HEMT) devices is a very important parameter because it is responsible for conduction losses that limit the power conversion efficiency of high-power switching converters. Due to charge trapping effects, dynamic R_ON is always higher than in DC, a behavior known as current collapse. To study how short-time dynamics of charge trapping and release affects R_ON we use rectangular 0–5 V gate voltage pulses with durations in the 1 μs to 100 μs range. Measurements are first carried out for single pulses of increasing duration, and it is found that R_ON depends on both pulse duration and drain current I_D, being higher at shorter pulse durations and lower I_D. For a train of five pulses, R_ON decreases with pulse number, reaching a steady state after a time interval of 100 μs. The response to a five pulses train is compared to that of a square-wave signal to study the time evolution of R_ON toward a dynamic steady state. The DC R_ON is also measured, and it is a factor of ten smaller than dynamic R_ON at the same I_D. This confirms that a reduction in trapped charges takes place in DC as compared to the square-wave switching operation. Additional off-state stress tests at V_DS = 55 V reveal the presence of residual surface traps in the drain access region, leading to four times increase in R_ON in comparison to pristine devices. Finally, the dynamic R_ON is also measured by the double-pulse test (DPT) technique with inductive load, giving a good agreement with results from single-pulse measurements. Full article

The explosive demand for high-performance secondary power sources in artificial intelligence (AI) has brought significant opportunities for low-voltage GaN devices. This paper focuses on research on high-efficiency and high-reliability low-voltage p-GaN gate HEMTs with a gate–drain distance, L_GD, of 1 to 3 μm in our pilot line, manufactured on 6-inch Si using a CMOS-compatible process, with extraordinary wafer-level uniformity. Specifically, these fabricated p-GaN gate HEMTs with an L_GD of 1.5 μm demonstrate a blocking voltage of over 180 V and a high V_TH of 1.6 V and exhibit a low R_ON of 2.8 Ω·mm. It is found that device structure optimization can significantly enhance device reliability. That is, through the dedicated optimization of source field plate structure and interlayer dielectric (ILD) thickness, the dynamic ON-resistance, R_ON, degradation of devices with an L_GD of 1.5 µm was successfully suppressed from 60% to 20%, and the V_TH shift was significantly reduced from 1.1 to 0.5 V. Further, the devices also passed preliminary gate bias stress and high-voltage OFF-state stress tests, providing guidance for preparing high-performance, low-voltage p-GaN gate HEMTs in the future. Full article

The SiC MOSFET with an integrated SBD (SBD-MOSFET) exhibits excellent performance in power electronics. However, the static and dynamic characteristics of this device are influenced by a multitude of parameters, and traditional TCAD simulation methods are often characterized by their complexity. Due to the increasing research on neural networks in recent years, such as the application of neural networks to the prediction of GaN JBS and Finfet devices, this paper considers the application of neural networks to the performance prediction of SiC MOSFET devices with an integrated SBD. This study introduces a novel approach utilizing neural network machine learning to predict the static and dynamic characteristics of the SBD-MOSFET. In this research, SBD-MOSFET devices are modeled and simulated using Sentaurus TCAD(2017) software, resulting in the generation of 625 sets of device structure and sample data, which serve as the sample set for the neural network. These input variables are then fed into the neural network for prediction. The findings indicate that the mean square error (MSE) values for the threshold voltage (Vth), breakdown voltage (BV), specific on-resistance (R_on), and total switching power dissipation (E) are 0.0051, 0.0031, 0.0065, and 0.0220, respectively, demonstrating a high degree of accuracy in the predicted values. Meanwhile, in the comparison of convolutional neural networks and machine learning, the CNN accuracy is much higher than the machine learning methods. This method of predicting device performance via neural networks offers a rapid means of designing SBD-MOSFETs with specified performance targets, thereby presenting significant advantages in accelerating research on SBD-MOSFET performance prediction. Full article

Devices under semi-on-state stress often suffer from more severe current collapse than when they are in the off-state, which causes an increase in dynamic on-resistance. Therefore, characterization of the trap states is necessary. In this study, temperature-dependent transient recovery current analysis determined a trap energy level of 0.08 eV under semi-on-state stress, implying that interface traps are responsible for current collapse. Multi-frequency capacitance–voltage (C-V) testing was performed on the MIS diode, calculating that interface trap density is in the range of $1.37\times {10}^{13}$ to $6.07\times {10}^{12}$${\mathrm{cm}}^{-2}$${\mathrm{eV}}^{-1}$ from $E_C-E_T=0.29$ eV to 0.45 eV. Full article

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆V_th) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (C_rss), while maintaining a similar low ON-resistance. Full article

This work analyzes the impact of working conditions on the current collapse (CC) phenomenon for an automotive GaN device. For this purpose, some sensing circuits have been compared to find the most suitable for the considered GaN family. Simulations of the testing schematic have been performed, a prototype board has been created, and some measurements have been taken. Finally, the work has investigated the effect on the CC of the input voltage, current level, switching frequency, and duty cycle. The key outcome is that the temperature increment mitigates the CC phenomenon, which implies that the on-state resistance worsening (dynamic/static ratio), which is due to the CC, reduces with increasing temperature. Therefore, the typical increment of the dynamic on-resistance (R_DSON) with increasing temperature is ascribable to the increment of the static one with temperature, while it is not at all an exacerbation of the current collapse phenomenon. Full article

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (t_sc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (R_on,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Q_gd) and gate-drain capacitance (C_gd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process. Full article

In this work, we present an analytical model of dynamic power losses for enhancement-mode AlGaN/GaN high-electron-mobility transistor power devices (eGaN HEMTs). To build this new model, the dynamic on-resistance (R_dson) is first accurately extracted via our extraction circuit based on a double-diode isolation (DDI) method using a high operating frequency of up to 1 MHz and a large drain voltage of up to 600 V; thus, the unique problem of an increase in the dynamic R_dson is presented. Then, the impact of the current operation mode on the on/off transition time is evaluated via a dual-pulse-current-mode test (DPCT), including a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM); thus, the transition time is revised for different current modes. Afterward, the discrepancy between the drain current and the real channel current is qualitative investigated using an external shunt capacitance (ESC) method; thus, the losses due to device parasitic capacitance are also taken into account. After these improvements, the dynamic model will be more compatible for eGaN HEMTs. Finally, the dynamic power losses calculated via this model are found to be in good agreement with the experimental results. Based on this model, we propose a superior solution with a quasi-resonant mode (QRM) to achieve lossless switching and accelerated switching speeds. Full article

A systematic study of epi-AlGaN/GaN on a SiC substrate was conducted through a comprehensive analysis of material properties and device performance. In this novel epitaxial design, an AlGaN/GaN channel layer was grown directly on the AlN nucleation layer, without the conventional doped thick buffer layer. Compared to the conventional epi-structures on the SiC and Si substrates, the non-buffer epi-AlGaN/GaN structure had a better crystalline quality and surface morphology, with reliable control of growth stress. Hall measurements showed that the novel structure exhibited comparable transport properties to the conventional epi-structure on the SiC substrate, regardless of the buffer layer. Furthermore, almost unchanged carrier distribution from room temperature to 150 °C indicated excellent two-dimensional electron gas (2DEG) confinement due to the pulling effect of the conduction band from the nucleation layer as a back-barrier. High-performance depletion-mode MIS-HEMTs were demonstrated with on-resistance of 5.84 Ω·mm and an output current of 1002 mA/mm. The dynamic characteristics showed a much smaller decrease in the saturation current (only ~7%), with a quiescent drain bias of 40 V, which was strong evidence of less electron trapping owing to the high-quality non-buffer AlGaN/GaN epitaxial growth. Full article