Current Collapse Phenomena Investigation in Automotive-Grade Power GaN Transistors

Abstract

This work analyzes the impact of working conditions on the current collapse (CC) phenomenon for an automotive GaN device. For this purpose, some sensing circuits have been compared to find the most suitable for the considered GaN family. Simulations of the testing schematic have been performed, a prototype board has been created, and some measurements have been taken. Finally, the work has investigated the effect on the CC of the input voltage, current level, switching frequency, and duty cycle. The key outcome is that the temperature increment mitigates the CC phenomenon, which implies that the on-state resistance worsening (dynamic/static ratio), which is due to the CC, reduces with increasing temperature. Therefore, the typical increment of the dynamic on-resistance (R_DSON) with increasing temperature is ascribable to the increment of the static one with temperature, while it is not at all an exacerbation of the current collapse phenomenon.

1. Introduction

The automotive market is driving the development of increasingly efficient and high-performance electronic devices. Even today, most of a vehicle’s mechanical components are managed by electronics to optimize driving performance, fuel consumption, efficiency, safety, and driving comfort [1]. Most future power management systems are looking for reductions in both volume occupation and power consumption, but also an improvement of the performance of the systems. Improving the energetic efficiency is the key to increasing devices’ power density and portability [2].

The high electron mobility transistors (HEMTs) are particularly well suited for automotive applications because of their intrinsic properties. The gallium nitride (GaN) power devices are part of the HEMT family. Compared to the silicon power MOSFET, GaN HEMT has some advantages [3]: lower on-resistance (${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$) at the same breakdown voltage (BV); the channel is a two-dimensional electron gas (2DEG) with high electron mobility (${\mathrm{\mu }}_{\mathrm{e}}$ = 900 ÷ 2000 cm²/Vs); a small ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ allows for reducing power losses and increasing GaN-based system efficiency; GaN is a wide bandgap material ($E_g$ = 3.4 eV) with a high critical electric field (${\epsilon }_c$ = 3.3 MV/cm); higher BV and small-size devices allow for reducing system size/weight and cost; lower parasitic capacitances and lower gate charge ($Q_G$), especially with respect to the $Q_{GD}$ component; and a lower gate charge allows for reducing power consumption and operating at a higher switching frequency. These characteristics allow GaN-based devices to operate at switching frequencies higher than those of silicon, with lower conduction losses. Because of the physical structure of the GaN HEMTs, the bidirectional charge flow is allowed, although GaN HEMTs have no parasitic body diode [4]. Moreover, they are compatible with silicon digital CMOS lateral devices.

The main fields of application of the GaN HEMTs in electric vehicles (EVs) are the high-efficiency on-board charges (OBCs) and the mild hybrid DC–DC converters. Class-D amplifiers and LiDAR (Laser Imaging Detection and Ranging) for autonomous driving are two GaN automotive target applications [5]. GaN-based systems allow to reach high conversion efficiency; the same structure allows bidirectional switching (useful for the OBC) and has a smaller form factor compared to the silicon ones because of the wide bandgap property, so the power density is bigger than that of the silicon-based ones. The applicative boards that adopt GaN HEMTs have reduced dimensions, specifically because the passive elements’ dimensions, like inductors and capacitors, can be reduced [6]. The total cost of the applications based on the GaN transistors is, consequently, smaller than the traditional silicon-based ones.

Most of the devices currently on the market utilize enhancement-mode (e-mode) since they ensure the most reliable and safe operations [7]. Moreover, their driving circuit is simpler to realize. However, the existing technology suffers from some weaknesses, which cannot yet be fixed [8,9]. The worst one is the current collapse (CC) phenomenon, which causes the conduction power consumption to be greater than what the simulations predict [10]. The current collapse leads to an increased on-state resistance, named dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$, because the degradation is due to the device switching [11,12,13].

This paper reports a critical analysis of some sensing–clamping networks for dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measurements, highlighting their advantages and disadvantages. The network has been chosen considering the compromise among the measurement reliability, circuital complexity and cost. An additional important aspect that drove the choice of the preferred network was the need for measurement automation that, in turn, was necessary to perform many dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ evaluations of different devices under various working conditions. The evaluation of the dynamic_${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ of these devices was necessary to understand the impact of the different working conditions. It is worth noting that, for manufacturers, measurement automation under different working conditions is useful for large-scale device characterization and potential problem appraisal.

As aforementioned, an additional practical outcome of this work concerns the study of the impact of different working conditions. The experimental analyses have highlighted that the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ increases with increasing the input voltage and switching frequency while it strongly decreases as the duty cycle increases. Instead, the effect of the input current is almost negligible. The most important practical outcome concerns the impact of the temperature on the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. In particular, the ratio between dynamic and static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ reduces with increasing temperature. In other words, an increase in the temperature does not exacerbate the current collapse phenomenon; actually, it mitigates the phenomenon itself.

Section 2 first presents a brief introduction of the physical mechanism, then it establishes the main available sensing networks and their main features, and, lastly, highlights some SPICE simulations about the performance of the chosen network working with the complete schematic. The experimental activity is described in Section 3, where the device under test (DUT) is presented and both the static and the dynamic measurements are reported. The conclusion is articulated in Section 4.

2. Analysis of Sensing–Clamping Networks Used for the Evaluation of the Dynamic Resistance in Power GaN Transistors

This section first recalls the physics behind the CC phenomenon, then it reports the sensing technique for dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ evaluation and related sensing networks. These techniques indirectly measure the resistance by applying Ohm’s law [14,15]. Consequently, they must accurately know the flowing current of the device, as well as the voltage drop across it. One of the simplest ways to perform the task is to force a known current and then measure the on-state drain-source voltage (${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$) of the DUT. Since the current collapse phenomenon is related to the charge trapping that dynamically occurs inside its structure, the DUT must switch several times to observe the phenomenon.

The CC is influenced by the following working conditions: off-state voltage (${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$); device current (${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$); switching condition (hard or soft); switching frequency (${\mathrm{f}}_{\mathrm{s}}$); duty cycle (D); gate resistance (${\mathrm{R}}_{\mathrm{g}}$); gate drive voltage (${\mathrm{V}}_{\mathrm{G}\mathrm{S}}$); and junction temperature (${\mathrm{T}}_{\mathrm{j}}$). Figure 1 shows the cross-section of a typical HEMT with a recessed p-GaN gate [16].

The charges are mainly trapped at the two highlighted points: below the gate electrode and inside the GaN/buffer layers.

• Off-state trapping.

This kind of trapping mechanism is also known as “buffer layer trapping”. It occurs when the transistor, during the off-time interval (${\mathrm{t}}_{\mathrm{o}\mathrm{f}\mathrm{f}}$), is subjected to the voltage stress ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$: the higher the voltage, the larger the electric field applied between the drain and substrate (1 in Figure 1). In the GaN/buffer layers, the deep-level acceptors are ionized or filled with the leakage electrons from the Si substrate. As the ${\mathrm{t}}_{\mathrm{o}\mathrm{f}\mathrm{f}}$ increases, so does the number of filled traps. As the voltage ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ increases, so does the number of acceptors, hence the amount of trapped electrons.

2.

Hot-electron trapping.

This kind of trapping occurs when the transistor works in hard switching conditions. During the transitory, if the transistor is subjected to both high current and high voltage, the drain region is subjected to a large electric field. The 2DEG electrons acquire sufficient energy to jump toward the GaN/buffer layers where they are trapped by the acceptors (1). Moreover, the electrons are pushed toward the gate-drain region and are trapped in the dielectric (2). The hot electrons trapping depends on the blocking voltage ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ (which affects the electron acceleration and therefore the trapping efficacy) the current ${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$ (proportional to the number of accelerated electrons) the gate resistance (from which the switching speed is dependent).

Figure 2 reports a generic schematic that can be used to carry out the pulsed I-V characteristic, which is useful for ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ estimation. The driver sets the DUT’s switching behavior to the desired frequency and duty cycle. The forcing current (${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$) is obtained thanks to the DC voltage ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ and the load resistor ${\mathrm{R}}_{\mathrm{L}}$:

$${\mathrm{I}}_{\mathrm{I}\mathrm{N}}=\frac{{\mathrm{V}}_{\mathrm{I}\mathrm{N}}}{{\mathrm{R}}_{\mathrm{L}}+{\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}}$$

(1)

The diode is used as a freewheeling path when the DUT is off, while the capacitor, ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$, is useful during the transition to the on-state to provide a steep current rising edge. When the DUT is off, it is equivalent to an open circuit, so the drain-source voltage is ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{F}\mathrm{F}}={\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ and no current flows through it. When the DUT is on, its drain-source voltage drops to ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. The ${\mathrm{V}}_{\mathrm{D}\mathrm{S}}$ of the DUT undergoes a voltage swing equal to ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}-{\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$, so the full scale of the sensing instrument must be set to include the entire swing. Using an oscilloscope as a sensing instrument, an increase of the ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ implies a reduction of the measurement resolution because of the oscilloscope overdrive phenomenon (OOP) [17,18,19,20]. For this reason, an opportune sensing network (Figure 2) is mandatory to perform an accurate analysis. The sensing network must be connected between the drain and the source of the DUT and an oscilloscope’s probe is connected between its output terminals. In the following, we will refer to the network output voltage as ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$. Depending on the state in which the DUT is, this additional circuitry plays a different function.

• When the DUT is off, the network works in clamping mode, clamping the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{F}\mathrm{F}}$ to a ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}<{\mathrm{V}}_{\mathrm{I}\mathrm{N}}$. Additionally, the clamped voltage must be greater than the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ to avoid clamping during the on-state. This strategy reduces the amplitude of the voltage swing at the output of the network, avoiding the OOP and increasing the measurement resolution.
• When the DUT is on, the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ is indirectly measured through the network which is working in sensing mode. During this time interval, the ideal output voltage provided by the network ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ is equal to ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$.

At the beginning of the on-state, the network must go quickly in sensing mode to provide an accurate ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measuring. For this reason, the analysis cannot be performed using only a traditional voltage clamping circuit, but one or more components must be included for the measurement purpose. The cost of adding this network is paid in terms of a major circuital complexity and/or possible measurement offset or limitations.

The existing networks differ among them for both

• the clamping mechanism,
• the sensing mechanism.

2.1. Description of Sensing-Clamping Networks

2.1.1. Sensing-Clamping Network N.1

The sensing network of Figure 3 contains a Zener diode ${\mathrm{D}}_2$, a diode ${\mathrm{D}}_1$, and a limiting current resistor R [20,21,22]. The key point of the network is the Zener diode, with its ability to work in the third quadrant, providing quite a stable reverse voltage.

• Clamping mechanism—The resistor R limits the current from the supply so that the clamped voltage is equal to the sum of ${\mathrm{D}}_1$ forward voltage (${\mathrm{V}}_{\mathrm{f}\mathrm{D}1}$) and the Zener voltage of ${\mathrm{D}}_2$ (${\mathrm{V}}_{\mathrm{z}\mathrm{D}2}$):

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{f}\mathrm{D}1}+{\mathrm{V}}_{\mathrm{z}\mathrm{D}2}$$

  (2)

The task of ${\mathrm{D}}_1$ is to reduce the sensing delay at the start of the on-state, reducing the equivalent series capacitance (ESC) of the network.

• Sensing mechanism—When the DUT is on, the output voltage is equal to:

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}-{\mathrm{V}}_{\mathrm{R}}$$

  (3)

  where ${\mathrm{V}}_{\mathrm{R}}$ is the offset caused by the leakage current flowing through the resistor. The voltage ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ follows the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ only after a time interval determined by the RC time constant of the sensing network.

2.1.2. Sensing–Clamping Network N.2

This sensing network [20,21,22,23] consists of a MOSFET depletion transistor M, a resistor R, and a constant voltage ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$ (Figure 4). The gate of M is connected to a fixed potential, so its source potential controls its working state.

• Clamping mechanism—When the DUT is off, the current flows through M toward the resistor R, thus increasing the potential of node A. The voltage is clamped when the transistor is in the subthreshold region. The clamping voltage is then equal to the gate voltage reduced by the MOSFET threshold one (${\mathrm{V}}_{\mathrm{M},\mathrm{t}\mathrm{h}}$):

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{C}\mathrm{C}}-{\mathrm{V}}_{\mathrm{M},\mathrm{t}\mathrm{h}}$$

  (4)
• Sensing mechanism—When the DUT is on, the current flowing through the sensing network decreases, and so does the potential at node A, bringing M to the on-state. The voltage at the output of the network is

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}-{\mathrm{V}}_{\mathrm{M},\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$$

  (5)

Even this network introduces a measurement offset, due to the residual current flowing through the network, consisting of the MOSFET on-state voltage (${\mathrm{V}}_{\mathrm{M},\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$).

2.1.3. Sensing-Clamping Network N.3

This sensing network [20,21,22,23,24,25] combines the two previous networks, adding a few components such as two Schottky diodes ${\mathrm{D}}_1$, ${\mathrm{D}}_2$, and the resistor ${\mathrm{R}}_2$ to limit the current that flows through the Zener diode ${\mathrm{D}}_3$ (Figure 5). M is a MOSFET transistor; ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$, ${\mathrm{R}}_1$, and C are, respectively, a DC voltage source, a resistor and a capacitor that set the gate potential and the on-state transient of M.

• Clamping mechanism—When the DUT is off, the transistor M is in the subthreshold region because the potential at node A increases thanks to the Zener diode ${\mathrm{D}}_3$. The clamping process is like the previous one since when M enters the subthreshold region, the network clamps the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{F}\mathrm{F}}$ to

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{C}\mathrm{C}}-{\mathrm{V}}_{\mathrm{M},\mathrm{t}\mathrm{h}}$$

  (6)

The voltage of ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$ is typically increased from 6 V to 8 V to mitigate the amplitude of the transition spikes on the ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$, avoiding thus the OOP.

• Sensing mechanism—When the DUT is on, the potential at node A decreases and M is also in on-state. The voltage at the output of the network is

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}-{\mathrm{V}}_{\mathrm{M},\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$$

  (7)

The two resistors ${\mathrm{R}}_1$ and ${\mathrm{R}}_2$ control how the transistor M changes its working state, respectively for the on-state and the off-state.

2.1.4. Sensing–Clamping Network N.4

The topology of Figure 6 consists of a current mirror configuration, a load resistor R, a chain of N diodes ${\mathrm{D}}_{\mathrm{C}}$ and two high voltage diodes ${\mathrm{D}}_{\mathrm{A}}$ and ${\mathrm{D}}_{\mathrm{B}}$, with the same I-V characteristics [18,20,21,22,24]. The series of diodes between nodes A and B is used to clamp the off voltage and could be replaced by a Zener diode.

• Clamping mechanism—When the DUT is off, the diode ${\mathrm{D}}_{\mathrm{A}}$ is reverse-biased, so the mirrored current flows through the series of diodes toward the ground. The current is set by the resistor R. The diode ${\mathrm{D}}_{\mathrm{B}}$ is always forward-biased. The clamped voltage, acquired between nodes A and B by a differential probe, is

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}=\mathrm{N}{\mathrm{V}}_{\mathrm{f}\mathrm{D}\mathrm{C}}$$

  (8)

  where N is the number of diodes in the chain and ${\mathrm{V}}_{\mathrm{f}\mathrm{D}\mathrm{C}}$ is the forward voltage of one diode.
• Sensing mechanism—When the DUT is on, the two high voltage diodes are forward biased, so the voltage between the network’s output terminals is equal to the DUT on-state one:

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$$

  (9)

It is worth noting that this network could avoid any offset. More specifically, the sensed voltage is not affected by any offset only if the two diodes are perfectly matched between them.

2.1.5. Sensing–Clamping Network N.5

The sensing network [17,21,22,24] consists of only passive components, and is mainly based on two fast switching SiC Schottky diodes, ${\mathrm{D}}_1$ and ${\mathrm{D}}_2$, that work in a complementary way (Figure 7). The other components are two limiting current resistors, ${\mathrm{R}}_{\mathrm{C}\mathrm{H}\mathrm{A}\mathrm{R}\mathrm{G}\mathrm{E}}$ and ${\mathrm{R}}_{\mathrm{D}\mathrm{R}\mathrm{I}\mathrm{V}\mathrm{E}}$, a storage capacitor C and three couple of Zener diodes and resistors (${\mathrm{D}}_3$, ${\mathrm{D}}_4$, ${\mathrm{D}}_5$, ${\mathrm{R}}_3$, ${\mathrm{R}}_4$, ${\mathrm{R}}_5$). The output terminal of the circuit is at the cathode of ${\mathrm{D}}_5$ referred to the ground.

• Clamping mechanism—When the DUT is off, the current flows through ${\mathrm{D}}_1$, while ${\mathrm{D}}_2$ is reverse biased. The capacitor C is charged during this interval until its voltage is clamped to the Zener voltage of diodes ${\mathrm{D}}_3$ and ${\mathrm{D}}_4$:

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{z}\mathrm{D}4}$$

  (10)
• Sensing mechanism—When the DUT is on, the charges stored in the capacitor flow through ${\mathrm{R}}_{\mathrm{D}\mathrm{R}\mathrm{I}\mathrm{V}\mathrm{E}}$ toward the DUT, forcing ${\mathrm{D}}_2$ into conduction. The measured voltage at the output is then equal to

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}+{\mathrm{V}}_{\mathrm{f}\mathrm{D}2}$$

  (11)

  where ${\mathrm{V}}_{\mathrm{f}\mathrm{D}2}$ is ${\mathrm{D}}_2$ forward voltage. The resistance ${\mathrm{R}}_{\mathrm{D}\mathrm{R}\mathrm{I}\mathrm{V}\mathrm{E}}$ is properly chosen to limit the diode’s forward current: a high current may alter its temperature, making temperature dependent on the network’s offset.

2.1.6. Sensing–Clamping Network N.6

The topology [22] consists of two parts (Figure 8): the clamping–sensing circuit, which plays the main function, and the filter circuit inside the dashed square, to reduce the induced ringing noise. Two resistors (${\mathrm{R}}_1$, ${\mathrm{R}}_2$), two diodes (${\mathrm{D}}_1$, ${\mathrm{D}}_2$), and two Zener diodes (${\mathrm{D}}_3$, ${\mathrm{D}}_4$) are the key components of the network.

• Clamping mechanism—When the DUT is off, the diode ${\mathrm{D}}_1$ is reverse-biased, so the clamped voltage at node A is obtained from the voltage divider:

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{C}\mathrm{C}}\frac{{\mathrm{R}}_2}{{\mathrm{R}}_1+{\mathrm{R}}_2}$$

  (12)
• Sensing mechanism—When the DUT is on, ${\mathrm{D}}_1$ is forward-biased, so the output voltage is the sum of the diode forward voltage (${\mathrm{V}}_{\mathrm{f}\mathrm{D}1}$) and the DUT on-state voltage:

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}+{\mathrm{V}}_{\mathrm{f}\mathrm{D}1}$$

  (13)

The proper choice of ${\mathrm{R}}_1$, ${\mathrm{R}}_2$, and ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$ is necessary to ensure a clamped voltage greater than ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. The filter circuit consists of an active voltage buffer to reduce the high-frequency oscillations of the power loop. The parasitic inductance and capacitance of the power loop may involve a resonant oscillation that reduces the measurement accuracy. The values of ${\mathrm{R}}_{\mathrm{C}1}$ and ${\mathrm{C}}_1$ are properly selected to reduce the ringing. The Zener diodes ${\mathrm{D}}_3$ and ${\mathrm{D}}_4$ are used to both reduce the equivalent parasitic capacitance of node A and to clamp the voltage spikes during the transient to the off-state.

2.1.7. Sensing–Clamping Network N.7

This network [24], like some of the previous ones, uses the Zener diode to clamp the off voltage. Moreover, a double isolation branch allows for interrupting the direct path with the DUT (Figure 9). The functional components of this topology are: ${\mathrm{D}}_1$, ${\mathrm{D}}_2$ low capacitance high voltage isolation diodes; ${\mathrm{D}}_6$, ${\mathrm{D}}_3$ freewheeling diodes, with ${\mathrm{D}}_6$ Zener diode; D₄ low value constant current diode; R_t resistor; ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$ constant voltage source. The output voltage of the network is acquired between node B and the ground. The branch where ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$ and D₄ are placed sets the low current used during the entire measurement process.

• Clamping mechanism—When the DUT is off, the two isolation diodes are reverse-biased, so the voltage at node C is clamped at the Zener voltage of ${\mathrm{D}}_6$:

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{z}\mathrm{D}6}+{\mathrm{V}}_{\mathrm{r}\mathrm{D}2}\approx {\mathrm{V}}_{\mathrm{z}\mathrm{D}6}$$

  (14)
• Sensing mechanism—At the start of the DUT on-state, the potential of B and C become negative because the junction capacitances of ${\mathrm{D}}_1$ and ${\mathrm{D}}_2$ undergo a sudden voltage variation, thus ${\mathrm{V}}_{\mathrm{B}}$ and ${\mathrm{V}}_{\mathrm{C}}$ are clamped by the freewheeling diodes. Without the two freewheeling diodes, the network’s frequency response would be slower, since it depends on the parasitic capacitance of the four main diodes (${\mathrm{D}}_1$, ${\mathrm{D}}_2$, ${\mathrm{D}}_3$, ${\mathrm{D}}_6$). After this initial effect, nodes B and C are charged by the constant current. The ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ can be evaluated when the charging of B and C brings the two diodes ${\mathrm{D}}_1$ and ${\mathrm{D}}_2$ in forward conduction. When the DUT is completely on, the two isolation diodes are both forward conducting (${\mathrm{V}}_{\mathrm{f}\mathrm{D}2}$ is their forward voltage), so the voltage at the output of the sensing network is

  $${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}-2{\mathrm{V}}_{\mathrm{f}\mathrm{D}2}$$

  (15)

The sensing offset is concurrently measured during the analysis thanks to the isolation performed by ${\mathrm{D}}_1$, thus enabling to nullification of the estimation error due to the sensing offset.

The ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ can also be analytically calculated as follows:

$${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}=\frac{{\mathrm{V}}_{\mathrm{B}}-2{\mathrm{V}}_{\mathrm{f}\mathrm{D}2}}{{\mathrm{I}}_{\mathrm{R}\mathrm{L}}+{\mathrm{I}}_1-\frac{{\mathrm{V}}_{\mathrm{B}}}{{\mathrm{R}}_{\mathrm{t}}}}$$

(16)

The voltages ${\mathrm{V}}_{\mathrm{B}}$ and ${\mathrm{V}}_{\mathrm{f}\mathrm{D}2}$ are measured by connecting the oscilloscope’s probes, and the currents ${\mathrm{I}}_1$ and ${\mathrm{V}}_{\mathrm{B}}$/${\mathrm{R}}_{\mathrm{t}}$, are imposed by the diodes and the resistor.

2.2. Analysis of Characteristics of the Networks

This subsection presents a critical analysis of the sensing networks described above, primarily highlighting their appeal and limits in the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ analysis context. The networks described in the previous section differ among them for different aspects, such as measurement offset, sensing delay/switching capability, and maximum voltage to clamp.

Network N.1 is the basic one, both for its functioning and implementation. It is not recommended for medium switching frequency analysis since it brings a non-negligible time delay to the sensing. The network includes only passive components and does not require external sources or batteries. The resistor R must have a high resistance to limit the power dissipation of the network:

$${\mathrm{P}}_{\mathrm{R}}=\frac{{\left({\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{F}\mathrm{F}}-{\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\right)}^2}{\mathrm{R}}$$

(17)

Consequently, the time constant of the network is the largest among all others [20] and the network has the worst switching capability. The capacitive contribution to the time constant is lowered by adding the second diode ${\mathrm{D}}_2$ at the structure. Nevertheless, the frequency improvement is restrained. The network introduces an offset to the measurement due to the leakage current that flows through the resistor R during the sensing time interval.

Network N.2 is the evolution of the first one and it exploits MOSFET’s capability of working as a resistor. This network is faster than the first one to provide the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measurement in sensing mode, thanks to the MOSFET M. Its main drawback is the voltage spikes induced to ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ when the DUT enters the subthreshold: the parasitic capacitance of M (${\mathrm{C}}_{\mathrm{M},\mathrm{D}\mathrm{S}}$) is affected by a voltage variation, so an extra current on the resistor R generates the voltage spike. This aspect becomes worse as the switching frequency increases or as the resistance R decreases [20]. Moreover, the disturbance propagates through the whole measuring system. The two main consequences are the reduction in measurement accuracy since spikes could induce OOP, and the risk of damaging circuitry and the DUT itself [6,8].

The clamping–sensing network N.3 is a combination of the previous two networks, from which it inherits both the advantages and the drawbacks. Like the previous ones, this topology can be easily implemented, and it is suitable for low on-state voltage measurements. Instead, this circuit is not appropriate for a conduction loss measurement, since during the sensing interval the ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ shows initial voltage oscillations due to the state transition [24]. Like the second network, it has a high-frequency response and introduces voltage spikes at the beginning of the DUT state changes. This network adds quite negligible voltage offset to the measurement, due to the leakage current that flows through MOSFET M during the sensing interval. The network’s sensing speed depends on the appropriate choice of ${\mathrm{D}}_3$ and ${\mathrm{D}}_1$ because ${\mathrm{D}}_3$ should not conduct when the DUT is turned on. The junction capacitance of ${\mathrm{D}}_1$ is charged only by the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$, so the system frequency capability depends on how fast ${\mathrm{D}}_1$ enters the blocking state. The Schottky diodes, the capacitor C and the resistor ${\mathrm{R}}_2$ are designated to mitigate the voltage spikes, respectively providing a current freewheeling path and a slower transient to the off-state for M [20,23,24]. The amplitude of the spikes can also be reduced by increasing the ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$ voltage, but at the cost of a higher clamping voltage. Another important aspect to be considered when choosing the network’s components is that they could easily work out of their safe condition (SOA) when the DUT is subjected to high voltages or it commutates at high frequency [23].

The clamping–sensing network N.4 is based on a current mirror and the two diodes ${\mathrm{D}}_{\mathrm{A}}$ and ${\mathrm{D}}_{\mathrm{B}}$. The functioning of the network assumes that ${\mathrm{D}}_{\mathrm{A}}$ and ${\mathrm{D}}_{\mathrm{B}}$ work exactly at the same working point. Hence a mismatch in the mirror transistors could involve different currents in the two branches, thus producing a measurement offset [23,24]. A second aspect that could decrease the accuracy of the measurement is that a large mirror current influences the voltage drops of the diodes due to a self-heating effect [24]. The use of this topology ensures the highest measurement accuracy and the smallest sensing delays. The output of the circuit is between nodes A and B, so a differential voltage probe is mandatory to correctly read the voltage. Another source of measurement error can be the common mode superimposed at the output. For this reason, the probe’s input amplifier must have a high CMRR. The DUT maximum switching frequency for which this topology can sense is determined by the bandwidth of the differential probe itself.

Network N.5 is thought of as the evolution of N.3 to contain only passive components. The MOSFET transistor is substituted by a capacitor, which stores the charges through the ${\mathrm{D}}_1$-${\mathrm{R}}_{\mathrm{C}\mathrm{H}\mathrm{A}\mathrm{R}\mathrm{G}\mathrm{E}}$ path and releases them during the on the state through the ${\mathrm{R}}_{\mathrm{D}\mathrm{R}\mathrm{I}\mathrm{V}\mathrm{E}}$-${\mathrm{D}}_2$ path. The key components of this network are ${\mathrm{D}}_1$ and ${\mathrm{D}}_2$, two high-voltage, fast-switching zero recovery SiC Schottky diodes, which allow the circuit to work up to 400 kHz. This network introduces an offset to the measurement consisting of the ${\mathrm{D}}_2$ forward voltage. The drawback of the network is that the forward current is provided by the energy storage of the capacitor, so it has a decreasing trend that reduces the measurement accuracy [24,25].

The network N.6 clamps the off voltage using a resistive voltage divider. The two resistances (${\mathrm{R}}_1$, ${\mathrm{R}}_2$) must be chosen to ensure correct clamping only when the DUT is off:

$${\mathrm{V}}_{\mathrm{C}\mathrm{C}}\frac{{\mathrm{R}}_2}{{\mathrm{R}}_1+{\mathrm{R}}_2}>{\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}+{\mathrm{V}}_{\mathrm{f}\mathrm{D}1}$$

(18)

This is the only network that takes advantage of a buffer configuration to reduce the ringing of the output node voltage. The frequency capability of the circuit therefore also depends on the bandwidth of the OpAmp. The main frequency limitation comes from the capacitive contribution at node A, because the discharge of the node at the beginning of the on-state is faster when ${\mathrm{C}}_{\mathrm{A}}$ is small [22]. Like networks N.3 and N.5, this network also contains the free-wheeling diodes (${\mathrm{D}}_2$, ${\mathrm{D}}_3$, ${\mathrm{D}}_4$) that work during the DUT’s off-state. To increase the frequency capability, ${\mathrm{D}}_2$ must be a Schottky diode with a low-value junction capacitance, since the output is clamped for a small transient to its negative forward voltage. This topology can provide the correct on-state voltage measurement about 50 ns after the current reaches the load value [22].

The topology N.7 can work at switching frequencies up to 1 MHz [24]. The optimized version of the circuit, with low parasitic capacitance devices, provides the correct on-state voltage 100 ns after the switching. The isolation approach allows for an increase in sensing accuracy thanks to the diode’s differential voltage drop measure. The diode self-heating effect is reduced thanks to ${\mathrm{D}}_4$ by setting a constant current source of a few milliamps. The two freewheeling diodes, ${\mathrm{D}}_6$ and ${\mathrm{D}}_3$, are chosen with very low parasitic capacitances. The double isolation improves the topology’s frequency response, thanks to the smaller parasitic ESC. The diodes must be chosen with low parasitic capacitance and low reverse recovery time to increase the frequency response of the topology. The clamping mechanism is ensured also for test voltages higher than 600 V. The ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ evaluation requires a low-voltage differential probe to measure the ${\mathrm{V}}_{\mathrm{f}\mathrm{D}2}$. The measurement accuracy is based on the hypothesis that the two insulating diodes exhibit the same characteristic sharing the same forward current. The paper [24] also suggested measuring the voltage at node B using a low-voltage probe with a 1:1 attenuation, thus rejecting background noise and increasing accuracy.

Table 1. Sensing–Clamping networks comparison.

Network	Based on	Max Voltage	External Source	Probe Type	Advantages	Weakness
Figure 3	Zener diode	No	No	passive	Minimal circuit Low ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T},\mathrm{O}\mathrm{F}\mathrm{F}}$	Lowest switching capability Trade-off between the measurement offset and the power dissipation on R
Figure 4	transistor	600 V	8 V	passive	Minimal circuit High switching capability	Reduced resolution due to the induced spikes on the ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$
Figure 5	transistor	600 V	8 V	passive	High switching capability	Trade-off between the clamped voltage and the voltage spikes on ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ Strictly working conditions may make the components work out of their SOA
Figure 6	diode	300 V	5 V	differential	No measuring offset Fast switching between clamping–sensing modes	High bandwidth and CMRR, low voltage differential voltage probe required
Figure 7	SiC diode	600 V	No	passive	Passive components only No ext. voltage supply High switching capability	Switching capability strictly depends on the properties of the SiC diodes
Figure 8	resistor		15 V	passive	Lowest ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ ringing noise, thanks to the filter circuit High switching capability	Non-minimal circuit ${\mathrm{D}}_2$ dependent switching capability
Figure 9	diode	650 V	5 V	differential	High switching capability High measurement accuracy	Non-minimal circuit Differential voltage probe required

reports the main information related to the different Sensing–Clamping networks discussed before. Moreover, the table also reports the main advantages and weak points of the different networks.

The choice of the sensing network to be adopted for the investigation depends on the applicative DUT’s working conditions. The setup of Figure 2 is useful to quantify the current collapse’s effects since it is possible to set the current flowing through the DUT, the off-state voltage stress, and the switching parameters of the driver. The sensing network is chosen based on the compromise between the measurement reliability and circuital complexity: the network N.3 is a low-cost simple circuit, which can quickly provide the ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measure with sufficient accuracy for the analyses to be performed. Furthermore, a SPICE functional simulation of the setup has been executed.

2.3. Test Schematic Simulations

Figure 10 reports the complete schematic adopted for the CC investigation. The basic circuit of Figure 2 is completed by the sensing–clamping network N.3 of Figure 5, connected between the drain-source sensing terminal of the DUT. Moreover, an RC voltage snubber circuit is connected in parallel to the DUT. The snubber is dimensioned to dampen the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}}$ oscillations during the DUT’s switching transients. Those oscillations could reduce the accuracy of the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measurement, also limiting the frequency capability of the sensing network. The high side of the half-bridge, not represented here, is shorted to the drain of the low side to prevent it from unwanted turning on.

This subsection shows SPICE simulations of the complete testing circuit represented in Figure 10. The simulations aim to represent the behavior of the sensing network N.3 (Figure 5) inside the testing circuit. The DUT is 7 mΩ 100 V GaN transistor. Its package case temperature (${\mathrm{T}}_{\mathrm{c}\mathrm{a}\mathrm{s}\mathrm{e}}$) is set at 25 °C and it is driven through a gate resistance of 47 Ω. The simulated test conditions are the most recurring one from

Table 2. Test conditions. To analyze the effect of each quantity, it is varied as reported below while keeping constant the others.

	Test Condition	${\mathbf{V}}_{\mathbf{I}\mathbf{N}}$	${\mathbf{I}}_{\mathbf{I}\mathbf{N}}$	Temperature	Frequency	Duty Cycle
Tested Quantity
${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$		32 V	48 A	25 °C	50 kHz	40%
		48 V
		56 V
${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$		48 V	32 A	25 °C	50 kHz	40%
			48 A
			56 A
			70 A
Temperature		48 V	48 A	−40 °C	50 kHz	40%
				25 °C
				125 °C
Frequency		48 V	48 A	25 °C	30 kHz	40%
					40 kHz
					50 kHz
					70 kHz
					80 kHz
Duty cycle		48 V	48 A	25 °C	50 kHz	15%
						20%
						30%
						40%
						50%

: ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ = 48 V, ${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$ = 48 A, ${\mathrm{f}}_{\mathrm{s}}$ = 50 kHz, D = 40%, and ${\mathrm{T}}_{\mathrm{c}\mathrm{a}\mathrm{s}\mathrm{e}}$= 25 °C.

Figure 11 shows the main waveforms of the simulations, considering the period of the last pulse. These simulations consider only ideal components to provide the functional behavior of the entire circuit, without considering any parasitic elements coming from the circuit layout.

Figure 12 shows the simulated ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ behavior during the on-time interval of a pulse. It is obtained dividing the on-state voltage for the current flowing through the DUT. The blue curve is the ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ simulated with the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$, the pink curve is obtained by the ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ from the sensing network. The two curves are perfectly overlapped. It is worth noting that the sensing network N.3 provides the correct ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ estimation using only a few passive components and a single MOSFET. This sensing network is most suitable for the test condition, based on the above compromise, without unnecessarily complicating the test schematic.

3. Experimental Activity

This section firstly describes the characterization board upon which the DUT is soldered, then it shows the designed testing board that realizes the testing schematic, then the resuming table with all the testing conditions is presented. Some considerations regarding the board layout are expressed. Finally, the static and the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measurements are reported, aiming at analyzing how various working conditions differently affect the ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ degradation because of the current collapse. To this aim, the multi-pulse test simulates more realistic working conditions compared to the double-pulse one. The ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ evolution is observed from the first pulse to the last.

3.1. Experimental Setup and Test Conditions

The DUT is the low-side transistor of a STMicroelectronics half-bridge structure encapsulated in a 2SPACK high-performance package. The half-bridge is 3.5–1.5 mΩ monolithic asymmetric, where the low side has lower ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. Both the high side and the low side share the same silicon substrate.

Figure 13 shows the characterization board, properly designed to carry out the current collapse investigation. All the pins on the high and low sides are accessible. Moreover, a dedicated sense lead is realized for each of them through a via (Figure 13b), which contacts the pad directly under the package. The distinction between the force and the sense pin for the same terminal favors a more accurate voltage measurement through the sense pins.

Figure 14 shows the test board that realizes the schematic in Figure 10. It contains nine electrolytic capacitors connected in parallel, which realize the ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$ capacitor; a set of eight load resistors ${\mathrm{R}}_{\mathrm{L}}$, tunable depending on the testing conditions; a thirty-pole connector, where the characterization board is inserted; the sensing network, the driver and the supply, placed in the upper right corner. The driver is an LTC7061, configured to drive only the low-side transistor, supplied between 7 V and the ground. The MOSFET of the sensing network is an STP120NF10, the Zener diode is a BZX55C6V2, and the Schottky are two SMD diodes.

Figure 15 shows a picture of the complete test board. A connector is used to facilitate multiple DUT testing, simply by changing the characterization board. A 1:10 wire transformer is used to read the ${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$ using a 30A TCP 202 current probe.

The driver control signal is a PWM burst of 100 pulses. The number of commutations is sufficient to trigger the charge-trapping mechanism, allowing current collapse to be observed. The ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measured at the last commutation is representative of the maximum ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. The difference between the maximum ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ and the ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ of the first pulse represents the ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ degradation for the test in question.

Table 2 contains all the test conditions reported in this article. The investigation covers five types of stress conditions: voltage, current, temperature, frequency, and duty cycle. The investigation characterizes the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ dependence from the analyzed stress conditions, holding all the others. The testing conditions are determined considering the typical working conditions of the transistors, the performances of the sensing network and the characteristics of the board.

One observation regarding the ${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$ for all the tests: it is obtained as ${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$ = ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$/(${\mathrm{R}}_{\mathrm{L}}$ + ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$). The ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$ capacitor is used to keep constant the ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ during the test window; moreover, ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$ is the charge tank that provides instant current to the DUT during the commutations. The sizing of ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$ considers the test conditions in Table 2 and the maximum voltage variation ∆V allowed, according to (19):

$${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}=\frac{{\mathrm{I}}_{\mathrm{I}\mathrm{N}}\mathrm{D}}{∆\mathrm{V}{\mathrm{f}}_{\mathrm{s}}}$$

(19)

where D is the duty cycle and ${\mathrm{f}}_{\mathrm{s}}$ is the switching frequency. According to (19), the worst-case ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$ to provide 48 A current, with a frequency of 30 kHz and D = 40%, with a voltage variation of 50 mV is: ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$ ≃ 12.8 mF. The testing board contains more electrolytic capacitors connected in parallel, obtaining a ${\mathrm{C}}_{\mathrm{S}\mathrm{T}\mathrm{O}\mathrm{C}\mathrm{K}}$ = 36.3 mF.

Bench-top equipment.

• two GPS 3303 Laboratory DC power supply (30 V/3 A)
• one TDK-Lambda GEN 80–65 Programmable DC power supply (80 V/65 A)
• one Keithley 2450 Source Measure Unit (200 V/1 A)
• one Tektronix AFG 3021C Arbitrary function generator
• one Tektronix TDS 5054 Digital phosphor oscilloscope (500 MHz)
• one Tektronix TCP 202 Current probe (30 A)
• one X-Stream 4300 Thermostream (−80 °C to 225 °C)

3.2. Experimental Measurements

Static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measurements provide the reference value for evaluating the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ degradation for each sample. The static measurements are performed by applying a ${\mathrm{V}}_{\mathrm{G}\mathrm{S}}$ = 7 V to statically turn on the samples. A sense current of 500 mA is forced through the DUT by a Keithley 2450 SMU, which also reads its ${\mathrm{V}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. Figure 16 shows the distribution of the static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measurements. The CC would involve a reduction of the slope on the DC output characteristic of the devices.

The static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ mean value is ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ = 1.51 mΩ.

Figure 17 shows the waveforms representing a switching period of the following test condition: ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}$ = 48 V, ${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$ = 48 A, ${\mathrm{f}}_{\mathrm{s}}$ = 50 kHz, D = 40%, and ${\mathrm{T}}_{\mathrm{c}\mathrm{a}\mathrm{s}\mathrm{e}}$ = 25 °C. The external temperature of the case is controlled using the Thermostream. The waveforms are related to the hundredth state commutation and represent, respectively, the ${\mathrm{V}}_{\mathrm{G}\mathrm{S}}$ (yellow waveform), the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}}$ (blue waveform), the ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ (pink waveform), and the ${\mathrm{I}}_{\mathrm{I}\mathrm{N}}$ current flowing through the device (green waveform). Regarding the sensing network, the gate of the transistor M is driven by ${\mathrm{V}}_{\mathrm{C}\mathrm{C}}$ = 7 V and ${\mathrm{V}}_{\mathrm{M},\mathrm{t}\mathrm{h}}$ ≈ 3 V. The rising and falling edges of the ${\mathrm{V}}_{\mathrm{G}\mathrm{S}}$ have been slowed down, in particular the falling one, adopting two different gate resistances to reduce the overvoltage on the ${\mathrm{V}}_{\mathrm{D}\mathrm{S}}$ during the transition to the off-state (Figure 17b).

During the clamping time interval, when the DUT is off, the simulated ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ showed in Figure 11c is higher than the measured ${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ (Figure 17c) since, according to (6), the transistor M of the simulation has a lower ${\mathrm{V}}_{\mathrm{M},\mathrm{t}\mathrm{h}}$.

In the following, the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ measured for five devices under various test conditions is reported. In particular, the working conditions of Table 2 have been considered.

For each device, a comparison with the static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ is also reported to effectively analyze the impact of the working conditions on the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. To this aim the increment of ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ has been evaluated as follows:

$$∆\mathrm{r}=\frac{{\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}.\mathrm{d}\mathrm{y}\mathrm{n}\mathrm{a}\mathrm{m}\mathrm{i}\mathrm{c}}-{\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}.\mathrm{s}\mathrm{t}\mathrm{a}\mathrm{t}\mathrm{i}\mathrm{c}}}{{\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}.\mathrm{d}\mathrm{y}\mathrm{n}\mathrm{a}\mathrm{m}\mathrm{i}\mathrm{c}}}\mathrm{\%}$$

(20)

The values of the static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ are reported in

Table 3. Static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ (mΩ) of the tested device at room temperature and extreme operating temperature.

${\mathbf{T}}_{\mathbf{c}\mathbf{a}\mathbf{s}\mathbf{e}}$	Dev 1	Dev 2	Dev 1	Dev 1	Dev 1
−40 °C	1.025	1.013	0.995	1.019	0.995
25 °C	1.53	1.512	1.485	1.521	1.485
125 °C	3.075	3.039	2.985	3.057	2.985

for different temperatures.

Figure 18, Figure 19, Figure 20, Figure 21 and Figure 22 report the values of the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ for various device and different working conditions (Table 2). Hence, each figure reports the effect of a single quantity variation since the others are kept constant. The resistance variation, $\mathsf{\Delta }\mathrm{r}$, with respect to the static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ is also reported for each device to better highlight the effect of the single quantity. Considering that the static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ increases with the temperature, $\mathsf{\Delta }\mathrm{r}$ is calculated at the same temperature to effectively evaluate the effect of temperature on the current collapse phenomenon.

The figures highlight the fact that the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ increases with an increasing input voltage (Figure 18) and switching frequency (Figure 21), while it strongly decreases as the duty cycle increases (Figure 22). These results are in accordance with the literature.

The increment of the input voltage involves a higher voltage across the device during the off-time and the turn-on. Thus, it negatively impacts the dynamic value since it empowers the off-state and hot-electrons trapping.

The increment of the switching frequency for a given duty cycle or the reduction of the duty cycle for a given frequency involves a reduction of the on-time. Considering that, as the device starts to conduct the carriers are partially removed also by the flowing current, the reduction of the on-time implies lessening the recombination of the trapped charges, thus more charges in the channel imply greater dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. Additionally, the off-time increases if the on-time is reduced. Considering that during the off-time one of the two trapping mechanisms occurs, the increment of the off-time also involves an increment of the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. Therefore, both phenomena concurrently entail the increment of the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ as highlighted in Figure 21 and Figure 22.

The effect of the input current (Figure 19) is almost negligible for all the devices. The effect of the current is affected by the other operating conditions and by the specific device family. The increment of the current enhances the aforementioned recombination phenomenon, thus pushing toward a dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ reduction. On the other hand, a larger current during the turn-on empowers the hot-trapping phenomenon, thus involving a dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ raise. Considering that varying the input current does not involve substantial dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ variation in all the tested devices, it follows that for this family—and the set test conditions—the two opposite phenomena compensate each other.

The results in Figure 20 seem contradictory since the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ increases as the temperature increases (Figure 20a) but the increment of the dynamic compared to the static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$, $\mathsf{\Delta }\mathrm{r}$, reduces as the temperature increases (Figure 20b). In the literature, it is usually reported an increase of the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ with increasing temperature, thus it seems that the information in Figure 20a is more valuable. However, such an approach is strongly reductive because it focuses on the dynamic value only, which is of interest only in terms of conduction losses increment in comparison to the one expected when the static one is considered. Therefore, the most important information is reported in Figure 20b, which shows that the ratio between dynamic and static ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ reduces with increasing temperature. In other words, an increment in the temperature does not exacerbate the current collapse phenomenon; rather, it mitigates the phenomenon.

4. Conclusions

This paper has first revised some sensing techniques for dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ evaluation and related sensing networks for selecting the best one in relation to the specific automotive grade GaN family to be investigated. The choice has considered an optimal compromise among measurement reliability, circuital complexity, and cost. Moreover, the networks suitability for mass experimental test has been also considered. The selected measurement system has been adopted for analyzing the effect of the working conditions on the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$. The results highlight that the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$ increases with increasing input voltage and switching frequency while it decreases as the duty cycle increases. The current does not have an appreciable effect, while a temperature increment increases the dynamic ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\mathrm{O}\mathrm{N}}$, although it positively affects the current collapse phenomenon.