Search Results (33)

This study used fresh (young) and old (mature) ginger tissues as model systems to investigate how plant maturity modulates the response to pulsed electric field (PEF), a non-thermal processing technology. Specifically, the influence of tissue maturity on dielectric behavior and its downstream effect on juice yield and bioactive compound extraction was systematically evaluated. At 2.5 kV/cm, old ginger exhibited a pronounced dielectric breakdown effect due to enhanced electrolyte content and cell wall lignification, resulting in a higher degree of cell disintegration (0.65) compared with fresh ginger (0.44). This translated into a significantly improved juice yield of 90.85% for old ginger, surpassing the 84.16% limit observed in fresh ginger. HPLC analysis revealed that the extraction efficiency of 6-gingerol and 6-shogaol increased from 1739.16 to 2233.60 µg/g and 310.31 to 339.63 µg/g, respectively, in old ginger after PEF treatment, while fresh ginger showed increases from 1257.88 to 1824.05 µg/g and 166.43 to 213.52 µg/g, respectively. Total phenolic content (TPC) and total flavonoid content (TFC) also increased in both tissues, with OG-2.5 reaching 789.57 µg GAE/mL and 336.49 µg RE/mL, compared with 738.19 µg GAE/mL and 329.62 µg RE/mL in FG-2.5. Antioxidant capacity, as measured by ABTS^•+ and DPPH^• inhibition, improved more markedly in OG-2.5 (37.8% and 18.7%, respectively) than in FG-2.5. Moreover, volatile compound concentrations increased by 177.9% in OG-2.5 and 137.0% in FG-2.5 compared with their respective controls, indicating differential aroma intensification and compound transformation. Structural characterization by SEM and FT-IR further corroborated enhanced cellular disruption and biochemical release in mature tissue. Collectively, these results reveal a maturity-dependent mechanism of electro-permeabilization in plant tissues, offering new insights into optimizing non-thermal processing for functional food production. Full article

In this study, we analyzed the electrical characteristics of metal–insulator–metal (MIM) capacitors fabricated with reference to insulator (Si_xN_y) thickness and deposition condition. Si_xN_y thicknesses of 650 Å, 500 Å, and 400 Å were used with four different conditions designated as MIM (N content 1.49), NEWMIM (N content 28.1), DAMANIT (N content 1.43), and NIT (N content 0.30), deposited by controlling gas flow and RF power as a function of N content. Capacitor characteristics were evaluated mainly in terms of the relationship between leakage current and breakdown voltage (BV). Current–voltage (I–V) characterizations revealed that a higher N–H/Si–H ratio effectively suppressed trap-assisted leakage conduction and enhanced dielectric robustness under high-field stress. Among the tested conditions, the NEWMIM process demonstrated the most favorable electrical performance with highest N contents. The MIM and NEWMIM conditions proved most effective among the evaluated processes, achieving sufficient BV values (>20 V) for reliable MIM capacitor operation and proposing a process optimization framework for integrating medium-density Si_xN_y–based MIM capacitors (2 fF/µm²) with sufficiently high BV values in the future. Full article

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness of 4 nm. The Al₂O₃ film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10⁻⁷ A/cm² at 1 MV/cm. MoS₂ FETs incorporating this Al₂O₃ gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (V_th) of −0.96 V, a high carrier mobility (μ) of 34.85 cm²·V⁻¹·s⁻¹, and an on/off current ratio exceeding 10⁶. These results highlight the potential of Al₂O₃ in enabling low-power 2D electronic devices for post-Moore applications. Full article

This study develops a high-performance polypropylene (PP) substrate platform by optimizing micro/macrostructures and introduces an efficient catalyst. Key findings include: (1) microstructural analysis identifies ash content impurities (>20 ppm) as triggers for partial discharge-induced insulation failure. PP molecular weights (10⁵–10⁶) with narrower distributions enhance mechanical strength, while functional groups (-CH₂/-CH₃) show no structural variations across samples. (2) Macroscopically, mixed α-β crystal interfaces increase insulation failure risks, necessitating single-crystalline structures. Higher temperatures reduce dielectric constants but increase losses, requiring environmental consideration. Crystallinity positively correlates with DC breakdown strength (443.31 kV/mm at 54.13% crystallinity). (3) Among three endo-donor catalysts, the internal electron donor 3-based catalyst achieved optimal die-test activity (47.7 kg PP/g cat·h). With 20 mL triethylamine, the catalyst reduced PP ash content by 42.1%, narrowed molecular weight distribution by 31.6%, and increased crystallinity by 8.74%. These results establish microstructure–property relationships for PP capacitors and provide technical guidelines for performance enhancement. The work addresses current limitations in PP evaluation methods and offers a practical strategy for manufacturing high-insulation PP materials through structural control and catalytic optimization. Full article

The performance of enameled wires has an important impact on new energy vehicle motors. The mainstream practice of existing technology is to improve partial discharge inception voltage (PDIV) by doping powder to inhibit corona and increase varnish thickness, the limitations of which are also obvious. Powder doping has the problem of dispersion stability, and increasing the varnish thickness affects the size and power density of the motor. In this paper, a novel insulation structure design was given. The electronic field stress was controlled by using different dielectric constant materials, and the dielectric constants can be controlled by adjusting the free volume of the polymer. Finally, we specifically create a preparation scheme to increase the corona voltage and the PDIV, without a loss of the breakdown margin of the enameled wire, and the simulation results show that the outermost electric field strength of the enameled wire model decreases by 22.11% and the enameled wire breakdown margin increases by 26.85%. Full article

Enhancing the energy storage properties of dielectric polymer capacitor films through composite materials has gained widespread recognition. Among the various strategies for improving dielectric materials, nanoscale coatings that create structurally controlled multiphase polymeric films have shown great promise. This approach has garnered considerable attention in recent years due to its effectiveness. This review examines surface-coated polymer composites used for dielectric energy storage, discussing their dielectric properties, behaviors, and the underlying physical mechanisms involved in energy storage. The review thoroughly examines the fabrication methods for nanoscale coatings and the selection of coating materials. It also explores the latest advancements in the rational design and control of interfaces in organic–inorganic, organic–organic, and heterogeneous multiphase structures. Additionally, the review delves into the structure–property relationships between different interfacial phases and various interface structures, analyzing how nanoscale coatings the impact dielectric constant, breakdown strength, conduction and charge transport mechanisms, energy density and efficiency, thermal stability, and electrothermal durability of polymeric capacitor films. Moreover, the review summarizes relevant simulation methods and offers computational insights. The potential practical applications and characteristics of such nanoscale coating techniques are discussed, along with the existing challenges and practical limitations. Finally, the review concludes with a summary and outlook, highlighting potential research directions in this rapidly evolving field. Full article

The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs on 6-inch sapphire substrates using a CMOS-compatible process. A 1.5 µm thin GaN buffer layer with excellent uniformity and a 20 nm in situ SiN gate dielectric ensured uniformly distributed V_TH and R_ON across the entire 6-inch wafer. The fabricated devices with an L_GD of 30 µm and W_G of 36 mm exhibited an R_ON of 18.06 Ω·mm and an off-state breakdown voltage of over 3 kV. The electrical mapping visualizes the high uniformity of R_ON and V_TH distributed across the whole 6-inch wafer, which is of great significance in promoting the applications of GaN power HEMTs for medium-voltage power electronics in the future. Full article

As consumer electronics and industrial control systems continue to evolve, the operating temperature range of capacitors is gradually increasing. Barium titanate-based ceramic capacitors are widely used in the field of high dielectrics, so temperature-stable barium titanate-based dielectric materials have been a hot research topic in the field of dielectric ceramics. The construction of a core–shell structure by unequal doping is an effective way to obtain temperature-stable dielectric materials. At the same time, this structure retains part of the highly dielectric tetragonal phase, and materials with overall high dielectric constants can be obtained. In this work, we prepared BaTiO₃-xNaNbO₃-0.002Gd₂O₃ (x = 1.0–6.0 mol%) as well as BaTiO₃-0.05NaNbO₃-yGd₂O₃ (y = 0–0.30 mol%) dielectric ceramics. On the basis of high-electronic-bandgap NaNbO₃-modified BaTiO₃ dielectric ceramics, a core–shell structure with a larger proportion of core phase was obtained by further doping the amphiphilic rare-earth oxide Gd₂O₃. By designing this core–shell structure, the temperature stability range of capacitors can be expanded. At a doping level of 5.0 mol% NaNbO₃ and 0.20 mol% Gd₂O₃, the room temperature dielectric constant ε_r = 4266 and dielectric loss tan δ = 0.95% conforms to the X8R standard (from −55 °C to 150 °C, TCC < ±15%); volume resistivity ρ_v = 10,200 GΩ·cm and breakdown strength E_b = 13.5 kV/mm is attained in BaTiO₃-based ceramics. The system has excellent dielectric and insulating properties; it provides a new solution for temperature-stable dielectric ceramics. Full article

A Dielectric Elastomer Actuator (DEA) consists of electrodes with a dielectric layer between them. By controlling the design of the electrodes, voltage, and frequency, the operating range and speed of the DEA can be adjusted. These DEAs find applications in biomimetic robots, artificial muscles, and similar fields. When voltage is applied to the DEA, the dielectric layer undergoes compression and expansion due to electrostatic forces, which can lead to electrical breakdown. This phenomenon is closely related to the performance and lifespan of the DEA. To enhance stability and improve dielectric properties, a DEA Reservoir layer is introduced. Here, stability refers to the ability of the DEA to perform its functions even as the applied voltage increases. The Reservoir layer delays electrical breakdown and enhances stability due to its enhanced thickness. The proposed DEA in this paper is composed of a Reservoir layer and electrode layer. The Reservoir layer is placed between the electrode layers and is independently configured, not subjected to applied voltage like the electrode layers. The performance of the DEA was evaluated by varying the number of polymer layers in the Reservoir and electrode designs. Introducing the Reservoir layer improved the dielectric properties of the DEA and delayed electrical breakdown. Increasing the dielectric constant through the DEA Reservoir can enhance output characteristics in response to electrical signals. This approach can be utilized in various applications in wearable devices, artificial muscles, and other fields. Full article

Nanopore sensor technology is widely used in biomolecular detection due to its advantages of low cost and easy operation. In a variety of nanopore manufacturing methods, controlled dielectric breakdown has the advantages of a simple manufacturing process and low cost under the premise of ensuring detection performance. In this paper, we have made enhancements to the applied pulses in controlled dielectric breakdown and utilized the improved dielectric breakdown technique to fabricate silicon nitride nanopores with diameters of 5 to 15 nm. Our improved fabrication method offers the advantage of precise control over the nanopore diameter (±0.4 nm) and enhances the symmetry of the nanopore. After fabrication, we performed electrical characterization on the nanopores, and the IV characteristics exhibited high linearity. Subsequently, we conducted detection experiments for DNA and protein using the prepared nanopores to assess the detection performance of the nanopores fabricated using our method. In addition, we also give a physical model of molecule translocation through the nanopores to give a reasonable explanation of the data processing results. Full article

This work studies the direct current breakdown characteristics of unfilled epoxy and epoxy nonconductive nanocomposites (${\mathrm{S}\mathrm{i}\mathrm{O}}_2,\mathrm{M}\mathrm{g}\mathrm{O}$ and ${\mathrm{A}\mathrm{l}}_2{\mathrm{O}}_3$). It also examines the variation of electrical properties in epoxy nanocomposites. The novel aspect of this study is that the samples of Epoxy nanocomposite were exposed to high voltages of up to six kilo volts for three hours using field electron microscopy under high vacuum conditions (${10}^{-5}$ mbar). The current emitted from these samples was measured at three different intervals of time. In addition, the influence of high voltage on the permittivity, loss factor (tan(δ)), and conductivity of the epoxy nanocomposite was studied. This evaluation was conducted before and after applying the voltage at room temperature, The frequency range extends from ${10}^{-2}$–${10}^{-7}$ Hz using the Novo Control Alpha-A analyzer. Current–voltage characterization was performed through field electron microscopy. The samples were characterized by scanning electron microscopy–energy dispersive X-ray spectroscopy and Fourier Transform Infrared Spectroscopy. The unfilled epoxy exhibited structural degradation, resulting in the formation of holes when exposed to high voltages of up to six kilo volts, leading to a reduction in electrical properties. Nevertheless, the addition of nanoparticles shows a significant increase in the operational lifetime of the epoxy nanocomposite. The degree of increase in the lifetime of epoxy composite varied depending on several factors such as the type of NPs introduced and their respective sizes. The epoxy/${\mathrm{A}\mathrm{l}}_2{\mathrm{O}}_3$ nanocomposite comparing with epoxy/MgO and epoxy/${\mathrm{S}\mathrm{i}\mathrm{O}}_2$ nanocomposite showed elevated resistance to direct current breakdown strength and maintaining its dielectric. Full article

Electrowetting with a dielectric layer is commonly preferred in practical applications. However, its potential is often limited by factors like the properties of the dielectric layer and its breakdown, along with the complexity of the deposition method. Fortunately, advancements in 3D inkjet printing offer a more adaptable solution for making patterned functional layers. In this study, we used a negative photoresist (HN-1901) to create a new dielectric layer for an electrowetting display on a 3-inch ITO glass using a Dimatix DMP-2580 inkjet printer. The resulting devices performed better due to their enhanced resistance to dielectric breakdown. We meticulously investigated the physical properties of the photoresist material and printer settings to achieve optimal printing. We also controlled the uniformity of the dielectric layer by adjusting ink drop spacing. Compared to traditional electrowetting display devices, those with inkjet-printed dielectric layers showed significantly fewer defects like bubbles and electrode corrosion. They maintained an outstanding response time and breakdown resistance, operating at an open voltage of 20 V. Remarkably, these devices achieved faster response times of ton 22.3 ms and toff 14.2 ms, surpassing the performance of the standard device. Full article

Class II ceramics are a material with high permittivity but low reliability of their capacitance and bias voltage due to high the temperature sensitivity of their dielectric permittivity. In this work, a BST-based (Ba_0.9−xSr_xCa_0.1)TiO₃·0.03(Bi₂O₃·3TiO₂) (x = 0.2, 0.25, 0.3, 0.35, 0.4) composition with Y5U characteristics was investigated through compositional control to develop high-permittivity and voltage-stable ceramic compositions. Sr doping can increase the breakdown strength (E_b) but decreases the Curie temperature (T_c). The composition at x = 0.3 can obtain optimal comprehensive electrical properties, with high permittivity of 4206, low dielectric loss of ~0.009, and moderate breakdown strength (E_b) of 77.6 kV/cm, which meets Y5U specifications. Typically, a low bias-voltage dependence of capacitance is confirmed with a variation rate of 7.64% under 20 kV/cm. This strategy provides a promising candidate for high-permittivity Class II ceramic dielectrics that can be used in this field. Full article

Two-dimensional (2D) materials, characterized by their atomically thin nature and exceptional properties, hold significant promise for future nano-electronic applications. The precise control of carrier density in these 2D materials is essential for enhancing performance and enabling complex device functionalities. In this study, we present an electron-beam (e-beam) doping approach to achieve controllable carrier doping effects in graphene and MoS₂ field-effect transistors (FETs) by leveraging charge-trapping oxide dielectrics. By adding an atomic layer deposition (ALD)-grown Al₂O₃ dielectric layer on top of the SiO₂/Si substrate, we demonstrate that controllable and reversible carrier doping effects can be effectively induced in graphene and MoS₂ FETs through e-beam doping. This new device configuration establishes an oxide interface that enhances charge-trapping capabilities, enabling the effective induction of electron and hole doping beyond the SiO₂ breakdown limit using high-energy e-beam irradiation. Importantly, these high doping effects exhibit non-volatility and robust stability in both vacuum and air environments for graphene FET devices. This methodology enhances carrier modulation capabilities in 2D materials and holds great potential for advancing the development of scalable 2D nano-devices. Full article

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS₂), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS₂ transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS₂ transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm²/V·s), on/off current ratio (from 4.90 × 10⁵ to 1.52 × 10⁷), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS₂ transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS₂ transistor array. Full article