Search Results (36)

This paper presents a fully integrated three-stage stacked power amplifier (PA) operating in the K-/Ka-band, fabricated using a TSMC 65 nm CMOS process for fifth-generation (5G) millimeter-wave applications. To improve the output power without sacrificing reliability, a two-stacked-FET configuration is adopted in the power stage, which distributes the voltage stress across series-connected transistors and permits a higher supply voltage than a conventional cascode structure. A differential topology with capacitive neutralization is employed in both the common-source driver stage and the stacked power stage. The neutralization capacitance is determined from a stability- and gain-oriented analysis based on the Rollett stability factor (K) and the maximum available gain (MAG), which clarifies the trade-off between feedback cancelation and wideband gain flatness over the operating band. The fabricated PA occupies a total chip area of 0.51 mm², including pads, with a core area of 0.18 mm². The measurement results demonstrate a measured 3 dB bandwidth of 6.7 GHz from 24.6 GHz to 31.3 GHz, a peak small-signal gain of 32.9 dB, a saturated output power of 20.8 dBm, an output 1 dB compression point of 16 dBm, and a peak power-added efficiency of 20.4% at 28.5 GHz. Over the 26–30 GHz range in which the large-signal characterization was performed, the saturated output power varies by less than 1 dB and the efficiency by less than 2 percentage points, indicating that the combination of capacitive neutralization and stacked-FET operation provides a compact solution for wideband K-/Ka-band CMOS power amplification. Full article

This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this study demonstrates that, when combined with self-cascode structures, BD architectures achieve competitive intrinsic gain, enhanced input common-mode range, and improved slew rate efficiency under nanoampere bias conditions. To support these claims, closed-form analytical derivations, dynamic analysis, and comprehensive Monte Carlo and PVT simulations are provided to quantify robustness and mismatch sensitivity. The results establish a systematic framework for evaluating BD versus GD architectures under identical technology and power constraints, offering practical design guidelines and optimized self-cascoded topologies for next-generation energy-autonomous systems. Full article

This work introduces a trimming technique based on eTrim technology to minimize both the input-referred offset voltage and its temperature drift in the operational amplifiers. The proposed low-voltage op-amp utilizes the body effect to maintain a constant bandwidth across the rail-to-rail input common-mode range under low supply voltages. During input common-mode transitions, the current in the folded cascode stage remains stable, ensuring a robust output stage. Furthermore, a specialized gain-boosting structure enhances the low-frequency gain while preventing occasional latch-up during low-voltage power-up. A pin-multiplexing scheme is employed for trimming data input, thereby eliminating the need for dedicated trimming pins and mitigating post-package parameter variations. At room temperature, a constant-current injection mechanism reduces the DC offset to microvolt levels. At high temperature, temperature-compensated current injection cancels the first-order drift component. Implemented in a low-voltage operational amplifier, post-layout simulation results demonstrate that with a 100-pF capacitive load, the amplifier achieves a gain–bandwidth product exceeding 10 MHz, a low-frequency gain greater than 140 dB, and an input-referred noise of 2.54 µVp-p for the P-channel input and 3.95 µVp-p for the N-channel input. The trimming process reduces the residual offset to the microvolt range and effectively suppresses offset drift, ensuring accurate offset compensation across the specified temperature range. Full article

This paper proposes a Cascode phase compensation network structure for controlling Buck–Boost converters to achieve wide-bandwidth and high-speed operation. The proposed scheme relocates the compensation capacitor (C_C) from the traditional position “across the first-stage output and the second-stage output” to a new position “between the source of the first-stage Cascode common-gate transistor and the second-stage output.” By integrating their high common-mode rejection ratio and power supply rejection ratio, a global system loop with robust interference immunity is constructed. The results indicate that a dominant-pole frequency of 10 kHz is achieved with our proposed structure compared to the circuit without Cascode compensation, representing a tenfold increase. As a result, a phase margin (PM) of up to 58.36° is achieved, which is improved by 9.1%. This work can provide an effective reference for achieving stable and rapidly responsive power conversion. Full article

The dramatic growth in the emerging optical applications, including Lidar, short-range optical communication, and optical integrated sensing and communication (ISAC) calls for high-bandwidth transimpedance amplifiers (TIA) with low noise and low power in advanced CMOS technology nodes. To address the issues of existing TIA design, including the conventional RGC structure and the dual-feedback regulated cascode (RGC) TIA, design with complex feedback paths, i.e., limited bandwidth, extra noise, and high power consumption for enough bandwidth, this paper presents a novel TIA with the following key contributions. A novel RGC structure with cascode-feedback is proposed to increase feedback gain, thereby extending bandwidth and reducing noise. Design strategy of the proposed RGC TIA in a low-power advanced CMOS process is carried out to exploit weak inversion operation to achieve better power efficiency. Frequency response and noise analysis are also conducted to achieve target bandwidth and noise performance. The proposed TIA is designed and simulated in 40 nm CMOS with a target PD capacitance of 0.15 pF, achieving a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ. The average input-referred noise current spectral density is 18.3 pA/$\sqrt{\mathrm{H}\mathrm{z}}$. Operating at 1.2 V, the core circuits consume only 6.6 mW, excluding the output buffer. Compared with prior RGC TIA designs, the proposed TIA achieves a 7.4×~243× enhancement in figure of merit. Full article

This work presents a direct conversion transmitter (DCT) for 5G new radio (NR) that eliminates the RF driver by directly feeding a single stage cascode PA through a baseband buffer amplifier and passive up-conversion mixer. The baseband interface uses Class-AB buffers to hold the output capacitor voltage, enabling accurate sampling at the PA input. A mixer switch is selected for minimal on-resistance variation over the required baseband swing. The PA is designed with separate I and Q voltage inputs and a current summing structure. The PA operates at 2.5 V; other blocks use 1.2 V. Post-layout two-tone simulations at 5 GHz indicate 21 dBm output saturation power and −36.1 dBc of IMD3 at 9 dB PBO power while removing the driver to inter stage matching network of a two-stage design. The results validate a compact, driverless architecture for integrated transmitters. Full article

A series of problems, such as material damage and charge trap, can be caused when GaN HEMT power devices are subjected to high field stress in the off-state. The reliability of GaN HEMT power devices affects the safe operation of the entire power electronic system and seriously threatens the stability of the equipment. Therefore, it is particularly important to study the damage mechanism of GaN HEMT power devices under high field conditions. This work studies the degradation of Cascode GaN HEMT power devices under off-state high-field stress and analyzes the related damage mechanism. It is found that the high field stress in the off-state will generate a positive charge trap in the oxide layer of the MOS device in the cascade structure. Moreover, defects occur in the barrier layer and buffer layer of GaN HEMT devices, and the threshold voltage of Cascode GaN HEMT power devices is negatively shifted, and the transconductance is reduced. This study provides an important theoretical basis for the reliability of GaN HEMT power devices in complex and harsh environments. Full article

This paper presents a wide-tuning-range, low-power tunable active inductor (AI) designed and fabricated using 130 nm CMOS technology with six metal layers. To achieve high performance with a relatively small silicon area and low power consumption, the AI structure is carefully designed and optimized using a cascode stage, a feedback resistor, and multi-gate finger transistors. In the proposed circuit topology, inductance tuning is realized by adjusting both the bias current and the feedback resistor. The performance of the circuit is evaluated in terms of tuning range, quality factor, power consumption, and chip area. The functionality of the fabricated device is experimentally validated, and the fundamental characteristics of the active inductor are measured over a wide frequency range using a Cascade GSG probe, with results compared to simulations. Experimental measurements show that, under a 1 V supply, the AI achieves a self-resonant frequency (SRF) of 3.961 GHz and a quality factor (Q) exceeding 1586 at 2.383 GHz. The inductance is tunable between 6.7 nH and 84.4 nH, with a total power consumption of approximately 2 mW. The total active area, including pads, is 345 × 400 µm². Full article

The advent of CMOS power amplifiers has enabled compact and cost-effective solutions for RF applications. Among the available options, switching amplifiers are the most competitive due to their superior efficiency. In this paper, we present the design of a fully integrated 130 nm CMOS class-E RF power amplifier optimized for 2.4 GHz ISM band operations that is compliant with the Bluetooth Low Energy (BLE) standard. The amplifier is based on a cascode configuration with charging acceleration capacitance and a combination of standard and high-voltage (HV) MOSFETs, ensuring optimal performance while maintaining device reliability. To identify the best configuration for the proposed circuit, we first provide an overview of basic class-E amplifier operations and critically review optimization techniques proposed in the scientific literature. This review is complemented by a numerical analysis of the potential advantages of using a combined standard-HV MOSFET structure. Post-layout simulations with parasitic parameter extraction demonstrated that the amplifier achieves 40.85% Power Added Efficiency and 20.52 dBm output power. Full article

This paper presents a high-gain multi-input low-noise amplifier (LNA) design aimed at achieving stable phase and minimal noise within a flexible gain range for modern wireless communication systems. The proposed LNA, designed using a CASCODE architecture and implemented in a 65 nm silicon-on-insulator (SOI) process, demonstrates significant improvements in isolation, noise reduction, and miniaturization. The SOI process reduces parasitic capacitance, enhancing performance and thermal/electrical isolation, critical for high-frequency applications. The CASCODE structure minimizes unwanted coupling between stages, enhancing signal integrity and maintaining stable operation across multiple gain modes. The LNA operates in the 2.3 GHz to 2.69 GHz frequency band and supports seven gain modes. It achieves a maximum gain of 21.45 dB with a noise figure of 1.03 dB at the highest gain mode. Notably, it maintains phase stability within 16.4 degrees across the entire gain range, ensuring consistent phase alignment, which is crucial for applications requiring precise signal alignment. The design eliminates the need for switching mechanisms typically used in conventional LNAs, which often introduce additional noise. This work demonstrates that the CASCODE-based multi-input LNA, implemented in a 65 nm SOI process, successfully meets the rigorous demands of high-frequency communication systems, achieving an optimal balance between gain flexibility, noise reduction, and stable phase control within a 32 dB gain range. Full article

This paper proposes a three-stage op amp based on the SOI (silicon-on-insulator) process, which achieves a low offset voltage and temperature coefficient across a wide temperature range from −40 °C to 250 °C. It can be used in aerospace, oil and gas exploration, automotive electronics, nuclear industry, and in other fields where the ability of electronic devices to withstand high-temperature environments is strongly required. By utilizing a SC (Switched Capacitor) notch filter, the op amp achieves low input offset in a power-efficient manner. The circuit features a multi-path nested Miller compensation structure, consisting of a low-speed channel and a high-speed channel, which switch according to the input signal frequency. The input-stage operational amplifier is a fully differential, rail-to-rail design, utilizing tail current control to reduce the impact of common-mode voltage on the transconductance of the input stage. The two-stage operational amplifier uses both cascode and Miller compensation, minimizing the influence of the feedforward signal path and improving the amplifier’s response speed. The prototype op amp is fabricated in a 0.15 µm SOI process and draws 0.3 mA from a 5 V supply. The circuit occupies a chip area of 0.76 mm². The measured open-loop gain exceeds 140 dB, with a 3 dB bandwidth greater than 100 kHz. The amplifier demonstrates stable performance across a wide temperature range from −40 °C to 250 °C, and exhibits an excellent input offset of approximately 20 µV at room temperature and an offset voltage temperature coefficient of 0.7 μV/°C in the full temperature range. Full article

This paper presents a thorough robust Class-AB power amplifier design and its application in pressure-mode sensor-on-chip nonlinearity correction. Considering its use in piezoresistive sensing applications, a gain-boosting-aided folded cascode structure is utilized to increase the amplifier’s gain by a large amount as well as enhancing the power rejection ability, and a push–pull structure with miller compensation, a floating gate technique, and an adaptive output driving limiting structures are adopted to achieve high-efficiency current driving capability, high stability, and electronic environmental compatibility. This amplifier is applied in a real sensor nonlinearity correction on-chip system. With the help of a self-designed 7-bit + sign DAC and a self-designed two-stage operational amplifier, this system is compatible with nonlinear correction at different signal conditioning output values. It can also drive resistive sensors as small as 300 ohms and as high as tens of thousands of ohms. The designed two-stage operational amplifier utilizes the TSMC 0.18 um process, resulting in a final circuit power consumption of 0.183 mW. The amplifier exhibits a gain greater than 140 dB, a phase margin of 68°, and a unit gain bandwidth exceeding 199.76 kHz. The output voltage range spans from 0 to 4.6 V. The final simulation results indicate that the nonlinear correction system designed in this paper can correct piezoresistive sensors with a nonlinearity of up to ±2.5% under various PVT (Process–Voltage–Temperature) conditions. After calibration by this system, the maximum error in the output voltage is 4 mV, effectively reducing the nonlinearity to 4% of its original value in the worst-case scenario. Full article

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs. Full article

A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP_1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP₃) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage. Full article

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively. Full article