A Fully Integrated Direct Conversion Transmitter with I/Q-Isolated CMOS PA for Sub-6 GHz 5G NR

Abstract

This work presents a direct conversion transmitter (DCT) for 5G new radio (NR) that eliminates the RF driver by directly feeding a single stage cascode PA through a baseband buffer amplifier and passive up-conversion mixer. The baseband interface uses Class-AB buffers to hold the output capacitor voltage, enabling accurate sampling at the PA input. A mixer switch is selected for minimal on-resistance variation over the required baseband swing. The PA is designed with separate I and Q voltage inputs and a current summing structure. The PA operates at 2.5 V; other blocks use 1.2 V. Post-layout two-tone simulations at 5 GHz indicate 21 dBm output saturation power and −36.1 dBc of IMD3 at 9 dB PBO power while removing the driver to inter stage matching network of a two-stage design. The results validate a compact, driverless architecture for integrated transmitters.

1. Introduction

In modern wireless communication systems, the implementation of massive MIMO and beamforming has significantly increased the density of antenna channels per module [1,2]. The challenge of integrating RF transceiver blocks within a limited chip area has become a critical issue [3,4].

The 5G NR standard requires user equipment (UE) transmitters to achieve high linearity and adequate output power while maintaining compact size and low power consumption. CMOS technology offers low cost and high integration for RF front-end designs. In modern mobile standards, the transmitter must ensure sufficient output power while maintaining high linearity. To meet gain and drivability requirements under the limited voltage headroom, multi-stage PA architectures are commonly adopted [5,6].

However, a driver stage often introduces drawbacks, such as increased power consumption, larger chip area, and loss due to additional matching networks and inter-stage parasitics.

Figure 1 shows the conventional RF amplifier with driver stage and matching network (shaded in Figure 1a) and the proposed design. While removing the driver amplifier improves compactness, it introduces critical system-level trade-offs. Without the driver, the mixer must directly drive the PA’s large input capacitance, making the linearity sensitive to the switch resistance. Furthermore, the baseband amplifier is burdened with delivering a larger voltage swing to compensate for the reduced RF gain.

This paper presents a fully integrated CMOS transmitter for the sub-6 GHz 5G NR band that removes the RF driver stage. The proposed architecture meets these challenges through the coordinated design of the passive mixer and PA input organization to enable precise sampling.

IQ modulators are fundamentally susceptible to I/Q path imbalance and nonlinear interaction between the in-phase and quadrature branches [7]. Previous analysis highlights that isolating the I and Q paths is critical to minimize unwanted crosstalk and recent studies have explored time domain techniques, such as employing optimized LO duty cycles (e.g., 33%) to enhance harmonic rejection and linearity [8,9].

By physically separating the I and Q inputs at the PA gate, the effective capacitive load seen by each mixer path is halved compared to the shared-path approach. This reduction in capacitance minimizes the charging time constant, thereby suppressing memory effects and improving sampling accuracy. The proposed transmitter delivers a maximum output power of 21 dBm at 5 GHz carrier. At 9 dB back-off, a two-tone test with 100 MHz spacing shows an IMD3 of −36.1 dBc.

2. Transmitter Architecture

Figure 2 shows the overall block diagram of the proposed transmitter. The I/Q baseband signals are each provided as differential inputs. These signals are processed by unity gain Class-AB buffer amplifiers, which preserve the baseband signal while providing sufficient drivability for the following circuits. The Class-AB configuration at the output stage ensures the necessary current drive to handle the capacitive load without distorting the large-swing baseband signals.

A differential 5–5.5 GHz LO is supplied and converted on-chip to quadrature (0°, 90°, 180°, 270°) by a passive poly-phase filter (PPF). Following the PPF, buffer stages shape the LO into rail-to-rail, 50%-duty waveforms and drive the transmission gate (TG) mixer switches. The up-converted RF signals are combined and fed into a single-stage internal PA, which is the maximum power matched to a 50 Ω load.

To aid in the comprehension of the proposed driverless architecture, Figure 3 visually summarizes the overall signal path. The diagram illustrates the sequential evolution of the signal from the differential baseband inputs, through the up-mixer, and finally to the RF output of the PA.

3. Circuit Implementation

3.1. Class-AB Buffer Amplifier

The baseband interface consists of four Class-AB buffer amplifiers, as shown in Figure 4, whose primary function is to hold the baseband output capacitor voltage so that accurate samples are captured at the PA gate through the TG mixer.

Figure 5 shows that the Class-AB output stage enables rail-to-rail swing and high load-driving capability. Device sizing and bias points are optimized to maintain linear operation under large signal conditions while ensuring sufficient slew rate for the maximum expected baseband frequency content. The output stage transistors are sized at 2400 μ/60n (PMOS) and 1440 μ/60n (NMOS) to ensure sufficient drivability.

The quiescent current and bias can be controlled via a 3-bit code that slices the current mirror ratios (*1, *1/2, *1/4). This programmability allows optimization of the gm variation near the zero-crossing point to balance power and linearity.

3.2. Transmission-Gate Switch Passive Mixer

The up-conversion mixer is implemented using TG switches formed by parallel NMOS and PMOS devices, as shown in Figure 6. The primary design objective is to minimize the variation in switch on-resistance over the entire baseband input voltage range. A CMOS transistor operating at triode region can be approximated as a linear resistor as follows:

$${\mathrm{R}}_{\mathrm{o}\mathrm{n}}\approx {\displaystyle \frac{1}{\mathsf{\mu }{\mathrm{C}}_{\mathrm{o}\mathrm{x}}\frac{\mathrm{W}}{\mathrm{L}}\left(\left|{\mathrm{V}}_{\mathrm{G}\mathrm{S}}\right|-\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}}\right|\right)}}$$

(1)

To sustain the required output power of approximately 21 dBm, the baseband swing at the mixer input must span 0.2 to 1.0 V, while the LO drives the switch with 0/1.2 V pulses. Over this full BB range, minimizing the nonlinearity of on-resistance of the passive mixer switch due to gate–source voltage variation is critical to stabilize the conversion gain and to suppress AM-AM/AM-PM distortion. We therefore evaluated three switch options—shown in Figure 7 as (a) PMOS-only, (b) NMOS-only, and (c) Transmission-gate—by sweeping the BB level and extracting Ron.

As shown in Figure 8, the TG switch exhibits the flattest ${\mathrm{R}}_{\mathrm{o}\mathrm{n}}$ profile: 3.37–4.50 Ω ($\Delta {\mathrm{R}}_{\mathrm{o}\mathrm{n}}$ = 1.13 Ω) across a 0.2–1.0 V input range. In contrast, the NMOS switch shows 3.97–8.07 Ω ($\Delta$4.10 Ω), and the PMOS switch degrades severely to 4.55–57.11 Ω ($\Delta$52.56 Ω). The reduced and flattened ${\mathrm{R}}_{\mathrm{o}\mathrm{n}}$ of the TG directly lowers the effective series resistance in the passive up-conversion path, stabilizing the approximate conversion gain relation:

$${\mathrm{G}}_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{v}}\propto {\displaystyle \frac{{\mathrm{R}}_{\mathrm{L}}}{{\mathrm{R}}_{\mathrm{o}\mathrm{n}}+{\mathrm{R}}_{\mathrm{S}}}}$$

(2)

The differential structure driven by in/out-phase LO signals cancels the 5 GHz LO feedthrough at the PA input and layout symmetry is strictly maintained, resulting in LO leakage levels lower than inter-modulated products in two-tone test results.

We evaluated two different IQ up-conversion mixer configurations, as shown in Figure 9, to optimize the performance.

From the time domain sampling viewpoint illustrated in Figure 10, reducing the charging time constant $\mathsf{\tau }\approx \left({\mathrm{R}}_{\mathrm{o}\mathrm{n}}+{\mathrm{R}}_{\mathrm{s}}\right){\mathrm{C}}_{\mathrm{P}\mathrm{A}.\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}$ improves the accuracy of the captured BB samples at the PA gate. Consequently, the TG option is adopted for the proposed mixer.The conversion gain of a passive up-conversion mixer scales with the fundamental coefficient of the LO switching pulse [10]. A 50% duty therefore yields a +3 dB higher fundamental than 25%.

$${\mathrm{A}}_{\mathrm{n}}={\displaystyle \frac{2\mathrm{A}}{\mathrm{n}\mathsf{\pi }}}\sin \left(\mathrm{n}\mathsf{\pi }\mathrm{D}\right),(\mathrm{D}=\mathrm{d}\mathrm{u}\mathrm{t}\mathrm{y} \mathrm{r}\mathrm{a}\mathrm{t}\mathrm{i}\mathrm{o})$$

(3)

$${\displaystyle \frac{{\mathrm{A}}_{1.50\%}}{{\mathrm{A}}_{1.25\%}}}={\displaystyle \frac{\mathrm{s}\mathrm{i}\mathrm{n}\left(\mathsf{\pi }/2\right)}{\mathrm{s}\mathrm{i}\mathrm{n}\left(\mathsf{\pi }/4\right)}}=\sqrt{2}(\approx +3\mathrm{d}\mathrm{B})$$

(4)

When the source behaves low-impedance, the charging time constant, PA gate voltage, and sampling error are

$${\mathsf{\tau }}_{\mathrm{c}\mathrm{h}}\approx \left({\mathrm{R}}_{\mathrm{s}}+{\mathrm{R}}_{\mathrm{o}\mathrm{n}}\right){\mathrm{C}}_{\mathrm{P}\mathrm{A}.\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}+}$$

(5)

$${\mathrm{V}}_{\mathrm{P}\mathrm{A}.\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}\left({\mathrm{T}}_{\mathrm{S}}\right)\approx {\mathrm{V}}_{\mathrm{B}\mathrm{B}}\left(1-{\mathrm{e}}^{-{\mathrm{T}}_{\mathrm{S}}/{\mathsf{\tau }}_{\mathrm{c}\mathrm{h}}}\right)$$

(6)

$${\mathsf{\epsilon }}_{\mathrm{s}}={\mathrm{e}}^{-{\mathrm{T}}_{\mathrm{S}}/{\mathsf{\tau }}_{\mathrm{c}\mathrm{h}}}$$

(7)

Dividing the PA input transistor size in half per path via I/Q splitting halves ${\mathrm{C}}_{\mathrm{P}\mathrm{A},\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}$, reduces ${\mathsf{\tau }}_{\mathrm{c}\mathrm{h}}$, and thus improves sampling accuracy within each sampling time.

In the charge-sharing-limited regime, the final PA gate voltage approaches about

$${\mathrm{V}}_{\mathrm{P}\mathrm{A}.\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}\approx {\displaystyle \frac{{\mathrm{V}}_{\mathrm{B}\mathrm{B}}\cdot {\mathrm{C}}_{\mathrm{B}\mathrm{B}}}{{\mathrm{C}}_{\mathrm{B}\mathrm{B}}+{\mathrm{C}}_{\mathrm{P}\mathrm{A}.\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}}}$$

(8)

Reducing ${\mathrm{C}}_{\mathrm{P}\mathrm{A}.\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}$ can therefore increase the accuracy of captured amplitude.

Under an I/Q-shared path, sequentially sampling I and Q onto a single PA gate can lead to residual charge on the gate node, causing memory-induced degradation of linearity metrics such as EVM. Increasing the baseband shunt capacitor can alleviate this (by making ${\mathrm{C}}_{\mathrm{B}\mathrm{B}}\hspace{0.17em}\gg \hspace{0.17em}{\mathrm{C}}_{\mathrm{P}\mathrm{A},\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}$), but an on-chip capacitor incurs substantial area and shifts the BB output pole to lower frequency, destabilizing the baseband amplifier.

The design reduces the effective ${\mathrm{C}}_{\mathrm{P}\mathrm{A},\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}$ per path through I/Q isolation rather than enlarging thebaseband shunt capacitor. Figure 11 shows that the 50% case exhibits ~6.5 dB higher input power at the PA interface.

3.3. Single-Stage Internal Power Amplifier

The PA is designed for Class-AB operation using a cascode topology, as shown in Figure 12, to improve linearity and power efficiency. The target maximum output power is 21 dBm, considering a 9 dB PAPR and 1.8 dB loss from the output transformer and interconnects.

The cascode structure with a 2.5 V supply is chosen to relieve voltage stress on the 1.2 V core devices while enhancing input–output isolation. The Class-AB bias is fixed to achieve a conduction angle of approximately 1.1 π at maximum power output.

From load-line analysis, the fundamental drain current for this power level is 230 mA with 2.5 VDD, but Class-AB operation produces harmonic components that increase the peak current demand. Allowing for these harmonics, the PA device sizes are optimized to handle up to 250 mA [11].

Accordingly, the cascode PA is implemented with I/Q isolated inputs and current combining at drain.

3.4. Poly-Phase Filter

The LO generator comprises a passive poly-phase filter (PPF) (Figure 13) followed by LO buffer amplifiers. The PPF converts the differential 5–5.5 GHz LO input into four quadrature-phase signals (0°, 90°, 180°, 270°) with a 50% duty cycle. The PPF is designed for constant-phase operation, ensuring that the 90° phase difference between I and Q paths is maintained consistently across the intended operating bandwidth [12].

The following LO buffers are implemented as CMOS inverter chains. As shown in Figure 14, simulations confirm that the quadrature phase mismatch remains below 0.2° (deviation from the ideal 90° spacing) and amplitude variation within 3% (535–548 mV) across 5–5.5 GHz, ensuring robust I/Q orthogonality.

The LO generator consumes approximately 150 mW, primarily due to the large gate capacitance inherent in the 65 nm process. However, since the inverter-based topology follows digital scaling laws ($\mathrm{P}\propto \mathrm{C}{\mathrm{V}}^2\mathrm{f}$), this power is expected to decrease significantly in advanced nodes, offering superior scalability compared to conventional analog drivers.

4. Simulated Results

Figure 15 shows the layout of the proposed transmitter. The internal PA occupies an area of approximately 0.25 mm², and the entire transmitter is fabricated using a 65 nm CMOS process.

The simulation results for the two-tone test and the 5G NR signal are shown in Figure 16. The key performance metrics of the proposed transmitter are compared with prior arts in

Table 1. Comparison table.

Reference	[13] *	[14] *	[15] *	This Work **
Process	65 nm CMOS	40 nm CMOS	65 nm CMOS	65 nm CMOS
Architecture	PA only	Mixer + PA	DA + PA	BB amp + Quadrature LO gen + Mixer + PA
Matching Network with Inductor or XFMR	Input and Output	Inter-stage and Output	Inter-stage and Output	Output Only
Psat [dBm]	16	22	20.1–22.4	21
PAE [%]	14.9–22.5	24.2–28.2	19–28.4	21–21.7 ***
S21 [dB]	10.8–12.4	11.3–11.9	23.6	15.1–15.2
Frequency [Hz]	3–4.2 G/24–28 G	2.4 G/5.5 G	2–6 G	5–5.5 G
Signal Bandwidth [Hz]	50 M	20 M	80 M	100 M

* Measured results/** post-layout simulation results/*** PA standalone.

.

To minimize noise coupling for dual supply domain (1.2, 2.5 V), the layout employs deep N-well isolation and ground guard rings to physically separate the 2.5 V PA domain from the 1.2 V analog blocks. The simulation setup includes EM-modeled bond wire inductances (~800 pH) to account for package parasitics.

Two-tone tests were performed with a signal centered at 5 GHz and a 100 MHz tone spacing. For modulation testing, a 100 MHz 256-QAM signal was applied, targeting 5G NR applications. At 9 dB output back-off, the transmitter achieves an IMD3 of −36.1 dBc in two-tone tests. In the time domain, the modulated RF output signal closely overlaps with the scaled baseband waveform.

To further validate the linearity compliance for 5G NR 256-QAM specifications (EVM < −29.1 dB), we conducted a cross-verification analysis. The standalone PA envelope simulation with the target modulated signal exhibits an EVM of −41.2 dB at 12 dBm of average output power (Figure 17), providing a linearity headroom of over 12 dB against the specification. Also, we analyzed the signal linearity at the PA input node to verify the performance of the driverless interface. The simulation confirms that the signal delivered from the mixer to the PA maintains a low IMD3 of −43.3 dBc at the 9 dB back-off power level with a 100 MHz spaced two-tone test, indicating that the preceding Class-AB buffer and TG mixer introduce negligible distortion. The total power consumption of the transmitter is summarized as follows: the four-channel Class-AB baseband buffer amplifiers consume about 100 mW, while the LO generation and buffering stage consume approximately 150 mW. In terms of efficiency, the standalone PA achieves a peak Power-Added Efficiency (PAE) of 21–21.7%.

Consequently, the combination of the linear input drive and robust PA capability suggests that the proposed architecture is a feasible solution for satisfying the stringent requirements of high-order modulation.

5. Conclusions

A fully integrated on-chip transmitter for sub-6 GHz 5G NR has been implemented in 65 nm CMOS, comprising baseband Class-AB buffer amplifiers, a TG-switched 50%-duty passive up-conversion mixer, an on-chip quadrature LO generator (PPF with buffers), and a single-stage cascode PA.

Post-layout simulations at 5 GHz show a maximum output power of 21 dBm; at 9 dB back-off, a 100 MHz two-tone test yields an IMD3 of −36.1 dBc. Eliminating the driver stage removes the inter-stage matching network—including on-chip inductors/transformers—thereby reducing on-chip area and simplifying the RF path relative to multi-stage designs.

To ensure practical robustness against PVT variations, the design incorporates a programmable bias control and employs deep N-well isolation with guard rings. The feasibility of the interface is further validated through rigorous simulations incorporating EM-modeled package components such as bond wire inductances. Acknowledging that actual silicon implementation may inevitably introduce performance degradations—such as reduced gain and output power due to unmodeled interface losses, or linearity fluctuations caused by process variations—we prioritized a robust design strategy to mitigate these risks. By incorporating programmable control elements and conducting comprehensive post-layout verifications to anticipate these deviations, this work demonstrates the practical feasibility of the proposed driverless architecture.