Search Results (20)

To enhance the spectral efficiency of hybrid beamforming in millimeter-wave massive MIMO systems, the problem is formulated as a high-dimensional non-convex optimization under constant modulus constraints. A novel algorithm based on fourth-order tensor Tucker decomposition is proposed. Specifically, the frequency-domain channel matrices are structured into a fourth-order tensor to explicitly capture the couplings across the spatial, frequency, and user domains. To tackle the non-convexity induced by constant modulus constraints, the analog precoder and combiner are derived by solving a truncated-rank Tucker decomposition problem through the Alternating Direction Method of Multipliers and Alternating Least Squares schemes. Subsequently, in the digital domain, the Regularized Block Diagonalization algorithm is integrated with the subcarrier and user factor matrices—obtained from the tensor decomposition—along with the water-filling strategy to design the digital precoder and combiner, thereby achieving a balance between multi-user interference suppression and noise enhancement. The proposed tensor-based algorithm is demonstrated through simulations to outperform existing state-of-the-art schemes. This work provides an efficient and mathematically sound solution for hybrid beamforming in dense multi-user scenarios envisioned for sixth-generation mobile communications. Full article

Edge-computing applications demand ultra-low-power architectures for both feature extraction and classification tasks. In this manuscript, a Keyword Spotting (KWS) system tailored for energy-constrained portable environments is proposed. A 16-channel analog filter bank is employed for audio feature extraction, followed by a digital Gated Recurrent Unit (GRU) classifier. The filter bank is behaviorally modeled, making use of second-order band-pass transfer functions, simulating the analog front-end (AFE) processing. To enable efficient deployment, the GRU classifier is trained using a Learned Step Size (LSQ) and Look-Up Table (LUT)-aware quantization method. The resulting quantized model, with 4-bit weights and 8-bit activation functions (W4A8), achieves 91.35% accuracy across 12 classes, including 10 keywords from the Google Speech Command Dataset v2 (GSCDv2), with less than 1% degradation compared to its full-precision counterpart. The model is estimated to require only 34.8 kB of memory and 62,400 multiply–accumulate (MAC) operations per inference in real-time settings. Furthermore, the robustness of the AFE against noise and analog impairments is evaluated by injecting Gaussian noise and perturbing the filter parameters (center frequency and quality factor) in the test data, respectively. The obtained results confirm a strong classification performance even under degraded circuit-level conditions, supporting the suitability of the proposed system for ultra-low-power, noise-resilient edge applications. Full article

The main contribution of this paper is to show the analysis and design of a resonant converter which was designed to operate in the transient stage and with underdamped response, where the resonant network stage has a frequency equal to “n” times the frequency of the switching stage (f_sw) “f_o = nf_sw”. The main advantage of this design methodology is to be able to operate the converter with frequencies higher than 1 MHz in the resonant network stage, without obtaining high levels of losses in the inverse stage. To validate this design methodology, a full bridge resonant converter acting as a frequency multiplier was implemented for a low power wireless power transmission application. For the experimental tests, a base frequency of 300 kHz was decided in the inverting stage, with a frequency multiplication of n = 3, 5, 7 in the resonant network stage (900 kHz, 1.5 MHz, 2.1 MHz) for an output power of 12 watts. Experimental tests proved the operation of the converter acting as a multiplier, where it was possible to reduce losses in the inverter stage, achieving efficiencies of up to 93% in the switching stage with frequencies higher than 1 MHz. Full article

Among many other applications, electronic converters can be used with sensors with analogue outputs (DC voltage). This article presents an analogue computation converter with two DC voltages at the inputs (one input changes the frequency of the output signal, another input changes the amplitude of the output signal) that provide a periodic sinusoidal signal (with variable frequency and amplitude) at the output. On the basis of the analogue computation converter is a nonhomogeneous second-order linear ordinary differential equation which is solved analogically. The analogue computation converter consists of analogue multipliers and operational amplifiers, composed of seven function circuits: two analogue multiplication circuits, two analogue addition circuits, one non-inverting amplifier, and two integration circuits (with RC time constants). At the output of an oscillator is a sinusoidal signal which depends on the DC voltages applied on two inputs (0 ÷ 10 V): at one input, a DC voltage is applied to linearly change the sinusoidal frequency output (up to tens of kHz, according to two time constants), and at the other input, a DC voltage is applied to linearly change the amplitude of the oscillator output signal (up to 10 V). It can be used with sensors which have a DC output voltage and must be converted to a sine wave signal with variable frequency and amplitude with the aim of transmitting information over longer distances through wires. This article presents the detailed theory of the functioning, simulations, and experiments of the analogue computation converter. Full article

True time delay digital beamforming enables large squint-free bandwidths and high beamcounts, ideal for Low Earth Orbit (LEO) satellite communication links. This work proposes a true time delay architecture using Variable Fractional Delay (VFD). True time delay eliminates many analog beamforming performance constraints including inaccurate beam steering and limited beamcounts, while managing system quantization error. This article presents a method of implementing true time delay using a VFD digital filter with sufficient time resolution to minimize quantization error and enable both gigahertz bandwidths and sampling frequencies. Simulations of antenna patterns utilizing the proposed VFD digital filters demonstrate satisfactory LEO beamforming performance with only a 29-tap filter. The VFD filter was implemented using a Xilinx Virtex Ultrascale FPGA and demonstrated a 1077% reduction in dynamic power and a minimum 498% reduction in logic resources, with only a modest increase in multipliers required when compared to Farrow-based architectures previously proposed in the literature. Full article

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages. Full article

The recent COVID-19 crisis has highlighted the importance of RNA-based viruses. The most prominent members of this group are SARS-CoV-2 (coronavirus), HIV (human immunodeficiency virus), EBOV (Ebola virus), DENV (dengue virus), HCV (hepatitis C virus), ZIKV (Zika virus), CHIKV (chikungunya virus), and influenza A virus. With the exception of retroviruses which produce reverse transcriptase, the majority of RNA viruses encode RNA-dependent RNA polymerases which do not include molecular proofreading tools, underlying the high mutation capacity of these viruses as they multiply in the host cells. Together with their ability to manipulate the immune system of the host in different ways, their high mutation frequency poses a challenge to develop effective and durable vaccination and/or treatments. Consequently, the use of antiviral targeting agents, while an important part of the therapeutic strategy against infection, may lead to the selection of drug-resistant variants. The crucial role of the host cell replicative and processing machinery is essential for the replicative cycle of the viruses and has driven attention to the potential use of drugs directed to the host machinery as therapeutic alternatives to treat viral infections. In this review, we discuss small molecules with antiviral effects that target cellular factors in different steps of the infectious cycle of many RNA viruses. We emphasize the repurposing of FDA-approved drugs with broad-spectrum antiviral activity. Finally, we postulate that the ferruginol analog (18-(phthalimide-2-yl) ferruginol) is a potential host-targeted antiviral. Full article

A frequency downscaling technique for enhancing the accuracy of analog lock-in amplifier (LIA) architectures in giant magneto-impedance (GMI) sensor applications is presented in this paper. As a proof of concept, the proposed method is applied to two different LIA topologies using, respectively, analog and switching-based multiplication for phase-sensitive detection. Specifically, the operation frequency of both the input and the reference signals of the phase-sensitive detector (PSD) block of the LIA is reduced through a subsampling process using sample-and-hold (SH) circuits. A frequency downscaling from 200 kHz, which is the optimal operating frequency of the employed GMI sensor, to 1 kHz has been performed. In this way, the proposed technique exploits the inherent advantages of analog signal multiplication at low frequencies, while the principle of operation of the PSD remains unaltered. The circuits were assembled using discrete components, and the frequency downscaling proposal was experimentally validated by comparing the measurement accuracy with the equivalent conventional circuits. The experimental results revealed that the error in the signal magnitude measurements was reduced by a factor of 8 in the case of the analog multipliers and by a factor of 21 when a PSD based on switched multipliers was used. The error in-phase detection using a two-phase LIA was also reduced by more than 25%. Full article

Currently, the design of resonant power converters has only been developed while operating in the steady state, while the design operating in the transient stage has not been considered nor reported. This paper is interested in testing the performance of the resonant circuits operating in the transient stage and finding applications where benefits can be obtained from this form of operation. One application in which it is possible to obtain benefits from designing resonant circuits in the transient state is in the area of frequency multiplication. Usually, to achieve frequency multiplication, it is necessary to resort to complex methods and special devices that increase the complexity of the design and the total cost of the circuit. This paper evaluates the performance of a series RLC resonant circuit operating in the transient stage and with an underdamped response acting as a frequency multiplier, where the oscillation frequency of the current in the resonant tank is “n” number of times the switching frequency of the square voltage source at the input with a duty cycle of D = 50%. To validate the analysis, a circuit was designed to deliver an output power of 30 watts to a resistive load, where the switching frequency of the square voltage source at the input was 500 kHz. Since a multiplier value “n” equal to fifteen was chosen, the current in the resonant tank reached an oscillation frequency of 7.5 MHz. The design methodology was validated by simulations in SPICE, complying with the established design parameters. Full article

In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude. Full article

In this paper, a universal fractional order memelement (FOME) emulator is proposed based on the use of a voltage differentiating current conveyor (VDCC) as active block. The emulation circuit was implemented without an analog voltage multiplier and with only one type of grounded passive element—capacitors. Specially designed switching networks allow controlling the type of memelement and the emulator mode—floating or/and grounded, electronically controlled (by changing the bias voltage of the VDCC) FOMEs. The proposed emulator was theoretically analyzed, and the influence of possible non-idealities and parasitic effects was also been analyzed to reduce the undesirable effects by selecting the passive circuit elements. The proposed designs are very simple compared to most of the designs available in the literature and can operate in a wide frequency range (up to 50 MHz) and also satisfy the non-volatility test. All realized memelements can be used in incremental and decremental modes as well as in inverse configuration. The performance of the circuit was verified by HSPICE simulations using 0.18 μm TSMC process parameters and ±0.9 V power supply. The proposal is also supported by experimental results with off-the-shelf components (LM13700 and one AD844) in order to confirm the proposed solution’s workability. Full article

Extensive research has been conducted on the scaling fractal fractor using various structures. The development of high-resolution emulator circuits to achieve a variable-order scaling fractal fractor with high resolution is a major area of interest. We present a scaling fractal-ladder circuit for achieving high-resolution variable-order fractor based on scaling expansion theory using a high-resolution multiplying digital-to-analog converter (HMDAC). Firstly, the circuit configuration of variable-order scaling fractal-ladder fractor (VSFF) is designed. A theoretical demonstration proves that VSFF exhibits the operational characteristics of variable-order fractional calculus. Secondly, a programmable resistor–capacitor series circuit and universal electronic component emulators are developed based on the HMDAC to adjust the resistance and capacitance in the circuit configuration. Lastly, the model, component parameters, approximation performance, and variable-order characteristics are analyzed, and the circuit is physically implemented. The experimental results demonstrate that the circuit exhibits variable-order characteristics, with an operational order ranging from $-0.7$ to $-0.3$ and an operational frequency ranging from $7.72\mathrm{Hz}$ to $4.82\mathrm{kHz}$. The peak value of the input signal is $10\mathrm{V}$. This study also proposes a novel method for variable-order fractional calculus based on circuit theory. This study was the first attempt to implement feasible high-resolution continuous variable-order fractional calculus hardware based on VSFF. Full article

Predictive maintenance is becoming increasingly important in industry and requires continuous monitoring to prevent failures and anticipate maintenance processes, resulting in reduced downtime. Vibration is often used for failure detection and equipment conditioning as it is well correlated to the machine’s operation and its variation is an indicator of process changes. In this context, we propose a novel energy-autonomous wireless sensor system that is able to measure without the use of batteries and automatically deliver alerts once the machine has an anomaly by the variation in acceleration. For this, we designed a wideband electromagnetic energy harvester and realized passive energy management to supply a wireless sensor node, which does not need an external energy supply. The advantage of the solution is that the designed circuit is able to detect the failure without the use of additional sensors, but by the Analog Digital Converter (ADC) of the Wireless Sensor Nodes (WSN) themselves, which makes it more compact and have lower energy consumption. The electromagnetic converter can harvest the relevant energy levels from weak vibration, with an acceleration of 0.1 g for a frequency bandwidth of 7 Hz. Further, the energy-management circuit enabled fast recharging of the super capacitor on a maximum of 31 s. The designed energy-management circuit consists of a six-stage voltage multiplier circuit connected to a wide-band DC-DC converter, as well as an under-voltage lock-out (UVLO) circuit to connect to the storage device to the WSN. In the failure condition with a frequency of 13 Hz and an acceleration of 0.3 g, the super capacitor recharging time was estimated to be 24 s. The proposed solution was validated by implementing real failure detection scenarios with random acceleration levels and, alternatively, modus. The results show that the WSN can directly measure the harvester’s response and decide about the occurrence of failure based on its characteristic threshold voltage without the use of an additional sensor. Full article

In this article, we present a system to measure current in the range of 0 to 10 $\mathsf{\mu }$A with high-voltage isolation up to 5 kV. This current monitor consists of three ammeters connected in series, to improve the resolution in the measurement. The design features several innovative elements such as using low voltage to provide power to the devices to measure the current and digitize it with a sampling frequency of 1 KHz, it is generated based on a DC-DC converter that produces three voltages, +12 V, −12 V, and 5 V, from a conventional 10 V source. The three voltages are referenced to the same floating ground. The DC-DC converter has a high voltage insulation up to 5 kV and four optocouplers with an insulation up to 20 kV are used to read the digitized data. The introduction of a DC-DC converter contributed to reduce the noise level in the analog part of the circuit which has been resolved implementing shields inside the board. In particle physics, several systems are used to detect particles in high-energy physics experiments such as Gas Electron Multiplier (GEM), micromegas, etc. GEMs suffer small deteriorations due to discharges in constant operation and require monitoring the current consumption at high frequency (1 kHz). In this work, we present the design and operation of a 0 to 10 $\mathsf{\mu }$A auto scale ammeter. The results obtained by monitoring the current in a 10 × 10 cm${}^2$ GEM are shown. Full article

Perceptron is an essential element in neural network (NN)-based machine learning, however, the effectiveness of various implementations by circuits is rarely demonstrated from chip testing. This paper presents the measured silicon results for the analog perceptron circuits fabricated in a 0.6 $\mathsf{\mu }$m/±2.5 V complementary metal oxide semiconductor (CMOS) process, which are comprised of digital-to-analog converter (DAC)-based multipliers and phase shifters. The results from the measurement convinces us that our implementation attains the correct function and good performance. Furthermore, we propose the multi-layer perceptron (MLP) by utilizing analog perceptron where the structure and neurons as well as weights can be flexibly configured. The example given is to design a 2-3-4 MLP circuit with rectified linear unit (ReLU) activation, which consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Its experimental case shows that the simulated performance achieves a power dissipation of 200 mW, a range of working frequency from 0 to 1 MHz, and an error ratio within 12.7%. Finally, to demonstrate the feasibility and effectiveness of our analog perceptron for configuring a MLP, seven more analog-based MLPs designed with the same approach are used to analyze the simulation results with respect to various specifications, in which two cases are used to compare to their digital counterparts with the same structures. Full article