Circuit Implementation of Variable-Order Scaling Fractal-Ladder Fractor with High Resolution

: Extensive research has been conducted on the scaling fractal fractor using various structures. The development of high-resolution emulator circuits to achieve a variable-order scaling fractal fractor with high resolution is a major area of interest. We present a scaling fractal-ladder circuit for achieving high-resolution variable-order fractor based on scaling expansion theory using a high-resolution multiplying digital-to-analog converter (HMDAC). Firstly, the circuit conﬁguration of variable-order scaling fractal-ladder fractor (VSFF) is designed. A theoretical demonstration proves that VSFF exhibits the operational characteristics of variable-order fractional calculus. Secondly, a programmable resistor–capacitor series circuit and universal electronic component emulators are developed based on the HMDAC to adjust the resistance and capacitance in the circuit conﬁguration. Lastly, the model, component parameters, approximation performance, and variable-order characteristics are analyzed, and the circuit is physically implemented. The experimental results demonstrate that the circuit exhibits variable-order characteristics, with an operational order ranging from − 0.7 to − 0.3 and an operational frequency ranging from 7.72 Hz to 4.82 kHz. The peak value of the input signal is 10 V. This study also proposes a novel method for variable-order fractional calculus based on circuit theory. This study was the ﬁrst attempt to implement feasible high-resolution continuous variable-order fractional calculus hardware based on VSFF.


Introduction
Fractional calculus, a branch of mathematics, has been widely implemented in the various fields of science and engineering [1][2][3]. Although it typically has a constant order, its application in describing new phenomena and problems with an operational order dependent on variables such as time and space is difficult. These problems can be better described using variable-order fractional calculus [4][5][6], which was first proposed by Samko and Ross [7] in 1993. Variable-order fractional calculus is expressed through mathematical functions that can be used to model natural phenomena and processes. The studies conducted on variable-order fractional calculus were primarily focused on the mathematical description of variable-order phenomena and processes and on the theory of variableorder fractional calculus application system design [4][5][6][8][9][10][11][12]. However, studies on the implementation of flexible and controllable physical entities of variable-order fractional calculus are scarce.
The solid-state fractor can be used as the physical entity of variable-order fractional calculus operation. However, it faces certain limitations, such as a narrow range of operational order variation, limited temperature control, and difficulty in operational order adjustment [13,14]. Analog circuit implementation is an important approach that enables the flexible and controllable physical implementation of variable-order fractional calculus operation. Sierociuk et al. conducted several pioneering studies [15][16][17]. They use analog circuits to implement many kinds of variable-order fractional calculus circuits. These studies primarily employed the switching strategy to switch between two or three-order types. Constantorder fractor has been used in variable-order circuits and systems [15][16][17][18]. Variable-order fractional impedance (variable-order fractor) is a basic unit circuit or element that can perform variable-order fractional calculus. Variable-order fractional calculus can be realized by changing the operational order while maintaining the structure of the variable-order fractor circuit. In [19], a fractor circuit was designed based on rational approximation, and the order was changed by adjusting the transconductance operational amplifier control current. The operational order was switched between 0.2, 0.5, and 0.8; however, a physical circuit was not implemented. The studies conducted on variable-order fractor with a low operational order variation, narrow range, and regulation difficulties remain limited, to the best of our knowledge. Additionally, the studies conducted on circuit implementation are scarce.
To date, the studies conducted on fractor primarily focused on constant-order fractor circuits. These studies primarily involved two types of constant-order fractor [20]. The first type is constructed either directly or by modeling the phenomena of electrochemistry or other scientific fields, such as Liu-Kaplan [21], 2h-type fractal-tree [20], fractal-ladder [22,23], and fractal-chuan fractor [22][23][24]. The second type is constructed by designing a circuit-realizable rational function to approximate the performance of fractional-order operators such as the Oustaloup algorithm [25,26], Dutta Roy's fractor [27], and Carlson's iterating rational approximation algorithm [28,29].
In a previous study, we developed scaling expansion theory [30,31]. This theory can be used to extend multiple fractors, thereby overcoming the limitation of only realizing half-to arbitrary-order operations [30,32,33]. Scaling expansion theory can also be used in mathematics to extend the algebraic iterative equation, which describes the rational approximation of half-order operators into an irregular scaling equation describing arbitrary fractional operators. This theory can be used to construct the scaling fractal-lattice [30,31], scaling fractal-chuan [32], scaling fractal-chain [33], and scaling fractal-ladder fractor [34]. The scaling fractal fractor presents a high operating frequency bandwidth.
Scaling expansion theory is used to extend the semi-order fractor to a fixed scaling structure based on the required constant order. The theory is employed to realize the circuit of a fractional memristor of the scaling fractal-lattice [30] and scaling fractal-ladder fractor [34]. The lumped parameter value adjustment with the port flux or charge must be solved to achieve the scaling fractal fractional memristor [34]. It is similar to that the operational order adjustment must be solved to achieve the variable-order fractor.
Several studies have been conducted on scaling fractal fractor by using various structures [30][31][32][33][34]. However, the design of high-resolution emulator circuits to achieve highresolution variable-order scaling fractal fractor is theoretically challenging. A variable-order scaling fractal-ladder fractor (VSFF) circuit implementation method is proposed to overcome this issue. The main contributions of this study are as follows: • The proposed circuit can realize the VSFF, thereby overcoming the limitations faced by the existing variable-order fractor, such as limited operational order variation, narrow range, and difficult adjustment [13,14,19]. • A programmable resistor-capacitor series circuit and programmable universal electronic component emulators are designed based on the high-resolution multiplying digital-to-analog converter (HMDAC). These emulators can also be applied to other variable-order fractor circuits, memristor emulators, and memcapacitor emulators [35][36][37]. • This paper also proposes a method for variable-order fractional calculus based on circuit theory.
The remainder of this paper is organized as follows. Section 2 presents the VSFF circuit configuration. A programmable resistor-capacitor series circuit emulator and a universal electronic component emulator are designed based on the requirements of the circuit configuration. Section 3 presents the model and component parameters in the VSFF and the calculation of the relative error of equivalent parameters of the programmable circuit. The approximation performance and variable-order characteristics of the VSFF are analyzed in the frequency domain. The VSFF is implemented, and the variable-order operation characteristic of the circuit is experimentally validated. Sections 4 and 5 present the discussions and conclusions, respectively.

VSFF Design
This section describes the design of the proposed VSFF. Firstly, the circuit configuration is presented. Subsequently, the emulators required to realize the programmable resistor-capacitor series circuit, universal electronic capacitor, and resistor components are described.

VSFF Circuit Configuration
Scaling fractal-ladder fractor is a classic constant-order fractor circuit [34]. It is employed to achieve the scaling fractal fractional memristor and design the lumped parameter value of the fractor with the port flux or charge [34]. Similarly, the constant-order fractor circuit component parameters must be adjusted based on the required change in the operational order to design a variable-order fractor circuit for solving the problem. Therefore, the design of the VSFF circuit configuration requires only the resistor and capacitor to be replaced in the constant-order scaling fractal-ladder fractor with the variable resistor and capacitor controlled by the microcontroller.
This subsection presents the VSFF circuit configuration and explains the parameters and calculation of the admittance function. Subsequently, the equivalent operation order expression of the VSFF in the characteristic frequency range is calculated to prove that the VSFF possesses characteristics of variable-order fractional calculus operations. Furthermore, it presents a method to optimize the VSFF and improve the approximation performance. Lastly, it explains the correlation between the circuit parameters and operation order. Figure 1 depicts the VSFF circuit configuration. The n-th subcircuit comprises a variable resistor, r n , in series with a variable capacitor, c n . k denotes the total number of subcircuits. The serial number, n = 1, 2, . . . , k. R(C), denotes the reference resistance (capacitance). Resistor r o and capacitor c o are used for circuit optimization. The n-th subcircuit, r o , and c o denote the programmable resistor-capacitor series circuit, programmable resistor, and programmable capacitor emulators, respectively, which are controlled by the microcontroller. α(β) denotes the resistance (capacitance) progression ratio. The parameter [15,31],

Circuit Configuration and Admittance
represents the scaling factor of the circuit, where α, β, and σ denote the scaling parameters. The scaling parameters are positive real numbers and α = 1, β = 1. The case in which all the scaling parameters are greater than 1 corresponds to the direct proportion extension VSFF. However, the case in which all the scaling parameters are between 0 and 1 corresponds to the inverse proportion extension VSFF. The VSFF can realize any real fractional operation in the approximation frequency range. When resistor r o and capacitor c o are not considered, the admittance of the VSFF function can be obtained as follows: s denotes the Laplace or the operational variable, where τ = RC, w = τs, and Y k (w) = Y k (w/τ)R. The admittance function is normalized as follows: The iterative algorithm formula of the normalized admittance function is expressed as follows:Ȳ When k → +∞, the equation, corresponding to the formula of the iterative algorithm, which is the VSFF scaling equation. Equation (5) can be used to analyze the electrical characteristics of the VSFF, including the frequency characteristics and operational order.

Characteristic Frequency and Operational Order
The theoretical expression of the operational order of VSFF in the characteristic frequency range can be calculated. The characteristic frequency of the n-th subcircuit can be expressed as follows: Therefore, when 1 < σ < ∞ is a direct proportion extension, ω n is extended to the lower-frequency range. In an inverse proportion extension, 0 < σ < 1, ω n is extended to the higher-frequency range. When at high frequencies (1 < |ω| → ∞), the circuit exhibits resistive characteristics. At low frequencies (1 > |ω| → 0), the circuit exhibits capacitive characteristics, that is When the frequency band meets the resistive and capacitive components interact, and the circuit exhibits fractional calculus operational performance. The operational order can be expressed as follows [34]: where µ denotes the operational order. A VSFF can be constructed by adjusting the values of α and β, as shown in (10).

VSFF Optimization
The parallel-connected resistor, r o , and capacitor, c o , in the circuit are used to optimize the VSFF to achieve a better variable-order fractional calculus performance. It is assumed that an infinite number of subcircuits exist before the 1-th subcircuit and behind the k-th subcircuit since the total number of subcircuits is limited. When α, β > 1. The resistance and capacitance decrease progressively with decreasing number of n at each subcircuit before the 1-th circuit. The capacitor of each subcircuit plays a significant role. The capacitor connected in parallel before the 1-th subcircuit is expressed as follows: For each subcircuit behind the k-th circuit, both the resistance and capacitance increase with increasing number of n. The resistor of each subcircuit plays a significant role. The resistor connected in parallel behind the k-th subcircuit is expressed as follows: Similarly, when 0 < α, β < 1, the capacitor connected in parallel before the 1-th subcircuit and the resistor connected in parallel behind the k-th subcircuit are β k C

Component Parameter Calculation
The parameter values of each component and its variation rule of the circuit configuration can be calculated based on the operational order, µ, and its variable-order range. µ min and µ max denote the minimum and maximum values of the variable-order range, respectively. The resistance progressive ratio, α = σ −µ , and capacitance progressive ratio, β = σ α = σ µ+1 , are calculated based on the variable-order range, −1 < µ min ≤ µ ≤ µ max < 0, and scaling parameter, σ. The n-th variable resistor, and the n-th variable capacitor, The resistor, and the capacitor, The partial derivative of the n-th variable resistor r n with respect to the operational order µ can be obtained as follows: If n = 1, ∂r n ∂µ = 0. If n = 2, 3, . . . , k, The resistance of r n decreases with an increase in µ apart from the fixed value of r 1 . The partial derivative of c n corresponding to µ can be obtained as follows: If n = 1, ∂c 1 ∂µ = 0. If n = 2, 3, . . . , k, Except for the fixed value of c 1 , the capacitance of c n increases with an increase in µ. Figure 1 depicts the n-th subcircuit, which is composed of a variable resistor, r n , in series with a variable capacitor, c n . If the variable resistor, r n , and variable capacitor, c n , are equivalent when using separate emulators, each emulator must be controlled separately, and the variable capacitor emulator circuit must be operated by floating. The n-th programmable resistor-capacitor series circuit emulator (n = 2, 3, . . . , k) was designed to avoid using more hardware circuits and separately control each emulator. r n and c n can be controlled by a single HMDAC, and a separate floating emulator circuit is not required.

Programmable Resistor-Capacitor Series Circuit Emulator
This subsection presents the circuit schematic of the programmable resistor-capacitor series circuit emulator and explains the parameters involved. The theory proves that the circuit schematic can achieve the aim of the emulator. The expression of the control variable, K (n) , is then theoretically deduced to fulfill the variable-order requirement. Lastly, the expressions of the relative errors ofr n andc n are derived theoretically. 1 represents the HMDAC. The electrical characteristics between ports, a (n) and b (n) , are considered as the equivalent electrical characteristics of the n-th subcircuit, as shown in Figure 1.

Circuit Schematic
y , the operational amplifier, (A x , is equal to the current flowing through the resistor, R (n) x . If the voltage across the capacitor, C (n) x , is 0 V in t = 0, the voltage is obtained as u (n) Most digital-to-analog converters (DACs) operate at a fixed reference voltage, where the output voltage or current corresponds to the product of the reference voltage and the value of a set control variable. The reference voltage of a multiplicative DAC typically varies within the range of ±10 V. U in (t) and the control variables, are controlled by the microcontrollers. K (n) corresponds to the digital quantity, , provided by the microcontroller. m is expressed as the number of bits of the HMDAC. R (n) constitute a differential amplifier circuit. The output voltage of A (n) Therefore, According to (23), the circuit illustrated in Figure 2 is equivalent to the series connection of the programmable resistance,r Furthermore, the programmable capacitance, According to (24) and (25), bothr n andc n correspond to the control variables, K (n) andr n , andc n are controlled by the microcontroller.

Calculating the Control Variable of K (n)
The equivalentr n andc n of Figure 2 can be achieved by adjusting the value of the control variable, K (n) , using the microcontroller based on the VSFF, which decreases the number of DACs and presents considerable advantages. According to r n gradually increases andc n gradually decreases with an increase in K (n) . When K (n) = 0, the minimum programmable resistance,r n is R (n) x . According to (13) and (18), whenr n is the minimum value within the change range, µ must be the maximum value, i.e., When K (n) = 0, the maximum value ofc n is C (n) x . According to (14) and (20), wheñ c n is the maximum value within the change range, the operational order, µ, must be the maximum value, that is Equation (27) is substituted into (24) to obtaiñ Equation (28) is substituted into (25) to obtaiñ Whenr n = r n , can be obtained from (13) and (29). Whenc n = c n , can be obtained from (14) and (30). Remarkably, (31) and (32) produce the same result: Only one control variable, K (n) , is required to satisfy the change in the resistance, r n , and capacitance, c n , of the n-th subcircuit in the VSFF, as shown in (33). When compared to the programmable resistance and capacitance circuits, which require HMDAC control, the number of HMDAC is halved, the circuit is simpler, and the I/O port resources of the microcontroller are reduced. Figure 2 depicts the relative errors ofr n andc n of the circuit, which correspond to µ min , µ max , n, and m. According to (24), the correlation between the relative error, δ (r n ) , of r n and the resolution, ∆K (n) = 1 2 m , of the HMDAC is expressed as:

Calculating the Relative Errors ofr n andc n
According to (25), the correlation between the relative error, δ (c n ) , ofc n and ∆K (n) = 1 2 m is expressed as: According to (33)- (35), when µ = µ max , K (n) = 0,r n , andc n are the minimum relative errors within the change range: When µ = µ min , K (n) is the maximum value within the change range, andr n andc n can be used to obtain the maximum relative error within the change range: The maximum relative error of the programmable resistor-capacitor series circuit emulator corresponds to the ranges of µ, n, and m. The larger the range of µ, the larger the maximum relative error of the equivalent programmable parameter. The larger the serial number, n, the larger the maximum relative error of the equivalent programmable parameter. The larger the number of bits, m, the smaller the resolution, ∆K (n) , and the maximum relative error of the equivalent programmable parameters.

Programmable Universal Electronic Component Emulator-Programmable Resistor and Capacitor for Circuit Optimization
in . For port, a (x o ) , the input current is expressed as where s denotes the complex frequency variable. According to (39), the equivalent component parameter value of the circuit shown in Figure 3 can be adjusted by adjusting x , the equivalent programmable optimized resistance is expressed as wherer o corresponds to the control variable, K (r o ) , and is controlled by the microcontroller.
x , the equivalent programmable optimized capacitance is expressed as:c wherec o corresponds to the control variable, K (c o ) , and is controlled by the microcontroller. If X (x o ) represents circuit parameters other than the resistance and capacitance, such as the inductance, fractance, and transtance [38], the circuit shown in Figure 3 can also be used to realize a programmable circuit with more component parameter values, thereby improving its applicability. The equivalent programmable optimized resistance,r o , or the programmable optimized capacitance,c o , shown in Figure 3 can be realized through a microcontroller by adjusting K (r o ) or K (c o ) . The partial derivative ofr o corresponding to K (r o ) can be obtained gressively. The partial derivative of r o , shown in (15), to µ can be obtained as ∂r o ∂µ > 0. This indicates that r o increases with an increase in µ. When K (r o ) = 0 is used, the maximumr o obtained is r o when µ = µ max . That is, Assumingr o = r o can be obtained from (15), (40) and (42), The partial derivative ofc o corresponding to K (c o ) is obtained as follows: . The partial derivative of c o of (16) corresponding to µ can be obtained as where c o decreases with an increase in µ.

Calculating the Relative Errors ofr o andc o
When realizing the VSFF, the relative error of the equivalent element parameter values in Figure 3 corresponds to µ min , µ max , n, and m. The correlation between the relative error, δ r o , ofr o and ∆K (r o ) = 1 2 m is expressed as follows: According to (43), K (r o ) = 0 can be obtained when µ = µ max and the minimum relative error ofr o within the change range is expressed as follows: when µ = µ min , K (r o ) is the maximum value within the change range, and the maximum relative error can be obtained from (43) and (48) as follows: The correlation between the relative error ofc o and ∆K (c o ) = 1 2 m can be given as According to (47), when the operation, µ = µ min , the control variable K (c o ) = 0, andc o is the minimum relative error within the change range, When µ = µ max , K (c o ) is the maximum value within the change range and the maximum relative error ofc o is obtained. That is,

Experimental Results
This section presents the results of the experiments and the verification of the VSFF circuit. Firstly, the model and component parameters in the VSFF are provided, and the relative error of the programmable circuit is calculated. Subsequently, the approximation performance and variable-order characteristics of the VSFF are analyzed in the frequency domain. Furthermore, two equivalent methods to calculate the variable-order electrical characteristics are presented. One of these characteristics is derived from circuit theory and is presented herein. Lastly, the VSFF is implemented and the variable-order characteristic of the circuit is experimentally validated.

Circuit Implementation
This subsection presents the parameters, models, and instruments used for circuit implementation. Firstly, the values of the component parameters are presented and the model selection of the microcontroller and the HMDAC are introduced. Subsequently, a list of circuit parameters is presented, which includes the control variables of the microcontroller, equivalent parameters of the emulators, and equivalent parameter relative errors of the emulators. The influence of the different parameters is also demonstrated. Lastly, some details that were considered in the implementation of the circuit are presented.
This circuit realizes the VSFF by replacing the n-th subcircuit shown in Figure 1 with the emulator shown in Figure 2 (n = 2, 3, · · · k), and by replacing the resistance, x ) of the emulator shown in Figure 3. It was assumed that k = 5, n = 2, 3, 4, 5, R = 330 Ω, C = 0.1 µF, σ = 5, and Each AD5544 comprised four current output DACs, with each DAC containing an independent multiplying reference input. A load strobe enabled 4-channel, simultaneous updates for hardware-synchronized output voltage changes. Two AD5544 units were used for the implementation of the circuit.
STC8A8K64S4A12 was selected as the microcontroller, as shown in Figure 1. This microcontroller did not require an external crystal oscillator and external reset circuit for an internal clock source frequency of up to 24 MHz. According to (33), (43), (47), and the variable order µ, the control variables, K (n) , K (r o ) , and K (c o ) of AD5544 were set by the STC8A8K64S4A12 to realize the change in the operational order of the VSFF. Table 1 lists the parameters of the circuit. R (n) x , C (n) x ,r n ,c n , K (n) , δ (x n ) min (x n =c n ,r n ), and δ (r n ) max (x n =c n ,r n ) were calculated from (27)-(29), (30), (33), (36) and (37), respectively.
Following the circuit implementation, R (n) x and C (n) x took fixed values. K (n) was controlled by the microcontroller, and by varying this value, the microcontroller adjustedr n andc n , thereby achieving variable order. δ   Table 1 were assumed to be 16 k Ω.   were not nominal values, they were obtained in parallel by using the nominal capacitance. Figures 2 and 3 illustrate the resistors and capacitors of the circuit, which were packaged with 0805. The rated power of the resistance was 0.125 W and the rated voltage of the capacitor was 50 V. During production, it was assumed that the power rating of the resistor did not exceed the rated power value, the capacitor voltage was less than the voltage withstand value, and that the power supply voltage, input and output voltages, and input and output currents of all the chips in the circuit were within the standard range.

Frequency Characteristic Analysis
This subsection presents the frequency domain analysis of the approximation performance and variable-order characteristics of the VSFF. The amplitude-frequency characteristic, phase-frequency characteristic, order-frequency characteristic, and F-frequency characteristic function are introduced, and the theoretical and experimental frequency domain characteristic analysis curve of the VSFF is obtained. Subsequently, the frequency domain characteristic curve is analyzed, and the range of the approximation frequency is obtained when the VSFF changes to a different operation order. Lastly, the correlation between the lumped parameter value and the operation order was solved.
The approximation performance and variable-order characteristics of the VSFF were analyzed by using the frequency characteristics. The impedance function of the VSFF was Z k (s) when the operational order changed to µ and the impedanceĨ (µ) (s) = F (µ) s µ was then approximated. The complex frequency variable, s, was replaced by the exponential frequency variable, [31]. That is: (54) The amplitude-frequency characteristic functions are: The phase-frequency characteristic function is: The order-frequency characteristic function [20] is: The F-frequency characteristic function [40] is: These functions were used for comparative analysis. Λ k ( ), θ k ( ), O k ( ), and Γ k ( ) represent the frequency characteristic functions ofZ k (s). Λ (µ) ( ), θ (µ) ( ), O (µ) ( ), and Γ (µ) represent the frequency characteristic functions ofĨ (µ) (s). For the circuit configuration shown in Figure 1 and in the case of the parameter values shown in Table 1, when µ = −0.7, −0.6, . . . , −0.3, respectively. r n (n = 2, 3, 4, 5), c n , r o , and c o were calculated from (13), (14)-(16), respectively. These parameters are substituted into (2). Based on (55)-(58), the theoretical characteristic function curve in the frequency domain was determined, as shown in Figure 4. Figure 4 also shows the simulation experiment results obtained by Multisim 14.  The amplitude-frequency and phase-frequency characteristic function curves, shown in Figure 4a,b, describe the gain and phase characteristics between the voltage and current of the VSFF in the frequency domain, respectively. It can be observed from the amplitudefrequency function curve that the amplitude-frequency characteristic values decreased with increasing frequency. The smaller the operational order, the higher the rate of reduction in the amplitude-frequency characteristic values with increasing frequency. In the low-frequency range, the amplitude-frequency characteristic values decreased with increasing operational order. The phase-frequency and order-frequency characteristic curves, shown in Figure 4b,c, respectively, constitute the mathematical basis to analyze the operational performance (such as the operational order, constant phase, and approximation performance) of the VSFF.
In the case of a fixed operational order, the phase was a fixed value in the approximation frequency range (10 1 ∼10 5 ). When the frequency was less than 10 1 , the phase increased with decreasing frequency. When the frequency was greater than 10 5 , the phase decreased with increasing frequency. In the case of a fixed frequency, the phase decreased with decreasing operational order. The order-frequency characteristic function represents the operational order of the VSFF from the frequency domain. It can be observed from the order-frequency function curve that the operational order was a fairly constant value in the approximation frequency range (10 1 ∼10 5 ). When the frequency was less than 10 1 , the operational order increased with decreasing frequency. When the frequency was greater than 10 5 , the operational order decreased with increasing frequency. In the case of a fixed frequency, the operational order decreased with decreasing operational order. The F-frequency characteristic function curve, shown in Figure 4d, represents the lumped parameter value of the VSFF in the frequency domain.
It can be observed from F-frequency function curve that the lumped parameter value was a fairly constant value in the approximation frequency range (10 1 ∼10 5 ). When the frequency was less than 10 1 , the lumped parameter value decreased with the decrease in the frequency. When the frequency was greater than 10 5 , the lumped parameter value increased with the increase in frequency. In the case of a fixed frequency, the lumped parameter value increased with the decrease in the operational order. The order-frequency and F-frequency characteristic functions visually represent the degree of operational order and the lumped parameter value of the VSFF approximation of the ideal fractor element. It can be observed from the order-frequency and F-frequency characteristic curves, that the VSFF realized the fractional and variable operation orders within a certain frequency range. The highest frequency index value [31], and the lowest frequency index value [31], were used to realize fractional-order operation. Therefore, the operating frequency range of the VSFF of the parameters shown in Table 1 was obtained as (10 1 ∼10 5 ), i.e., (7.72 Hz∼4.82 kHz). The lumped parameter value, F (µ) , was solved within the operating frequency range, as observed from the Ffrequency characteristic curve. The correlation between the lumped parameter value, F (µ) , and µ was solved by using the least square method to fit the data and to obtain the following equation: The relative error of Γ (µ) (µ) calculated by (61) within the variation range of µ, was less than 0.05%.

Two Equivalent Methods for Calculating Variable-Order Electrical Characteristics
This subsection presents two equivalent methods to calculate the variable-order electrical characteristics to obtain the time-domain theoretical electrical characteristics of the VSFF. One of these methods is derived from circuit theory and is presented in this study. The other variable-order electrical characteristic calculation method is obtained through the Grünwald-Letnikov variable-order fractional calculus.

Variable-Order Electrical Characteristics Obtained through Circuit Theory
For the input voltage signal, u(t), to the VSFF, the current flowing through the VSFF according to Kirchhoff's current and voltage laws can be represented as follows: where u n (t) denotes the voltage across the capacitor, c n (n = 1, 2, . . . , k), and is described by The correlation between α and β in Equations (62) and (63) and the operation order can be obtained from Equation (10). Therefore, the variable-order electrical characteristics of the VSFF can be obtained based on (10), (62) and (63).

Variable-Order Electrical Characteristics Obtained through the Grünwald-Letnikov Definition
The input voltage signal, u(t), to the VSFF and the main spectral range of u(t) was within the approximate frequency range of the VSFF. The input current obtained is expressed as follows [13]: where t 0 is the initial time.
Grünwald-Letnikov variable-order fractional calculus was used to define the computation completion (64). It has at least three widely used definitions [15][16][17]. These definitions are based on replacing the constant operational order, µ, with variable operational order, µ(t). The coefficients are then obtained based on different sampling methods. If the coefficient is sampled from the order value at the corresponding time of the coefficient, then [15][16][17]: where t < t 0 , u in (t) ≡ 0, and −µ(t − jh) j are binomial coefficients. To complete the numerical calculation of (65), the step size, h, must be sufficiently small; therefore: where ψ (−µ(t−jh)) j = (−1) j −µ(t − jh) j represents the polynomial coefficient of the function, (1 − z) −µ(t−jh) , which can be directly calculated by using the following recursive formula: If µ(t) is constant, the calculated result of (66) must be consistent with that defined by the Grünwald-Letnikov fractional calculus of the constant operational order.

Experimental Verification
In this subsection, the variable-order characteristics of VSFF are experimentally verified. The experimental fields include steady-state, dynamic, and continuous variable order. The steady-state variable-order experiments can be used to prove that a single VSFF can be used as a constant-order fractor of different orders. The dynamic variable-order experiments can prove that the VSFF contains a variable-order process, which can be used in the cases where the operational order requires a jump. For example, in the design of programmable variable-order fractional chaos [18]. The continuous variable-order experiments can be used to demonstrate the capability of VSFF for programmable high-resolution continuous variable-order.
GPS-4303C, TBS1052B, EE16330, TCP312A, and TCPA300, were employed as the power supply, oscilloscope, signal generator, current probe, and current amplifier, respectively. The current probe and amplifier were used to convert the current waveform to a linear voltage signal and to amplify the voltage signal for the oscilloscope test, respectively. The TBS1052B is connected to a PC through a USB interface, which has the Tektronix OpenChoice PC Communications software installed on it to obtain the data that it measured by TBS1052B. Figure 5 depicts the experimental test images.

Steady-State Variable-Order Experiment
If the signal generator outputs a sinusoidal voltage signal, to the VSFF, A (S) = 10 V, and f (S) = 1000 Hz. Then, µ(t) is −0.30, −0.46, and −0.63, respectively. The Grünwald-Letnikov definition method is used to calculate the current waveform obtained from (61), (66) and (67), and Figure 6a,c,e presents the corresponding experimental current waveform. If the triangular wave voltage signal, u (T) (t), is input into the VSFF, the peak voltage, A (T) = 6 V, frequency, f (T) = 50 Hz, and µ(t) change to −0.32, −0.48, and −0.65, respectively. The Grünwald-Letnikov definition method is used to calculate the current waveform, and Figure 6b,d,f depicts the corresponding experimental current waveform. Furthermore, Figure 6 depicts the current error waveform between the experimental current waveform and the Grünwald-Letnikov definition method is used to calculate the current waveform.
According to the experimental current waveform shown in Figure 6, when the input voltage signals are sinusoidal and triangular, the VSFF can perform steady-state variableorder experiments of different orders. The average values of the current error waveforms shown in Figure 6a Figure 6a,c,e also demonstrates that when µ(t) is −0.30, −0.46, and −0.63, the corresponding experimental phase difference is −26.6 • , −40.5 • and −53.1 • , respectively. The phase error between the experimental and the theoretical phase is shown in Figure 6a,c,e are 0.4 • , 0.9 • , and 3.6 • , respectively. The phase difference decreases with a decrease in the operational order, µ(t), which is consistent with the phase-frequency characteristic curve presented in Figure 4b. The experimental results concur well with their theoretical counterparts when the input waveform, amplitude, frequency, and operational order change. The peak value of the input signal was 10 V.

Dynamic Variable-Order Experiment
If the voltage signal, u (S) (t), shown in (68) is input to the VSFF and the peak voltage, A (S) = 6 V, ,ñ = 0, 1, 2, . . . Figure 7a presents the circuit theoretical method used to calculate the current waveform obtained from (10), (62) and (63) and the Grünwald-Letnikov definition method used to calculate the current waveform obtained from (61), (66) and (67). Figure 7a presents the corresponding experimental current waveforms. When the triangle wave voltage signal, u (T) (t), is input into the VSFF, the peak voltage, A (T) = 6 V, frequency, f (T) = 50 Hz, and µ(t) vary between −0.33 and −0.66. Figure 7b illustrates the circuit theoretical method used to calculate the current waveform obtained from (10), (62) and (63) and the Grünwald-Letnikov definition method used to calculate the current waveform obtained from (61), (66) and (67). Figure 7b illustrates the corresponding experimental current waveform. Additionally, Figure 7a,b presents the current error waveform between the experimental current waveform and the circuit theoretical method calculated current waveform.
According to the experimental current waveform shown in Figure 7, when the input voltage signals are sinusoidal and triangular, the VSFF can complete dynamic variable-order experiments of different orders. The circuit theoretical method and the Grünwald-Letnikov definition method used to calculate the current waveform overlap perfectly. The accuracy of the variable-order electrical characteristics obtained through circuit theory is verified.
The average values of the current error waveforms shown in Figure 7a,b are 0.0517 mA and 0.0723 mA, respectively. The standard deviations of the current error waveforms shown in Figure 7a,b are 0.9938 mA and 0.7473 mA, respectively. At the moment when the operation order jumps, the circuit theoretical method calculated current waveform and the Grünwald-Letnikov definition method calculated current waveform also jump. However, the corresponding experimental waveform jump is not obvious. This is due to parasitic resistance and capacitance parameters in VSFF, test cables, and experimental apparatus, which filter out the high-frequency spectrum during the current waveform jump. According to the experimental current waveform shown in Figure 7, the VSFF completed the change of order within the approximation frequency and operational order ranges.

Continuous Variable-Order Experiment
A continuous variable-order experiment was conducted to fully demonstrate the variable-order capability of the VSFF and to reflect its advantages. If the voltage signal, u (S) (t), shown in (68) is input to the VSFF and the peak voltage, A (S) = 6 V, the frequency, f (S) = 50 Hz, and µ(t) change from −0.3 to −0.7. The variable-order range included the maximum and minimum values of the designed operational order. Figure 8 depicts the circuit theoretical method used to calculate current waveform obtained from (10), (62) and (63) and the Grünwald-Letnikov definition method used to calculate the current waveform obtained from (61), (66) and (67). Figure 8 depicts the corresponding experimental current waveform. Additionally, Figure 8 depicts the current error waveform between the experimental current waveform and the circuit theoretical method used to calculate the current waveform. The VSFF can perform continuous variable-order experiments based on the experimental current waveform depicted in Figure 8. The circuit theoretical method and the Grünwald-Letnikov definition method used to calculate the current waveform overlap perfectly. The accuracy of the variable-order electrical characteristics obtained through circuit theory is confirmed once again. The larger current error waveforms are partly due to small phase errors. In essence, the current error is not large. The average value and standard deviations of the current error waveforms shown in Figure 8 are 0.1167 mA and 0.7094 mA, respectively. Errors may be caused by many factors such as circuit components, experimental instruments, and frequency domain approximation errors. Errors in circuit components include resistors, capacitors, operational amplifiers, and AD5544. The relative errors of various equivalent parameters of AD5544 caused by resolution have been given in Table 1. Integral non-linearity is also an important factor causing error of AD5544. There is a non-linear relationship between integral non-linearity and digital quantity of AD5544 [39]. The frequency characteristic curves shown in Figure 4 also indicate that there are frequency domain errors that fluctuate with frequency within the approximate frequency range. When the input amplitude of the voltage waveform is constant, µ(t) changes from −0.3 to −0.7, the smaller the amplitude of the current waveform. This is consistent with the amplitude-frequency characteristic function curve shown in Figure 4a. It can also be observed from Figure 8 that when the operation order reduces, the smaller the operation order, the larger the relative error between the experimental current waveform and the theoretical waveform. This is similar to the equivalent relative error variation rule shown in Table 1. It is observed that the equivalent relative error changes from minimum to maximum as the operation order changes from maximum to minimum. It can be observed from Figure 8 that the variable-order scaling fractal-ladder fractor can perform high-resolution continuous variable-order experiments within the range of the operation order. This is because the HRMDAC and other devices can support the requirement of device indicators for continuous operational order varying.
It can also be observed from Figure 8 that when the operation order is large, the amplitude of the experimental current waveform is smaller than that of the theoretical current waveform. When the operation order is small, the amplitude of the experimental current waveform is larger than that of theoretical current waveform. A similar situation is observed in the steady-state variable-order and dynamic variable-order experiments. The error between the experimental waveform and the theoretical waveform, and the operation order exhibit a stable regularity; this type of error is called a systematic error. System errors must be calibrated often in circuit and system design. Therefore, when the results of Figures 6 and 7 are presented, the same systematic error calibration parameters are implemented for the circuit theoretical method, which is used to obtain the current waveform from (10), (62) and (63) and the Grünwald-Letnikov definition method used to obtain the current waveform from (61), (66) and (67). The calibration results used while constructing an application system using VSFF must be more accurate.

Discussion
This study implemented the VSFF superior to existing related studies in multiple indicator dimensions. In [13], when the temperature of the solid-state fractor changed within the range of 25∼60 • C, and the operational order changed within a range of only 0.909∼0.949. In [14], when the temperature of the solid-state fractor changed within the range 100∼150 • C, the operational order changed within a range of only 0.77∼0.86. The VSFF implemented in this study used a microcontroller, which is more convenient and efficient than the temperature control method [13,14]. In [19], the operational order switched between 0.2, 0.5, and 0.8. However, the studies conducted on circuit implementation are limited. The variable-order range of the circuit realized in this study was from −0.7 to −0.3. This significantly exceeds the operational order range of the variable-order fractor [13,14,19] and exhibits high-resolution characteristics. The HMDAC is crucial in the implementation of the VSFF.
In this study, the scaling fractal fractor used in the VSFF exhibited a classic structure. The voltage-controlled resistance and capacitance circuits used the AD633 multiplier as the core in the memristor and memcapacitor emulators [35][36][37]. The resolution and precision requirements of the VSFF for variable circuit parameter adjustment could not be easily satisfied since the accuracy of the AD633 was approximately 2%. The HMDACs are typically used in the DAC conversion and in multiplier circuits. The HMDAC uses the AD5544, m = 16 bits, and a resolution of ∆K = 1 2 m = 1 65,536 . For the emulator, the equivalent minimum relative error δ (x n ) min = 1 65,536 (x n =c n ,r n , c o , r o ) and maximum relative error δ (x n ) max = 6.732 × 10 −4 . The programmable resistor-capacitor series circuit and programmable universal electronic component emulators designed using the HMDAC as the core can better meet the requirements of the VSFF parameter adjustment.
In this study, the selection of component parameters is merely an example of the circuit implementation of the VSFF. The technical specifications of VSFF can be adjusted based on the requirement of the actual system. The frequency range of the operations can be increased by increasing the total number of subcircuits. The accuracy can be improved by decreasing the value of the scaling parameter, σ. The VSFF accuracy can also be improved by selecting components with higher precision and resolution. Furthermore, the speed of the variable order can be increased by using faster microcontrollers.
Despite the various advantages presented by the implemented VSFF, it faces certain limitations that must be addressed. Firstly, VSFF is larger and thus requires more space, although it is more flexible and has a wider range of steps when compared to the existing solid-state fractor. Secondly, the VSFF variable-order speed is limited by the control speed of the microcontroller. Lastly, it can be observed from the F-frequency characteristic function curve presented in Figure 4d, that when the operational order of VSFF changes, the lumped parameter value also changes.

Conclusions
Variable-order fractor is an important unit or component for realizing variable-order fractional calculus operations. Based on previous studies on scaling fractal fractor with various structures [30][31][32][33][34], the theoretical problem of developing high-resolution emulator circuits to achieve VSFF is a major challenge. This study proposed a VSFF circuit configuration based on the scaling expansion theory [30,31]. A programmable resistor-capacitor series circuit and programmable universal electronic component emulators with HMDAC were designed based on the requirements of the circuit configuration. The experimental content includes steady-state, dynamic and continuous variable-order. The operational order ranged from −0.7 to −0.3. The operation frequency of the VSFF ranged from 7.72 Hz to 4.82 kHz and the peak value of the input signal was 10 V.
The programmable resistor-capacitor series circuit and the programmable universal electronic component emulators were designed based on the HMDAC. Furthermore, these emulators can be applied to other variable-order fractor circuits, memristor emulators, and memcapacitor emulators. The proposed implementation method can also be used to design the existing scaling fractal-chain [33], fractal-chuan [32], and fractal-lattice [30,31] circuits with variable-order fractor. The VSFF can be used to model natural phenomena and processes of the variable order. The proposed variable-order fractional calculus method that is based on circuit theory can be used as a new time-domain approximation method. More circuit theoretical calculation formulas of variable-order fractional calculus operation can be obtained based on the proposed circuit theoretical calculation method of variable-order fractional calculus operation. The variable-order fractional calculus using circuit theory requires further analysis since it is a novel calculation method.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations are used in this manuscript: