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Electronics
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Design of CMOS Integrated, Circuits and Systems for Wireless Communications
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Design of CMOS Integrated, Circuits and Systems for Wireless Communications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (20 December 2023) | Viewed by 9546

Special Issue Editor

Prof. Dr. Young-Kyun Cho

E-Mail Website
Guest Editor
Department of Radio & Information Communications Engineering (RICE), Chungnam National University, 99 Daehak-ro, Yuseong-gu, Daejeon 34134, Republic of Korea
Interests: delta-sigma modulation; CMOS integrated circuits; operational amplifiers; resonator filters; switching convertors; CMOS digital integrated circuits; DC-DC power convertors; analogue-digital
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Integrated circuits and systems for wireless communications have fundamentally changed the way we live within the span of a few decades. With the help of process technology evolution, various systems in the 0.1~60 GHz frequency range have been commercialized, such as cellular telephones, wireless networks, radios for the internet of things, millimeter-wave transceivers for communication, and ultra-wide band networks. Moreover, extensive research on next-generation wireless communication systems, such as 6G radios and sub-THz transceivers, is already underway. The evolution of these integrated circuits and systems could accelerate the development and commercialization of next-generation wireless communication systems. This Special issue aims to offer an up-to-date overview of recent advances in wireless communication systems, focusing on the design and development of integrated circuits and systems. Topics of interest include, but are not limited to:

  • RF or baseband integrated circuit designs;
  • RF or baseband components for wireless communication;
  • Integrated circuits or peripheral circuits for RF systems;
  • Design strategy for highly efficient wireless communications;
  • New techniques to improve the efficiency of wireless systems;
  • Wireless communication applications.

Prof. Dr. Young-Kyun Cho
Guest Editor

Manuscript Submission Information

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Keywords

  • RF or baseband integrated circuit designs
  • RF or baseband components for wireless communication
  • integrated circuits or peripheral circuits for RF systems
  • design strategy for highly efficient wireless communications
  • new techniques to improve the efficiency of wireless systems
  • wireless communication applications

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Published Papers (3 papers)

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14 pages, 6495 KiB  
Article
Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response
by Mali Gao, Xiaowu Cai, Yuexin Gao, Ruirui Xia and Bo Li
Electronics 2023, 12(6), 1409; https://doi.org/10.3390/electronics12061409 - 15 Mar 2023
Cited by 5 | Viewed by 3222
Abstract
Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output [...] Read more.
Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1 kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively. Full article
(This article belongs to the Special Issue Design of CMOS Integrated, Circuits and Systems for Wireless Communications)
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11 pages, 4446 KiB  
Article
A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique
by Junjie Wu, Honglin Xu, Xu Cao and Tao Liu
Electronics 2022, 11(23), 3979; https://doi.org/10.3390/electronics11233979 - 30 Nov 2022
Cited by 2 | Viewed by 1970
Abstract
In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is [...] Read more.
In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude. Full article
(This article belongs to the Special Issue Design of CMOS Integrated, Circuits and Systems for Wireless Communications)
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13 pages, 5890 KiB  
Article
A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias
by Yange Lu, Ming Chen, Kunyu Wang, Yanjun Yang and Haiyong Wang
Electronics 2022, 11(19), 3009; https://doi.org/10.3390/electronics11193009 - 22 Sep 2022
Cited by 3 | Viewed by 3737
Abstract
The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly [...] Read more.
The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively. Full article
(This article belongs to the Special Issue Design of CMOS Integrated, Circuits and Systems for Wireless Communications)
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