Search Results (46)

The substantially lower breakdown electric field of Si compared to GaN necessitates thick buffer layers in Si-based GaN power devices for medium-voltage applications, significantly increasing cost. Recently, sapphire substrates, offering high electrical insulation and excellent mechanical strength, have emerged as a promising alternative. In this work, we demonstrate a CMOS-compatible process for sapphire-based GaN MIS-HEMTs utilizing a thin buffer layer. The fabricated devices with a W_G of 20.4 mm and an L_GD of 24 μm achieve a high off-state breakdown voltage >1650 V and a maximum on-state current > 4.1 A, with tight statistical distributions of V_TH and R_ON across the wafer. Furthermore, statistical characterization results of dynamic R_ON and leakage current under electrical stress conditions at both room temperature and 150 °C, confirm operational viability at high temperatures. Finally, long-term reliability for 650 V operation is validated by high-temperature reverse bias (HTRB) accelerated aging tests. Full article

The thickness of the LPCVD-Si₃N₄ gate dielectric layer significantly influences the electron transport properties of AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs), but the mechanism by which it affects polarization Coulomb field (PCF) scattering remains largely unexplored. In this study, AlGaN/GaN MIS-HEMTs with LPCVD-Si₃N₄ gate dielectric thicknesses of 0 nm, 5 nm, and 20 nm were fabricated, and the influence of LPCVD-Si₃N₄ thickness on PCF scattering was systematically investigated. Through electrical measurements and theoretical calculations, the relationship between LPCVD-Si₃N₄ gate dielectric layer thickness, additional polarization charge (∆ρ), two-dimensional electron gas (2DEG) density, and 2DEG mobility was analyzed. The results show that increasing the LPCVD-Si₃N₄ thickness reduces the vertical electric field in the AlGaN barrier, weakening the inverse piezoelectric effect (IPE) and reducing ∆ρ. Further analysis reveals that the ∆ρ exhibits a non-monotonic dependence on negative gate voltage, initially increasing and subsequently decreasing, due to the competition between strain accumulation and stress relaxation. Meanwhile, the 2DEG mobility limited by PCF (μ_PCF) decreases monotonically with increasing negative gate voltage, mainly due to the progressive weakening of the 2DEG screening effect. The research results reveal the physical mechanism by which LPCVD-Si₃N₄ thickness regulates PCF scattering, providing theoretical guidance for optimizing gate dielectric parameters and enhancing the performance of AlGaN/GaN MIS-HEMTs. Full article

A dual Al₂O₃ MIS gate structure is proposed to enhance the DC and RF performance of enhancement-mode GaN high-electron mobility transistors (HEMTs). As a result, the proposed MOS-HEMT with a dual recessed MIS gate structure offers 84% improvements in cutoff frequency (f_T) and 92% improvements in maximum oscillation frequency (f_max) compared to conventional HEMTs (from 7.1 GHz to 13.1 GHz and 17.5 GHz to 33.6 GHz, respectively). As for direct-current characteristics, a remarkable reduction in off-state gate leakage current and a 26% enhancement in the maximum saturation drain current (from 519 mA·mm⁻¹ to 658 A·mm⁻¹) are manifested in HEMTs with new structures. The maximum transconductance (g_m) is also raised from 209 mS·mm⁻¹ to 246 mS·mm⁻¹. Correspondingly, almost unchanged gate–source capacitance curves and gate–drain capacitance curves are also discussed to explain the electrical characteristic mechanism. These results indicate the superiority of using a dual Al₂O₃ MIS gate structure in GaN-based HEMTs to promote the RF and DC performance, providing a reference for further development in a miniwatt antenna amplifier and sub-6G frequencies of operation. Full article

This study introduces an enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) featuring a self-aligned p-GaN gate structure, fabricated using a gate-first process. The key innovation of this work lies in simplifying the fabrication process by utilizing gate metallization for both electrical contact and etching mask functions, enabling precise self-alignment. A highly selective Cl₂/N₂/O₂ inductively coupled plasma (ICP) etching process was optimized to etch the p-GaN layer in the access regions, with a selectivity ratio of 33:1 and minimal damage to the AlGaN barrier. Additionally, a novel, non-annealed ohmic contact formation technique was developed, leveraging ICP etching to create nitrogen vacancies that facilitate contact formation without requiring thermal annealing. This technique streamlines the process by combining ohmic contact formation and mesa isolation into a single lithographic step. Incorporating a SiNx gate dielectric layer led to a 4.5 V threshold voltage shift in the fabricated devices. The resulting devices exhibited improved electrical performance, including a wide gate voltage swing (>10 V), a high on/off current ratio (~10⁷), and clear pinch-off characteristics. These results demonstrate the effectiveness of the proposed fabrication approach, offering significant improvements in process efficiency and manufacturability. Full article

This study employed low-pressure chemical vapor deposition (LPCVD) SiN_x as both the gate dielectric layer and surface passivation layer, systematically investigating the effects of different growth conditions on the dielectric layer quality, two-dimensional electron gas (2DEG) characteristics, interface trap density, and devices’ performance, thereby optimizing the growth parameters of LPCVD SiN_x. The experiment investigated the effects of growth parameters such as the growth temperature, chamber pressure, and gas flow ratio on the growth rate of SiN_x during the process of growing SiN_x using the LPCVD technique. Further studies were performed to analyze the impact of SiN_x introduction on the 2DEG performance. The results indicated that both Si-rich and N-rich SiN_x compositions could enhance the 2DEG density improvement induced by SiN_x passivation. The impact of the gas flow ratio on the interface trap density is studied. Through the quantitative characterization of the interface trap density using the pulse-mode I_DS-V_GS method and frequency-dependent capacitance–voltage (C-V) measurement, the results show that the interface trap density decreases with an increased Si-to-N ratio. Full article

With the growing demand for more efficient power conversion and silicon reaching its theoretical limit, wide bandgap semiconductor devices are emerging as a potential solution. For instance, Gallium Nitride (GaN)-based high-electron-mobility transistors (HEMTs) are getting more attention, and several structures for the normally off operation have been proposed. Adding an AlN interlayer in conventional AlGaN/GaN normally on HEMT structures is known to enhance the current density. In this work, the effect of an AlN interlayer in the normally off AlGaN/GaN MISHEMT with a buried p-region was investigated using a TCAD simulation from Silvaco. The added AlN interlayer increases the two-dimensional electron gas density, requiring a higher p-doping concentration to achieve the same threshold voltage. The simulation results show that the overall effect is a reduction in the device’s current density and peak transconductance by 21.83% and 44.4%, respectively. Further analysis of the current profile shows that because of the buried p-region and at high gate voltages, the current flows near the AlGaN/GaN interface and along the insulator/AlGaN interface. Adding an AlN interface blocks the migration of channel electrons to the insulator/AlGaN interface, resulting in a lower current density. Full article

Devices under semi-on-state stress often suffer from more severe current collapse than when they are in the off-state, which causes an increase in dynamic on-resistance. Therefore, characterization of the trap states is necessary. In this study, temperature-dependent transient recovery current analysis determined a trap energy level of 0.08 eV under semi-on-state stress, implying that interface traps are responsible for current collapse. Multi-frequency capacitance–voltage (C-V) testing was performed on the MIS diode, calculating that interface trap density is in the range of $1.37\times {10}^{13}$ to $6.07\times {10}^{12}$${\mathrm{cm}}^{-2}$${\mathrm{eV}}^{-1}$ from $E_C-E_T=0.29$ eV to 0.45 eV. Full article

A comprehensive study of proton irradiation reliability on a bilayer dielectrics SiN_x/Al₂O₃ MIS-HEMT, the common Schottky gate HEMT, and a single dielectric layer MIS-HEMT with SiN_x and with Al₂O₃ for comparison is conducted in this paper. Combining the higher displacement threshold energy of Al₂O₃ with the better surface passivation of the SiN_x layer, the bilayer dielectrics MIS-HEMT presents much smaller degradation of structural materials and of device electrical performance after proton irradiation. Firstly, the least of the defects caused by irradiation suggesting the smallest structural material degradation is observed in the bilayer dielectrics MIS-HEMT through simulations. Then, DC and RF electrical performance of four kinds of devices before and after proton irradiation are studied through simulation and experiments. The smallest threshold voltage degradation rate, the smallest maximum on-current degradation and Gm degradation, the largest cut-off frequency, and the lowest cut-off frequency degradation are found in the bilayer dielectrics MIS-HEMT among four kinds of devices. The degradation results of both structural materials and electrical performance reveal that the bilayer dielectrics MIS-HEMT performs best after irradiation and had better radiation resilience. Full article

The V_th stability and gate reliability of AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) with alternating O₂ plasma treatment were systematically investigated in this article. It was found that the conduction band offset at the Al₂O₃/AlGaN interface was elevated to 2.4 eV, which contributed to the suppressed gate leakage current. The time-dependent dielectric breakdown (TDDB) test results showed that the ALD-Al₂O₃ with the alternating O₂ plasma treatment had better quality and reliability. The AlGaN/GaN MIS-HEMT with the alternating O₂ plasma treatment demonstrated remarkable advantages in higher V_th stability under high-temperature and long-term gate bias stress. Full article

This article presents the utilization of the chemical–mechanical polishing (CMP) method to fabricate high-performance N-polar GaN/AlGaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) through layer transfer technology. The nucleation and buffer layers were removed via CMP to attain a pristine N-polar GaN surface with elevated smoothness, featuring a low root-mean-square (RMS) roughness of 0.216 nm. Oxygen, carbon, and chlorine impurity elements content were low after the CMP process, as detected via X-ray photoelectron spectroscopy (XPS). The electrical properties of N-polar HEMTs fabricated via CMP exhibited a sheet resistance (R_sh) of 244.7 Ω/sq, a mobility of 1230 cm²/V·s, and an n_s of 2.24 × 10¹³ cm⁻². Compared with a counter device fabricated via inductively coupled plasma (ICP) dry etching, the CMP devices showed an improved output current of 756.1 mA/mm, reduced on-resistance of 6.51 Ω·mm, and a significantly reduced subthreshold slope mainly attributed to the improved surface conditions. Meanwhile, owing to the MIS configuration, the reverse gate leakage current could be reduced to as low as 15 μA/mm. These results highlight the feasibility of the CMP-involved epitaxial layer transfer (ELT) technique to deliver superior N-polar GaN MIS-HEMTs for power electronic applications. Full article

In this paper, the degradation behaviors of the ferroelectric gate Gallium nitride (GaN) high electron mobility transistor (HEMT) under positive gate bias stress are discussed. Devices with a gate dielectric that consists of pure Pb(Zr,Ti)O₃ (PZT) and a composite PZT/Al₂O₃ bilayer are studied. Two different mechanisms, charge trapping and generation of traps, both contribute to the degradation. We have observed positive threshold voltage shift in both kinds of devices under positive gate bias stress. In the devices with a PZT gate oxide, we have found the degradation is owing to electron trapping in pre-existing oxide traps. However, the degradation is caused by electron trapping in pre-existing oxide traps and the generation of traps for the devices with a composite PZT/Al₂O₃ gate oxide. Owing to the large difference in dielectric constants between PZT and Al₂O₃, the strong electric field in the Al₂O₃ interlayer makes PZT/Al₂O₃ GaN HEMT easier to degrade. In addition, the ferroelectricity in PZT enhances the electric field in Al₂O₃ interlayer and leads to more severe degradation. According to this study, it is worth noting that the reliability problem of the ferroelectric gate GaN HEMT may be more severe than the conventional metal–insulator–semiconductor HEMT (MIS-HEMT). Full article

As wide bandgap semiconductors, gallium nitride (GaN) lateral high-electron-mobility transistors (HEMTs) possess high breakdown voltage, low resistance and high frequency performance. PGaN gate HEMTs are promising candidates for high-voltage, high-power applications due to the normally off operation and robust gate reliability. However, the threshold and gate-breakdown voltages are relatively low compared with Si-based and SiC-based power MOSFETs. The epitaxial layers and device structures were optimized to enhance the main characteristics of pGaN HEMTs. In this work, various methods to improve threshold and gate-breakdown voltages are presented, such as the top-layer optimization of the pGaN cap, hole-concentration enhancement, the low-work-function gate electrode, and the MIS-type pGaN gate. The discussion of the main gate characteristic enhancement of p-type GaN gate HEMTs would accelerate the development of GaN power electronics to some extent. Full article

GaN devices are nowadays attracting global attention due to their outstanding performance in high voltage, high frequency, and anti-radiation ability. Research on total ionizing dose and annealing effects on E-mode GaN Cascode devices has been carried out. The Cascode device consists of a low-voltage MOSFET and a high-voltage depletion-mode GaN MISHEMT. Cascode devices of both conventional processed MOSFET and radiation-hardened MOSFET devices are fabricated to observe the TID effects. Experiment results indicate that, for the Cascode device with conventional processed MOSFET, the V_TH shifts to negative values at 100 krad(Si). For the Cascode device with radiation-hardened MOSFET, the V_TH shifts by −0.5 V at 100 krad(Si), while shifts to negative values are 500 krad(Si). The annealing process, after the TID experiment, shows that it can release trapped charges and help V_TH recover. On one hand, the V_TH shift and recover trends are similar to those of a single MOSFET device, suggesting that the MOSFET is the vulnerable part in the Cascode which determines the anti-TID ability of the device. On the other hand, the V_TH shift amount of the Cascode device is much larger than that of a previously reported p-GaN HEMT device, indicating that GaN material shows a better anti-TID ability than Si. Full article

A typical method for normally-off operation, the metal–insulator–semiconductor-high electron mobility transistor (MIS-HEMT) has been investigated. Among various approaches, gate recessed MIS-HEMT have demonstrated a high gate voltage sweep and low leakage current characteristics. Despite their high performance, obtaining low-damage techniques in gate recess processing has so far proven too challenging. In this letter, we demonstrate a high current density and high breakdown down voltage of a MIS-HEMT with a recessed gate by the low damage gate recessed etching of atomic layer etching (ALE) technology. After the remaining 3.7 nm of the AlGaN recessed gate was formed, the surface roughness (Ra of 0.40 nm) was almost the same as the surface without ALE (no etching) as measured by atomic force microscopy (AFM). Furthermore, the devices demonstrate state-of-the-art characteristics with a competitive maximum drain current of 608 mA/mm at a V_G of 6 V and a threshold voltage of +2.0 V. The devices also show an on/off current ratio of 10⁹ and an off-state hard breakdown voltage of 1190 V. The low damage of ALE technology was introduced into the MIS-HEMT with the recessed gate, which effectively reduced trapping states at the interface to obtain the low on-resistance (R_on) of 6.8 Ω·mm and high breakdown voltage performance. Full article

A novel atomic-level post-etch-surface-reinforcement (PESR) process is developed to recover the p-GaN etching induced damage region for high performance p-GaN gate HEMTs fabrication. This process is composed of a self-limited surface modification step with O₂ plasma, following by an oxide removal step with BCl₃ plasma. With PESR process, the AlGaN surface morphology after p-GaN etching was comparable to the as-epitaxial level by AFM characterization, and the AlGaN lattice crystallization was also recovered which was measured in a confocal Raman system. The electrical measurement further confirmed the significant improvement of AlGaN surface quality, with one-order of magnitude lower surface leakage in a metal-semiconductor (MS) Schottky-diode and 6 times lower interface density of states (D_it) in a MIS C-V characterization. The XPS analysis of Al₂O₃/AlGaN showed that the p-GaN etching induced F-byproduct and Ga-oxide was well removed and suppressed by PESR process. Finally, the developed PESR process was successfully integrated in p-GaN gate HEMTs fabrication, and the device performance was significantly enhanced with ~20% lower of on-resistance and ~25% less of current collapse at V_ds,Q bias of 40 V, showing great potential of leverage p-GaN gate HEMTs reliability. Full article